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author | Tom Rini | 2022-05-25 09:50:08 -0400 |
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committer | Tom Rini | 2022-05-25 09:50:08 -0400 |
commit | 661f5400754750df4104b6466942c8b62897340d (patch) | |
tree | 5ccaa46280decbe9696b58344eaedf2b2893e3cc /test/py | |
parent | 7e0edcadb09d55d5319fdc862041fd1b874476f5 (diff) | |
parent | 594f692f491f0def6c4b6543e158a7f367b35dcc (diff) |
Merge tag 'xilinx-for-v2022.07-rc4' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2022.07-rc4
zynqmp:
- Fix DP PLL configuration for zcu102/zcu106 and SOM
- Fix split mode for starting R5s
- DT fixes
- Remove firmware node for mini configurations
- Wire TEE for multi DTB fit image
xilinx:
- Handle board_get_usable_ram_top(0) properly
phy:
- Extend psgtr timeout
mmc:
- Fix mini configuration which misses zynqmp_pm_is_function_supported()
Diffstat (limited to 'test/py')
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