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authorPragnesh Patel2020-05-29 11:33:31 +0530
committerAndes2020-06-04 09:44:09 +0800
commit1ba43d29eb626ee813650baf12a72a31ed2bffca (patch)
tree75e44bd1e559f352c22db58aa48d1598028dcb1b /tools/omapimage.h
parent378c7094afb0219ef11271e427f2e80753722ba8 (diff)
clk: sifive: fu540-prci: Release ethernet clock reset
U-Boot ethernet works with FSBL flow where releasing ethernet clock reset is part of FSBL itself but with the SPL, We need to release ethernet clock reset explicitly for U-Boot proper. With this change Release ethernet clock reset code in FSBL might not be needed or unaffected. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
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