diff options
50 files changed, 1578 insertions, 2 deletions
diff --git a/arch/mips/dts/Makefile b/arch/mips/dts/Makefile index 840dbf170dc..e80905cf3a5 100644 --- a/arch/mips/dts/Makefile +++ b/arch/mips/dts/Makefile @@ -15,6 +15,7 @@ dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb dtb-$(CONFIG_BOARD_COMTREND_WAP5813N) += comtrend,wap-5813n.dtb dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb +dtb-$(CONFIG_BOARD_NETGEAR_DGND3700V2) += netgear,dgnd3700v2.dtb dtb-$(CONFIG_BOARD_SAGEM_FAST1704) += sagem,f@st1704.dtb dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb diff --git a/arch/mips/dts/brcm,bcm6318.dtsi b/arch/mips/dts/brcm,bcm6318.dtsi index 54964a70098..015acc91735 100644 --- a/arch/mips/dts/brcm,bcm6318.dtsi +++ b/arch/mips/dts/brcm,bcm6318.dtsi @@ -153,5 +153,35 @@ reg = <0x10004000 0x38>; u-boot,dm-pre-reloc; }; + + ehci: usb-controller@10005000 { + compatible = "brcm,bcm6318-ehci", "generic-ehci"; + reg = <0x10005000 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + ohci: usb-controller@10005100 { + compatible = "brcm,bcm6318-ohci", "generic-ohci"; + reg = <0x10005100 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + usbh: usb-phy@10005200 { + compatible = "brcm,bcm6318-usbh"; + reg = <0x10005200 0x30>; + #phy-cells = <0>; + clocks = <&periph_clk BCM6318_CLK_USB>; + clock-names = "usbh"; + power-domains = <&periph_pwr BCM6318_PWR_USB>; + resets = <&periph_rst BCM6318_RST_USBH>; + + status = "disabled"; + }; }; }; diff --git a/arch/mips/dts/brcm,bcm63268.dtsi b/arch/mips/dts/brcm,bcm63268.dtsi index 4d4e36ccccf..ade0b49e68a 100644 --- a/arch/mips/dts/brcm,bcm63268.dtsi +++ b/arch/mips/dts/brcm,bcm63268.dtsi @@ -183,6 +183,36 @@ status = "disabled"; }; + ehci: usb-controller@10002500 { + compatible = "brcm,bcm63268-ehci", "generic-ehci"; + reg = <0x10002500 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + ohci: usb-controller@10002600 { + compatible = "brcm,bcm63268-ohci", "generic-ohci"; + reg = <0x10002600 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + usbh: usb-phy@10002700 { + compatible = "brcm,bcm63268-usbh"; + reg = <0x10002700 0x38>; + #phy-cells = <0>; + clocks = <&periph_clk BCM63268_CLK_USBH>, <&timer_clk BCM63268_TCLK_USB_REF>; + clock-names = "usbh", "usb_ref"; + power-domains = <&periph_pwr BCM63268_PWR_USBH>; + resets = <&periph_rst BCM63268_RST_USBH>; + + status = "disabled"; + }; + memory-controller@10003000 { compatible = "brcm,bcm6328-mc"; reg = <0x10003000 0x894>; diff --git a/arch/mips/dts/brcm,bcm6328.dtsi b/arch/mips/dts/brcm,bcm6328.dtsi index 67d9278be49..4fbbcec1530 100644 --- a/arch/mips/dts/brcm,bcm6328.dtsi +++ b/arch/mips/dts/brcm,bcm6328.dtsi @@ -153,6 +153,36 @@ #power-domain-cells = <1>; }; + ehci: usb-controller@10002500 { + compatible = "brcm,bcm6328-ehci", "generic-ehci"; + reg = <0x10002500 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + ohci: usb-controller@10002600 { + compatible = "brcm,bcm6328-ohci", "generic-ohci"; + reg = <0x10002600 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + usbh: usb-phy@10002700 { + compatible = "brcm,bcm6328-usbh"; + reg = <0x10002700 0x38>; + #phy-cells = <0>; + clocks = <&periph_clk BCM6328_CLK_USBH>; + clock-names = "usbh"; + power-domains = <&periph_pwr BCM6328_PWR_USBH>; + resets = <&periph_rst BCM6328_RST_USBH>; + + status = "disabled"; + }; + memory-controller@10003000 { compatible = "brcm,bcm6328-mc"; reg = <0x10003000 0x864>; diff --git a/arch/mips/dts/brcm,bcm6348.dtsi b/arch/mips/dts/brcm,bcm6348.dtsi index 540b9fea5ba..92fb91afc1b 100644 --- a/arch/mips/dts/brcm,bcm6348.dtsi +++ b/arch/mips/dts/brcm,bcm6348.dtsi @@ -135,6 +135,26 @@ status = "disabled"; }; + ohci: usb-controller@fffe1b00 { + compatible = "brcm,bcm6348-ohci", "generic-ohci"; + reg = <0xfffe1b00 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + usbh: usb-phy@fffe1c00 { + compatible = "brcm,bcm6348-usbh"; + reg = <0xfffe1c00 0x4>; + #phy-cells = <0>; + clocks = <&periph_clk BCM6348_CLK_USBH>; + clock-names = "usbh"; + resets = <&periph_rst BCM6348_RST_USBH>; + + status = "disabled"; + }; + memory-controller@fffe2300 { compatible = "brcm,bcm6338-mc"; reg = <0xfffe2300 0x38>; diff --git a/arch/mips/dts/brcm,bcm6358.dtsi b/arch/mips/dts/brcm,bcm6358.dtsi index 1662783279f..b63b53baee7 100644 --- a/arch/mips/dts/brcm,bcm6358.dtsi +++ b/arch/mips/dts/brcm,bcm6358.dtsi @@ -164,5 +164,32 @@ reg = <0xfffe1200 0x4c>; u-boot,dm-pre-reloc; }; + + ehci: usb-controller@fffe1300 { + compatible = "brcm,bcm6358-ehci", "generic-ehci"; + reg = <0xfffe1300 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + ohci: usb-controller@fffe1400 { + compatible = "brcm,bcm6358-ohci", "generic-ohci"; + reg = <0xfffe1400 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + usbh: usb-phy@fffe1500 { + compatible = "brcm,bcm6358-usbh"; + reg = <0xfffe1500 0x28>; + #phy-cells = <0>; + resets = <&periph_rst BCM6358_RST_USBH>; + + status = "disabled"; + }; }; }; diff --git a/arch/mips/dts/brcm,bcm6362.dtsi b/arch/mips/dts/brcm,bcm6362.dtsi new file mode 100644 index 00000000000..f695ec32535 --- /dev/null +++ b/arch/mips/dts/brcm,bcm6362.dtsi @@ -0,0 +1,216 @@ +/* + * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dt-bindings/clock/bcm6362-clock.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/power-domain/bcm6362-power-domain.h> +#include <dt-bindings/reset/bcm6362-reset.h> +#include "skeleton.dtsi" + +/ { + compatible = "brcm,bcm6362"; + + aliases { + spi0 = &lsspi; + spi1 = &hsspi; + }; + + cpus { + reg = <0x10000000 0x4>; + #address-cells = <1>; + #size-cells = <0>; + u-boot,dm-pre-reloc; + + cpu@0 { + compatible = "brcm,bcm6362-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <0>; + u-boot,dm-pre-reloc; + }; + + cpu@1 { + compatible = "brcm,bcm6362-cpu", "mips,mips4Kc"; + device_type = "cpu"; + reg = <1>; + u-boot,dm-pre-reloc; + }; + }; + + clocks { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + hsspi_pll: hsspi-pll { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <133333333>; + }; + + periph_osc: periph-osc { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + u-boot,dm-pre-reloc; + }; + + periph_clk: periph-clk { + compatible = "brcm,bcm6345-clk"; + reg = <0x10000004 0x4>; + #clock-cells = <1>; + }; + }; + + ubus { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + u-boot,dm-pre-reloc; + + pll_cntl: syscon@10000008 { + compatible = "syscon"; + reg = <0x10000008 0x4>; + }; + + syscon-reboot { + compatible = "syscon-reboot"; + regmap = <&pll_cntl>; + offset = <0x0>; + mask = <0x1>; + }; + + periph_rst: reset-controller@10000010 { + compatible = "brcm,bcm6345-reset"; + reg = <0x10000010 0x4>; + #reset-cells = <1>; + }; + + wdt: watchdog@1000005c { + compatible = "brcm,bcm6345-wdt"; + reg = <0x1000005c 0xc>; + clocks = <&periph_osc>; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdt>; + }; + + gpio1: gpio-controller@10000080 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x10000080 0x4>, <0x10000088 0x4>; + gpio-controller; + #gpio-cells = <2>; + ngpios = <16>; + + status = "disabled"; + }; + + gpio0: gpio-controller@10000084 { + compatible = "brcm,bcm6345-gpio"; + reg = <0x10000084 0x4>, <0x1000008c 0x4>; + gpio-controller; + #gpio-cells = <2>; + + status = "disabled"; + }; + + uart0: serial@10000100 { + compatible = "brcm,bcm6345-uart"; + reg = <0x10000100 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + uart1: serial@10000120 { + compatible = "brcm,bcm6345-uart"; + reg = <0x10000120 0x18>; + clocks = <&periph_osc>; + + status = "disabled"; + }; + + lsspi: spi@10000800 { + compatible = "brcm,bcm6358-spi"; + reg = <0x10000800 0x70c>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&periph_clk BCM6362_CLK_SPI>; + resets = <&periph_rst BCM6362_RST_SPI>; + spi-max-frequency = <20000000>; + num-cs = <8>; + + status = "disabled"; + }; + + hsspi: spi@10001000 { + compatible = "brcm,bcm6328-hsspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x10001000 0x600>; + clocks = <&periph_clk BCM6362_CLK_HSSPI>, <&hsspi_pll>; + clock-names = "hsspi", "pll"; + resets = <&periph_rst BCM6362_RST_SPI>; + spi-max-frequency = <50000000>; + num-cs = <8>; + + status = "disabled"; + }; + + leds: led-controller@10001900 { + compatible = "brcm,bcm6328-leds"; + reg = <0x10001900 0x24>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + periph_pwr: power-controller@10001848 { + compatible = "brcm,bcm6328-power-domain"; + reg = <0x10001848 0x4>; + #power-domain-cells = <1>; + }; + + ehci: usb-controller@10002500 { + compatible = "brcm,bcm6362-ehci", "generic-ehci"; + reg = <0x10002500 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + ohci: usb-controller@10002600 { + compatible = "brcm,bcm6362-ohci", "generic-ohci"; + reg = <0x10002600 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + usbh: usb-phy@10002700 { + compatible = "brcm,bcm6368-usbh"; + reg = <0x10002700 0x38>; + #phy-cells = <0>; + clocks = <&periph_clk BCM6362_CLK_USBH>; + clock-names = "usbh"; + power-domains = <&periph_pwr BCM6362_PWR_USBH>; + resets = <&periph_rst BCM6362_RST_USBH>; + + status = "disabled"; + }; + + memory-controller@10003000 { + compatible = "brcm,bcm6328-mc"; + reg = <0x10003000 0x864>; + u-boot,dm-pre-reloc; + }; + }; +}; diff --git a/arch/mips/dts/brcm,bcm6368.dtsi b/arch/mips/dts/brcm,bcm6368.dtsi index 1bb538a1f34..fc1c5a244f0 100644 --- a/arch/mips/dts/brcm,bcm6368.dtsi +++ b/arch/mips/dts/brcm,bcm6368.dtsi @@ -164,5 +164,34 @@ reg = <0x10001200 0x4c>; u-boot,dm-pre-reloc; }; + + ehci: usb-controller@10001500 { + compatible = "brcm,bcm6368-ehci", "generic-ehci"; + reg = <0x10001500 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + ohci: usb-controller@10001600 { + compatible = "brcm,bcm6368-ohci", "generic-ohci"; + reg = <0x10001600 0x100>; + phys = <&usbh>; + big-endian; + + status = "disabled"; + }; + + usbh: usb-phy@10001700 { + compatible = "brcm,bcm6368-usbh"; + reg = <0x10001700 0x38>; + #phy-cells = <0>; + clocks = <&periph_clk BCM6368_CLK_USBH>; + clock-names = "usbh"; + resets = <&periph_rst BCM6368_RST_USBH>; + + status = "disabled"; + }; }; }; diff --git a/arch/mips/dts/comtrend,ar-5315u.dts b/arch/mips/dts/comtrend,ar-5315u.dts index 4e4d69b6384..af3159a03af 100644 --- a/arch/mips/dts/comtrend,ar-5315u.dts +++ b/arch/mips/dts/comtrend,ar-5315u.dts @@ -21,6 +21,10 @@ }; }; +&ehci { + status = "okay"; +}; + &leds { status = "okay"; @@ -67,6 +71,10 @@ }; }; +&ohci { + status = "okay"; +}; + &spi { status = "okay"; @@ -83,3 +91,7 @@ u-boot,dm-pre-reloc; status = "okay"; }; + +&usbh { + status = "okay"; +}; diff --git a/arch/mips/dts/comtrend,ar-5387un.dts b/arch/mips/dts/comtrend,ar-5387un.dts index 6067881a78a..3a97315b3fb 100644 --- a/arch/mips/dts/comtrend,ar-5387un.dts +++ b/arch/mips/dts/comtrend,ar-5387un.dts @@ -21,6 +21,10 @@ }; }; +&ehci { + status = "okay"; +}; + &leds { status = "okay"; @@ -51,6 +55,10 @@ }; }; +&ohci { + status = "okay"; +}; + &spi { status = "okay"; @@ -67,3 +75,7 @@ u-boot,dm-pre-reloc; status = "okay"; }; + +&usbh { + status = "okay"; +}; diff --git a/arch/mips/dts/comtrend,ct-5361.dts b/arch/mips/dts/comtrend,ct-5361.dts index c909a528a97..74dc09046ce 100644 --- a/arch/mips/dts/comtrend,ct-5361.dts +++ b/arch/mips/dts/comtrend,ct-5361.dts @@ -39,6 +39,10 @@ status = "okay"; }; +&ohci { + status = "okay"; +}; + &pflash { status = "okay"; }; @@ -47,3 +51,7 @@ u-boot,dm-pre-reloc; status = "okay"; }; + +&usbh { + status = "okay"; +}; diff --git a/arch/mips/dts/comtrend,vr-3032u.dts b/arch/mips/dts/comtrend,vr-3032u.dts index 54e738c8210..9bbecbcdff2 100644 --- a/arch/mips/dts/comtrend,vr-3032u.dts +++ b/arch/mips/dts/comtrend,vr-3032u.dts @@ -21,6 +21,10 @@ }; }; +&ehci { + status = "okay"; +}; + &leds { status = "okay"; brcm,serial-leds; @@ -64,7 +68,15 @@ }; }; +&ohci { + status = "okay"; +}; + &uart0 { u-boot,dm-pre-reloc; status = "okay"; }; + +&usbh { + status = "okay"; +}; diff --git a/arch/mips/dts/comtrend,wap-5813n.dts b/arch/mips/dts/comtrend,wap-5813n.dts index 29386e2662e..f1f5430b422 100644 --- a/arch/mips/dts/comtrend,wap-5813n.dts +++ b/arch/mips/dts/comtrend,wap-5813n.dts @@ -51,10 +51,18 @@ }; }; +&ehci { + status = "okay"; +}; + &gpio0 { status = "okay"; }; +&ohci { + status = "okay"; +}; + &pflash { status = "okay"; }; @@ -63,3 +71,7 @@ u-boot,dm-pre-reloc; status = "okay"; }; + +&usbh { + status = "okay"; +}; diff --git a/arch/mips/dts/huawei,hg556a.dts b/arch/mips/dts/huawei,hg556a.dts index 31c7d7ed5ce..a1e9c15ab90 100644 --- a/arch/mips/dts/huawei,hg556a.dts +++ b/arch/mips/dts/huawei,hg556a.dts @@ -90,10 +90,18 @@ }; }; +&ehci { + status = "okay"; +}; + &gpio0 { status = "okay"; }; +&ohci { + status = "okay"; +}; + &pflash { status = "okay"; }; @@ -102,3 +110,7 @@ u-boot,dm-pre-reloc; status = "okay"; }; + +&usbh { + status = "okay"; +}; diff --git a/arch/mips/dts/netgear,dgnd3700v2.dts b/arch/mips/dts/netgear,dgnd3700v2.dts new file mode 100644 index 00000000000..8dc7d7ec328 --- /dev/null +++ b/arch/mips/dts/netgear,dgnd3700v2.dts @@ -0,0 +1,133 @@ +/* + * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include "brcm,bcm6362.dtsi" + +/ { + model = "Netgear DGND3700v2"; + compatible = "netgear,dgnd3700v2", "brcm,bcm6362"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-leds { + compatible = "gpio-leds"; + + inet_green { + label = "DGND3700v2:green:inet"; + gpios = <&gpio0 1 GPIO_ACTIVE_LOW>; + }; + + dsl_green { + label = "DGND3700v2:green:dsl"; + gpios = <&gpio0 28 GPIO_ACTIVE_LOW>; + }; + + power_amber { + label = "DGND3700v2:red:power"; + gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ehci { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&leds { + status = "okay"; + brcm,serial-leds; + brcm,serial-dat-low; + brcm,serial-shift-inv; + brcm,serial-mux; + + led@8 { + reg = <8>; + label = "DGND3700v2:green:power"; + }; + + led@9 { + reg = <9>; + active-low; + label = "DGND3700v2:green:wps"; + }; + + led@10 { + reg = <10>; + active-low; + label = "DGND3700v2:green:usb1"; + }; + + led@11 { + reg = <11>; + active-low; + label = "DGND3700v2:green:usb2"; + }; + + led@12 { + reg = <12>; + active-low; + label = "DGND3700v2:amber:inet"; + }; + + led@13 { + reg = <13>; + active-low; + label = "DGND3700v2:green:ethernet"; + }; + + led@14 { + reg = <14>; + active-low; + label = "DGND3700v2:amber:dsl"; + }; + + led@16 { + reg = <16>; + active-low; + label = "DGND3700v2:amber:usb1"; + }; + + led@17 { + reg = <17>; + active-low; + label = "DGND3700v2:amber:usb2"; + }; + + led@18 { + reg = <18>; + active-low; + label = "DGND3700v2:amber:ethernet"; + }; +}; + +&ohci { + status = "okay"; +}; + +&uart0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usbh { + status = "okay"; +}; diff --git a/arch/mips/dts/sfr,nb4-ser.dts b/arch/mips/dts/sfr,nb4-ser.dts index f2092e9f999..473372faa18 100644 --- a/arch/mips/dts/sfr,nb4-ser.dts +++ b/arch/mips/dts/sfr,nb4-ser.dts @@ -50,6 +50,10 @@ }; }; +&ehci { + status = "okay"; +}; + &gpio0 { status = "okay"; }; @@ -83,6 +87,10 @@ }; }; +&ohci { + status = "okay"; +}; + &pflash { status = "okay"; }; @@ -91,3 +99,7 @@ u-boot,dm-pre-reloc; status = "okay"; }; + +&usbh { + status = "okay"; +}; diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig index e4a0118368d..10900bf6045 100644 --- a/arch/mips/mach-bmips/Kconfig +++ b/arch/mips/mach-bmips/Kconfig @@ -12,6 +12,7 @@ config SYS_SOC default "bcm6348" if SOC_BMIPS_BCM6348 default "bcm6358" if SOC_BMIPS_BCM6358 default "bcm6368" if SOC_BMIPS_BCM6368 + default "bcm6362" if SOC_BMIPS_BCM6362 default "bcm63268" if SOC_BMIPS_BCM63268 choice @@ -94,6 +95,17 @@ config SOC_BMIPS_BCM6368 help This supports BMIPS BCM6368 family including BCM6368 and BCM6369. +config SOC_BMIPS_BCM6362 + bool "BMIPS BCM6362 family" + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select MIPS_TUNE_4KC + select MIPS_L1_CACHE_SHIFT_4 + select SWAP_IO_SPACE + select SYSRESET_SYSCON + help + This supports BMIPS BCM6362 family including BCM6361 and BCM6362. + config SOC_BMIPS_BCM63268 bool "BMIPS BCM63268 family" select SUPPORTS_BIG_ENDIAN @@ -188,6 +200,17 @@ config BOARD_NETGEAR_CG3100D ethernet ports, 1 UART, GPIO buttons and LEDs, and a BCM43225 (miniPCIe). +config BOARD_NETGEAR_DGND3700V2 + bool "Netgear DGND3700v2" + depends on SOC_BMIPS_BCM6362 + select BMIPS_SUPPORTS_BOOT_RAM + help + Netgear DGND3700v2 boards have a BCM6362 SoC with 64 MB of RAM and + 32 MB of flash (NAND). + Between its different peripherals there's a BCM53125 switch with 5 + ethernet ports, 2 USB ports, 1 UART, GPIO buttons and LEDs, and a + BCM43228 (miniPCIe). + config BOARD_SAGEM_FAST1704 bool "Sagem F@ST1704" depends on SOC_BMIPS_BCM6338 @@ -235,6 +258,7 @@ source "board/comtrend/vr3032u/Kconfig" source "board/comtrend/wap5813n/Kconfig" source "board/huawei/hg556a/Kconfig" source "board/netgear/cg3100d/Kconfig" +source "board/netgear/dgnd3700v2/Kconfig" source "board/sagem/f@st1704/Kconfig" source "board/sfr/nb4_ser/Kconfig" diff --git a/board/micronas/vct/scc.c b/board/micronas/vct/scc.c index 0d33cc4c28e..8dbf4100e70 100644 --- a/board/micronas/vct/scc.c +++ b/board/micronas/vct/scc.c @@ -524,12 +524,14 @@ int scc_setup_dma(enum scc_id id, u32 buffer_tag, struct scc_dma_state *dma_state; int return_value = 0; union scc_dma_cfg dma_cfg; - u32 *buffer_tag_list = scc_descriptor_table[id].buffer_tag_list; + u32 *buffer_tag_list; u32 tag_count, t, t_valid; if ((id >= SCC_MAX) || (id < 0)) return -EINVAL; + buffer_tag_list = scc_descriptor_table[id].buffer_tag_list; + /* if the register is only configured by hw, cannot write! */ if (1 == scc_descriptor_table[id].hw_dma_cfg) return -EACCES; diff --git a/board/netgear/dgnd3700v2/Kconfig b/board/netgear/dgnd3700v2/Kconfig new file mode 100644 index 00000000000..11af1887854 --- /dev/null +++ b/board/netgear/dgnd3700v2/Kconfig @@ -0,0 +1,12 @@ +if BOARD_NETGEAR_DGND3700V2 + +config SYS_BOARD + default "dgnd3700v2" + +config SYS_VENDOR + default "netgear" + +config SYS_CONFIG_NAME + default "netgear_dgnd3700v2" + +endif diff --git a/board/netgear/dgnd3700v2/MAINTAINERS b/board/netgear/dgnd3700v2/MAINTAINERS new file mode 100644 index 00000000000..998077b69be --- /dev/null +++ b/board/netgear/dgnd3700v2/MAINTAINERS @@ -0,0 +1,6 @@ +NETGEAR DGND3700V2 BOARD +M: Ãlvaro Fernández Rojas <noltari@gmail.com> +S: Maintained +F: board/netgear/dgnd3700v2/ +F: include/configs/netgear_dgnd3700v2.h +F: configs/netgear_dgnd3700v2_ram_defconfig diff --git a/board/netgear/dgnd3700v2/Makefile b/board/netgear/dgnd3700v2/Makefile new file mode 100644 index 00000000000..89fd6c89ebd --- /dev/null +++ b/board/netgear/dgnd3700v2/Makefile @@ -0,0 +1,5 @@ +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += dgnd3700v2.o diff --git a/board/netgear/dgnd3700v2/dgnd3700v2.c b/board/netgear/dgnd3700v2/dgnd3700v2.c new file mode 100644 index 00000000000..3ae7f6afbdb --- /dev/null +++ b/board/netgear/dgnd3700v2/dgnd3700v2.c @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> + +#define GPIO_BASE_6362 0x10000080 + +#define GPIO_MODE_6362_REG 0x18 +#define GPIO_MODE_6362_SERIAL_LED_DATA BIT(2) +#define GPIO_MODE_6362_SERIAL_LED_CLK BIT(3) + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + void __iomem *gpio_regs = map_physmem(GPIO_BASE_6362, 0, MAP_NOCACHE); + + /* Enable Serial LEDs */ + setbits_be32(gpio_regs + GPIO_MODE_6362_REG, + GPIO_MODE_6362_SERIAL_LED_DATA | + GPIO_MODE_6362_SERIAL_LED_CLK); + + return 0; +} +#endif diff --git a/configs/comtrend_ar5315u_ram_defconfig b/configs/comtrend_ar5315u_ram_defconfig index 892977a649b..6b2c3555fe6 100644 --- a/configs/comtrend_ar5315u_ram_defconfig +++ b/configs/comtrend_ar5315u_ram_defconfig @@ -27,7 +27,9 @@ CONFIG_CMD_MEMINFO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_SF=y CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y # CONFIG_CMD_MISC is not set +CONFIG_OF_EMBED=y # CONFIG_NET is not set # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_DM_GPIO=y @@ -38,7 +40,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_MTD=y -CONFIG_POWER_DOMAIN=y +CONFIG_PHY=y +CONFIG_BCM6318_USBH_PHY=y CONFIG_BCM6328_POWER_DOMAIN=y CONFIG_DM_RESET=y CONFIG_RESET_BCM6345=y @@ -47,3 +50,9 @@ CONFIG_DM_SERIAL=y CONFIG_BCM6345_SERIAL=y CONFIG_DM_SPI=y CONFIG_BCM63XX_HSSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y diff --git a/configs/comtrend_ar5387un_ram_defconfig b/configs/comtrend_ar5387un_ram_defconfig index 12dbf0bc27a..efccf9adec7 100644 --- a/configs/comtrend_ar5387un_ram_defconfig +++ b/configs/comtrend_ar5387un_ram_defconfig @@ -27,7 +27,9 @@ CONFIG_CMD_MEMINFO=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_SF=y CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y # CONFIG_CMD_MISC is not set +CONFIG_OF_EMBED=y # CONFIG_NET is not set # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_DM_GPIO=y @@ -38,6 +40,8 @@ CONFIG_DM_SPI_FLASH=y CONFIG_SPI_FLASH=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_MTD=y +CONFIG_PHY=y +CONFIG_BCM6368_USBH_PHY=y CONFIG_POWER_DOMAIN=y CONFIG_BCM6328_POWER_DOMAIN=y CONFIG_DM_RESET=y @@ -47,3 +51,9 @@ CONFIG_DM_SERIAL=y CONFIG_BCM6345_SERIAL=y CONFIG_DM_SPI=y CONFIG_BCM63XX_HSSPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y diff --git a/configs/comtrend_ct5361_ram_defconfig b/configs/comtrend_ct5361_ram_defconfig index 108e8ea267c..708dcda3ddd 100644 --- a/configs/comtrend_ct5361_ram_defconfig +++ b/configs/comtrend_ct5361_ram_defconfig @@ -24,7 +24,9 @@ CONFIG_CMD_LICENSE=y # CONFIG_CMD_CRC32 is not set CONFIG_CMD_MEMINFO=y # CONFIG_CMD_LOADS is not set +CONFIG_CMD_USB=y # CONFIG_CMD_MISC is not set +CONFIG_OF_EMBED=y # CONFIG_NET is not set # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_DM_GPIO=y @@ -34,9 +36,15 @@ CONFIG_LED_GPIO=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_CFI_FLASH=y +CONFIG_PHY=y +CONFIG_BCM6348_USBH_PHY=y CONFIG_DM_RESET=y CONFIG_RESET_BCM6345=y # CONFIG_SPL_SERIAL_PRESENT is not set CONFIG_DM_SERIAL=y CONFIG_BCM6345_SERIAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y CONFIG_WDT_BCM6345=y diff --git a/configs/comtrend_vr3032u_ram_defconfig b/configs/comtrend_vr3032u_ram_defconfig index 8149fabbc3e..3920f3381c3 100644 --- a/configs/comtrend_vr3032u_ram_defconfig +++ b/configs/comtrend_vr3032u_ram_defconfig @@ -25,13 +25,17 @@ CONFIG_CMD_LICENSE=y CONFIG_CMD_MEMINFO=y # CONFIG_CMD_FLASH is not set # CONFIG_CMD_LOADS is not set +CONFIG_CMD_USB=y # CONFIG_CMD_MISC is not set +CONFIG_OF_EMBED=y # CONFIG_NET is not set # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_DM_GPIO=y CONFIG_LED=y CONFIG_LED_BCM6328=y CONFIG_LED_BLINK=y +CONFIG_PHY=y +CONFIG_BCM6368_USBH_PHY=y CONFIG_POWER_DOMAIN=y CONFIG_BCM6328_POWER_DOMAIN=y CONFIG_DM_RESET=y @@ -39,3 +43,9 @@ CONFIG_RESET_BCM6345=y # CONFIG_SPL_SERIAL_PRESENT is not set CONFIG_DM_SERIAL=y CONFIG_BCM6345_SERIAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y diff --git a/configs/comtrend_wap5813n_ram_defconfig b/configs/comtrend_wap5813n_ram_defconfig index 6112725a81a..a9c00e9122e 100644 --- a/configs/comtrend_wap5813n_ram_defconfig +++ b/configs/comtrend_wap5813n_ram_defconfig @@ -24,7 +24,9 @@ CONFIG_CMD_LICENSE=y # CONFIG_CMD_CRC32 is not set CONFIG_CMD_MEMINFO=y # CONFIG_CMD_LOADS is not set +CONFIG_CMD_USB=y # CONFIG_CMD_MISC is not set +CONFIG_OF_EMBED=y # CONFIG_NET is not set # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_DM_GPIO=y @@ -34,8 +36,16 @@ CONFIG_LED_GPIO=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_CFI_FLASH=y +CONFIG_PHY=y +CONFIG_BCM6368_USBH_PHY=y CONFIG_DM_RESET=y CONFIG_RESET_BCM6345=y # CONFIG_SPL_SERIAL_PRESENT is not set CONFIG_DM_SERIAL=y CONFIG_BCM6345_SERIAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y diff --git a/configs/huawei_hg556a_ram_defconfig b/configs/huawei_hg556a_ram_defconfig index b9208ff325c..4a13de46642 100644 --- a/configs/huawei_hg556a_ram_defconfig +++ b/configs/huawei_hg556a_ram_defconfig @@ -24,7 +24,9 @@ CONFIG_CMD_LICENSE=y # CONFIG_CMD_CRC32 is not set CONFIG_CMD_MEMINFO=y # CONFIG_CMD_LOADS is not set +CONFIG_CMD_USB=y # CONFIG_CMD_MISC is not set +CONFIG_OF_EMBED=y # CONFIG_NET is not set # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_DM_GPIO=y @@ -34,8 +36,16 @@ CONFIG_LED_GPIO=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_CFI_FLASH=y +CONFIG_PHY=y +CONFIG_BCM6358_USBH_PHY=y CONFIG_DM_RESET=y CONFIG_RESET_BCM6345=y # CONFIG_SPL_SERIAL_PRESENT is not set CONFIG_DM_SERIAL=y CONFIG_BCM6345_SERIAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y diff --git a/configs/netgear_cg3100d_ram_defconfig b/configs/netgear_cg3100d_ram_defconfig index 595ad6cfaff..f1ceb5c2c76 100644 --- a/configs/netgear_cg3100d_ram_defconfig +++ b/configs/netgear_cg3100d_ram_defconfig @@ -27,6 +27,7 @@ CONFIG_CMD_MEMINFO=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y # CONFIG_CMD_MISC is not set +CONFIG_OF_EMBED=y # CONFIG_NET is not set # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_DM_GPIO=y diff --git a/configs/netgear_dgnd3700v2_ram_defconfig b/configs/netgear_dgnd3700v2_ram_defconfig new file mode 100644 index 00000000000..496833683de --- /dev/null +++ b/configs/netgear_dgnd3700v2_ram_defconfig @@ -0,0 +1,55 @@ +CONFIG_MIPS=y +CONFIG_SYS_TEXT_BASE=0x80010000 +CONFIG_ARCH_BMIPS=y +CONFIG_SOC_BMIPS_BCM6362=y +# CONFIG_MIPS_BOOT_CMDLINE_LEGACY is not set +# CONFIG_MIPS_BOOT_ENV_LEGACY is not set +CONFIG_MIPS_BOOT_FDT=y +CONFIG_DEFAULT_DEVICE_TREE="netgear,dgnd3700v2" +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_OF_STDOUT_VIA_ALIAS=y +CONFIG_DISPLAY_CPUINFO=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="DGND3700v2 # " +CONFIG_CMD_CPU=y +CONFIG_CMD_LICENSE=y +# CONFIG_CMD_BOOTD is not set +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_XIMG is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_EDITENV is not set +# CONFIG_CMD_SAVEENV is not set +# CONFIG_CMD_ENV_EXISTS is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_MEMINFO=y +# CONFIG_CMD_FLASH is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_USB=y +# CONFIG_CMD_NET is not set +# CONFIG_CMD_NFS is not set +# CONFIG_CMD_MISC is not set +CONFIG_OF_EMBED=y +# CONFIG_DM_DEVICE_REMOVE is not set +CONFIG_DM_GPIO=y +CONFIG_BCM6345_GPIO=y +CONFIG_LED=y +CONFIG_LED_BCM6328=y +CONFIG_LED_BLINK=y +CONFIG_LED_GPIO=y +CONFIG_PHY=y +CONFIG_BCM6368_USBH_PHY=y +CONFIG_POWER_DOMAIN=y +CONFIG_BCM6328_POWER_DOMAIN=y +CONFIG_DM_RESET=y +CONFIG_RESET_BCM6345=y +# CONFIG_SPL_SERIAL_PRESENT is not set +CONFIG_DM_SERIAL=y +CONFIG_BCM6345_SERIAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y diff --git a/configs/sagem_f@st1704_ram_defconfig b/configs/sagem_f@st1704_ram_defconfig index 886e3676af2..7b049fceaa7 100644 --- a/configs/sagem_f@st1704_ram_defconfig +++ b/configs/sagem_f@st1704_ram_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_MEMINFO=y CONFIG_CMD_SF=y CONFIG_CMD_SPI=y # CONFIG_CMD_MISC is not set +CONFIG_OF_EMBED=y # CONFIG_NET is not set # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_DM_GPIO=y diff --git a/configs/sfr_nb4-ser_ram_defconfig b/configs/sfr_nb4-ser_ram_defconfig index 57ca22c4d6f..f2031df8454 100644 --- a/configs/sfr_nb4-ser_ram_defconfig +++ b/configs/sfr_nb4-ser_ram_defconfig @@ -25,7 +25,9 @@ CONFIG_CMD_LICENSE=y # CONFIG_CMD_CRC32 is not set CONFIG_CMD_MEMINFO=y # CONFIG_CMD_LOADS is not set +CONFIG_CMD_USB=y # CONFIG_CMD_MISC is not set +CONFIG_OF_EMBED=y # CONFIG_NET is not set # CONFIG_DM_DEVICE_REMOVE is not set CONFIG_DM_GPIO=y @@ -36,8 +38,16 @@ CONFIG_LED_GPIO=y CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_CFI_FLASH=y +CONFIG_PHY=y +CONFIG_BCM6358_USBH_PHY=y CONFIG_DM_RESET=y CONFIG_RESET_BCM6345=y # CONFIG_SPL_SERIAL_PRESENT is not set CONFIG_DM_SERIAL=y CONFIG_BCM6345_SERIAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y diff --git a/drivers/cpu/bmips_cpu.c b/drivers/cpu/bmips_cpu.c index 4ad291a56e2..6c612bacdc9 100644 --- a/drivers/cpu/bmips_cpu.c +++ b/drivers/cpu/bmips_cpu.c @@ -50,6 +50,10 @@ DECLARE_GLOBAL_DATA_PTR; #define DMIPSPLLCFG_6358_N2_SHIFT 29 #define DMIPSPLLCFG_6358_N2_MASK (0x7 << DMIPSPLLCFG_6358_N2_SHIFT) +#define REG_BCM6362_MISC_STRAPBUS 0x1814 +#define STRAPBUS_6362_FCVO_SHIFT 1 +#define STRAPBUS_6362_FCVO_MASK (0x1f << STRAPBUS_6362_FCVO_SHIFT) + #define REG_BCM6368_DDR_DMIPSPLLCFG 0x12a0 #define DMIPSPLLCFG_6368_P1_SHIFT 0 #define DMIPSPLLCFG_6368_P1_MASK (0xf << DMIPSPLLCFG_6368_P1_SHIFT) @@ -194,6 +198,44 @@ static ulong bcm6358_get_cpu_freq(struct bmips_cpu_priv *priv) return (16 * 1000000 * n1 * n2) / m1; } +static ulong bcm6362_get_cpu_freq(struct bmips_cpu_priv *priv) +{ + unsigned int mips_pll_fcvo; + + mips_pll_fcvo = readl_be(priv->regs + REG_BCM6362_MISC_STRAPBUS); + mips_pll_fcvo = (mips_pll_fcvo & STRAPBUS_6362_FCVO_MASK) + >> STRAPBUS_6362_FCVO_SHIFT; + + switch (mips_pll_fcvo) { + case 0x03: + case 0x0b: + case 0x13: + case 0x1b: + return 240000000; + case 0x04: + case 0x0c: + case 0x14: + case 0x1c: + return 160000000; + case 0x05: + case 0x0e: + case 0x16: + case 0x1e: + case 0x1f: + return 400000000; + case 0x06: + return 440000000; + case 0x07: + case 0x17: + return 384000000; + case 0x15: + case 0x1d: + return 200000000; + default: + return 320000000; + } +} + static ulong bcm6368_get_cpu_freq(struct bmips_cpu_priv *priv) { unsigned int tmp, p1, p2, ndiv, m1; @@ -289,6 +331,12 @@ static const struct bmips_cpu_hw bmips_cpu_bcm6358 = { .get_cpu_count = bcm6358_get_cpu_count, }; +static const struct bmips_cpu_hw bmips_cpu_bcm6362 = { + .get_cpu_desc = bmips_short_cpu_desc, + .get_cpu_freq = bcm6362_get_cpu_freq, + .get_cpu_count = bcm6358_get_cpu_count, +}; + static const struct bmips_cpu_hw bmips_cpu_bcm6368 = { .get_cpu_desc = bmips_short_cpu_desc, .get_cpu_freq = bcm6368_get_cpu_freq, @@ -395,6 +443,9 @@ static const struct udevice_id bmips_cpu_ids[] = { .compatible = "brcm,bcm6358-cpu", .data = (ulong)&bmips_cpu_bcm6358, }, { + .compatible = "brcm,bcm6362-cpu", + .data = (ulong)&bmips_cpu_bcm6362, + }, { .compatible = "brcm,bcm6368-cpu", .data = (ulong)&bmips_cpu_bcm6368, }, { diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 3b9a09ce181..4e9d09910c3 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -59,6 +59,31 @@ config SPL_NOP_PHY This is useful when a driver uses the PHY framework but no real PHY hardware exists. +config BCM6318_USBH_PHY + bool "BCM6318 USBH PHY support" + depends on PHY && ARCH_BMIPS + select POWER_DOMAIN + help + Support for the Broadcom MIPS BCM6318 USBH PHY. + +config BCM6348_USBH_PHY + bool "BCM6348 USBH PHY support" + depends on PHY && ARCH_BMIPS + help + Support for the Broadcom MIPS BCM6348 USBH PHY. + +config BCM6358_USBH_PHY + bool "BCM6358 USBH PHY support" + depends on PHY && ARCH_BMIPS + help + Support for the Broadcom MIPS BCM6358 USBH PHY. + +config BCM6368_USBH_PHY + bool "BCM6368 USBH PHY support" + depends on PHY && ARCH_BMIPS + help + Support for the Broadcom MIPS BCM6368 USBH PHY. + config PIPE3_PHY bool "Support omap's PIPE3 PHY" depends on PHY && ARCH_OMAP2PLUS diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 668040b0bb7..68087ae3b13 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -7,6 +7,10 @@ obj-$(CONFIG_$(SPL_)PHY) += phy-uclass.o obj-$(CONFIG_$(SPL_)NOP_PHY) += nop-phy.o +obj-$(CONFIG_BCM6318_USBH_PHY) += bcm6318-usbh-phy.o +obj-$(CONFIG_BCM6348_USBH_PHY) += bcm6348-usbh-phy.o +obj-$(CONFIG_BCM6358_USBH_PHY) += bcm6358-usbh-phy.o +obj-$(CONFIG_BCM6368_USBH_PHY) += bcm6368-usbh-phy.o obj-$(CONFIG_PHY_SANDBOX) += sandbox-phy.o obj-$(CONFIG_$(SPL_)PIPE3_PHY) += ti-pipe3-phy.o obj-$(CONFIG_STI_USB_PHY) += sti_usb_phy.o diff --git a/drivers/phy/bcm6318-usbh-phy.c b/drivers/phy/bcm6318-usbh-phy.c new file mode 100644 index 00000000000..6d542145818 --- /dev/null +++ b/drivers/phy/bcm6318-usbh-phy.c @@ -0,0 +1,144 @@ +/* + * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com> + * + * Derived from linux/arch/mips/bcm63xx/usb-common.c: + * Copyright 2008 Maxime Bizon <mbizon@freebox.fr> + * Copyright 2013 Florian Fainelli <florian@openwrt.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <generic-phy.h> +#include <power-domain.h> +#include <reset.h> +#include <asm/io.h> +#include <dm/device.h> + +/* USBH Setup register */ +#define USBH_SETUP_REG 0x00 +#define USBH_SETUP_IOC BIT(4) + +/* USBH PLL Control register */ +#define USBH_PLL_REG 0x04 +#define USBH_PLL_SUSP_EN BIT(27) +#define USBH_PLL_IDDQ_PWRDN BIT(31) + +/* USBH Swap Control register */ +#define USBH_SWAP_REG 0x0c +#define USBH_SWAP_OHCI_DATA BIT(0) +#define USBH_SWAP_OHCI_ENDIAN BIT(1) +#define USBH_SWAP_EHCI_DATA BIT(3) +#define USBH_SWAP_EHCI_ENDIAN BIT(4) + +/* USBH Sim Control register */ +#define USBH_SIM_REG 0x20 +#define USBH_SIM_LADDR BIT(5) + +struct bcm6318_usbh_priv { + void __iomem *regs; +}; + +static int bcm6318_usbh_init(struct phy *phy) +{ + struct bcm6318_usbh_priv *priv = dev_get_priv(phy->dev); + + /* enable pll control susp */ + setbits_be32(priv->regs + USBH_PLL_REG, USBH_PLL_SUSP_EN); + + /* configure to work in native cpu endian */ + clrsetbits_be32(priv->regs + USBH_SWAP_REG, + USBH_SWAP_EHCI_ENDIAN | USBH_SWAP_OHCI_ENDIAN, + USBH_SWAP_EHCI_DATA | USBH_SWAP_OHCI_DATA); + + /* setup config */ + setbits_be32(priv->regs + USBH_SETUP_REG, USBH_SETUP_IOC); + + /* disable pll control pwrdn */ + clrbits_be32(priv->regs + USBH_PLL_REG, USBH_PLL_IDDQ_PWRDN); + + /* sim control config */ + setbits_be32(priv->regs + USBH_SIM_REG, USBH_SIM_LADDR); + + return 0; +} + +static struct phy_ops bcm6318_usbh_ops = { + .init = bcm6318_usbh_init, +}; + +static const struct udevice_id bcm6318_usbh_ids[] = { + { .compatible = "brcm,bcm6318-usbh" }, + { /* sentinel */ } +}; + +static int bcm6318_usbh_probe(struct udevice *dev) +{ + struct bcm6318_usbh_priv *priv = dev_get_priv(dev); + struct power_domain pwr_dom; + struct reset_ctl rst_ctl; + struct clk clk; + fdt_addr_t addr; + fdt_size_t size; + int ret; + + addr = devfdt_get_addr_size_index(dev, 0, &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->regs = ioremap(addr, size); + + /* enable usbh clock */ + ret = clk_get_by_name(dev, "usbh", &clk); + if (ret < 0) + return ret; + + ret = clk_enable(&clk); + if (ret < 0) + return ret; + + ret = clk_free(&clk); + if (ret < 0) + return ret; + + /* enable power domain */ + ret = power_domain_get(dev, &pwr_dom); + if (ret < 0) + return ret; + + ret = power_domain_on(&pwr_dom); + if (ret < 0) + return ret; + + ret = power_domain_free(&pwr_dom); + if (ret < 0) + return ret; + + /* perform reset */ + ret = reset_get_by_index(dev, 0, &rst_ctl); + if (ret < 0) + return ret; + + ret = reset_deassert(&rst_ctl); + if (ret < 0) + return ret; + + ret = reset_free(&rst_ctl); + if (ret < 0) + return ret; + + mdelay(100); + + return 0; +} + +U_BOOT_DRIVER(bcm6318_usbh) = { + .name = "bcm6318-usbh", + .id = UCLASS_PHY, + .of_match = bcm6318_usbh_ids, + .ops = &bcm6318_usbh_ops, + .priv_auto_alloc_size = sizeof(struct bcm6318_usbh_priv), + .probe = bcm6318_usbh_probe, +}; diff --git a/drivers/phy/bcm6348-usbh-phy.c b/drivers/phy/bcm6348-usbh-phy.c new file mode 100644 index 00000000000..169ee0ecec0 --- /dev/null +++ b/drivers/phy/bcm6348-usbh-phy.c @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com> + * + * Derived from linux/arch/mips/bcm63xx/usb-common.c: + * Copyright 2008 Maxime Bizon <mbizon@freebox.fr> + * Copyright 2013 Florian Fainelli <florian@openwrt.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <generic-phy.h> +#include <reset.h> +#include <asm/io.h> +#include <dm/device.h> + +#define USBH_SETUP_PORT1_EN BIT(0) + +struct bcm6348_usbh_priv { + void __iomem *regs; +}; + +static int bcm6348_usbh_init(struct phy *phy) +{ + struct bcm6348_usbh_priv *priv = dev_get_priv(phy->dev); + + writel_be(USBH_SETUP_PORT1_EN, priv->regs); + + return 0; +} + +static struct phy_ops bcm6348_usbh_ops = { + .init = bcm6348_usbh_init, +}; + +static const struct udevice_id bcm6348_usbh_ids[] = { + { .compatible = "brcm,bcm6348-usbh" }, + { /* sentinel */ } +}; + +static int bcm6348_usbh_probe(struct udevice *dev) +{ + struct bcm6348_usbh_priv *priv = dev_get_priv(dev); + struct reset_ctl rst_ctl; + struct clk clk; + fdt_addr_t addr; + fdt_size_t size; + int ret; + + addr = devfdt_get_addr_size_index(dev, 0, &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->regs = ioremap(addr, size); + + /* enable usbh clock */ + ret = clk_get_by_name(dev, "usbh", &clk); + if (ret < 0) + return ret; + + ret = clk_enable(&clk); + if (ret < 0) + return ret; + + ret = clk_free(&clk); + if (ret < 0) + return ret; + + /* perform reset */ + ret = reset_get_by_index(dev, 0, &rst_ctl); + if (ret < 0) + return ret; + + ret = reset_deassert(&rst_ctl); + if (ret < 0) + return ret; + + ret = reset_free(&rst_ctl); + if (ret < 0) + return ret; + + return 0; +} + +U_BOOT_DRIVER(bcm6348_usbh) = { + .name = "bcm6348-usbh", + .id = UCLASS_PHY, + .of_match = bcm6348_usbh_ids, + .ops = &bcm6348_usbh_ops, + .priv_auto_alloc_size = sizeof(struct bcm6348_usbh_priv), + .probe = bcm6348_usbh_probe, +}; diff --git a/drivers/phy/bcm6358-usbh-phy.c b/drivers/phy/bcm6358-usbh-phy.c new file mode 100644 index 00000000000..e000316a932 --- /dev/null +++ b/drivers/phy/bcm6358-usbh-phy.c @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com> + * + * Derived from linux/arch/mips/bcm63xx/usb-common.c: + * Copyright 2008 Maxime Bizon <mbizon@freebox.fr> + * Copyright 2013 Florian Fainelli <florian@openwrt.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <generic-phy.h> +#include <reset.h> +#include <asm/io.h> +#include <dm/device.h> + +/* USBH Swap Control register */ +#define USBH_SWAP_REG 0x00 +#define USBH_SWAP_OHCI_DATA BIT(0) +#define USBH_SWAP_OHCI_ENDIAN BIT(1) +#define USBH_SWAP_EHCI_DATA BIT(3) +#define USBH_SWAP_EHCI_ENDIAN BIT(4) + +/* USBH Test register */ +#define USBH_TEST_REG 0x24 +#define USBH_TEST_PORT_CTL 0x1c0020 + +struct bcm6358_usbh_priv { + void __iomem *regs; +}; + +static int bcm6358_usbh_init(struct phy *phy) +{ + struct bcm6358_usbh_priv *priv = dev_get_priv(phy->dev); + + /* configure to work in native cpu endian */ + clrsetbits_be32(priv->regs + USBH_SWAP_REG, + USBH_SWAP_EHCI_ENDIAN | USBH_SWAP_OHCI_ENDIAN, + USBH_SWAP_EHCI_DATA | USBH_SWAP_OHCI_DATA); + + /* test port control */ + writel_be(USBH_TEST_PORT_CTL, priv->regs + USBH_TEST_REG); + + return 0; +} + +static struct phy_ops bcm6358_usbh_ops = { + .init = bcm6358_usbh_init, +}; + +static const struct udevice_id bcm6358_usbh_ids[] = { + { .compatible = "brcm,bcm6358-usbh" }, + { /* sentinel */ } +}; + +static int bcm6358_usbh_probe(struct udevice *dev) +{ + struct bcm6358_usbh_priv *priv = dev_get_priv(dev); + struct reset_ctl rst_ctl; + fdt_addr_t addr; + fdt_size_t size; + int ret; + + addr = devfdt_get_addr_size_index(dev, 0, &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->regs = ioremap(addr, size); + + /* perform reset */ + ret = reset_get_by_index(dev, 0, &rst_ctl); + if (ret < 0) + return ret; + + ret = reset_deassert(&rst_ctl); + if (ret < 0) + return ret; + + ret = reset_free(&rst_ctl); + if (ret < 0) + return ret; + + return 0; +} + +U_BOOT_DRIVER(bcm6358_usbh) = { + .name = "bcm6358-usbh", + .id = UCLASS_PHY, + .of_match = bcm6358_usbh_ids, + .ops = &bcm6358_usbh_ops, + .priv_auto_alloc_size = sizeof(struct bcm6358_usbh_priv), + .probe = bcm6358_usbh_probe, +}; diff --git a/drivers/phy/bcm6368-usbh-phy.c b/drivers/phy/bcm6368-usbh-phy.c new file mode 100644 index 00000000000..71abc0fcc4b --- /dev/null +++ b/drivers/phy/bcm6368-usbh-phy.c @@ -0,0 +1,196 @@ +/* + * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com> + * + * Derived from linux/arch/mips/bcm63xx/usb-common.c: + * Copyright 2008 Maxime Bizon <mbizon@freebox.fr> + * Copyright 2013 Florian Fainelli <florian@openwrt.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <generic-phy.h> +#include <power-domain.h> +#include <reset.h> +#include <asm/io.h> +#include <dm/device.h> + +/* USBH PLL Control register */ +#define USBH_PLL_REG 0x18 +#define USBH_PLL_IDDQ_PWRDN BIT(9) +#define USBH_PLL_PWRDN_DELAY BIT(10) + +/* USBH Swap Control register */ +#define USBH_SWAP_REG 0x1c +#define USBH_SWAP_OHCI_DATA BIT(0) +#define USBH_SWAP_OHCI_ENDIAN BIT(1) +#define USBH_SWAP_EHCI_DATA BIT(3) +#define USBH_SWAP_EHCI_ENDIAN BIT(4) + +/* USBH Setup register */ +#define USBH_SETUP_REG 0x28 +#define USBH_SETUP_IOC BIT(4) +#define USBH_SETUP_IPP BIT(5) + +struct bcm6368_usbh_hw { + uint32_t setup_clr; + uint32_t pll_clr; +}; + +struct bcm6368_usbh_priv { + const struct bcm6368_usbh_hw *hw; + void __iomem *regs; +}; + +static int bcm6368_usbh_init(struct phy *phy) +{ + struct bcm6368_usbh_priv *priv = dev_get_priv(phy->dev); + const struct bcm6368_usbh_hw *hw = priv->hw; + + /* configure to work in native cpu endian */ + clrsetbits_be32(priv->regs + USBH_SWAP_REG, + USBH_SWAP_EHCI_ENDIAN | USBH_SWAP_OHCI_ENDIAN, + USBH_SWAP_EHCI_DATA | USBH_SWAP_OHCI_DATA); + + /* setup config */ + if (hw->setup_clr) + clrbits_be32(priv->regs + USBH_SETUP_REG, hw->setup_clr); + + setbits_be32(priv->regs + USBH_SETUP_REG, USBH_SETUP_IOC); + + /* enable pll control */ + if (hw->pll_clr) + clrbits_be32(priv->regs + USBH_PLL_REG, hw->pll_clr); + + return 0; +} + +static struct phy_ops bcm6368_usbh_ops = { + .init = bcm6368_usbh_init, +}; + +static const struct bcm6368_usbh_hw bcm6328_hw = { + .pll_clr = USBH_PLL_IDDQ_PWRDN | USBH_PLL_PWRDN_DELAY, + .setup_clr = 0, +}; + +static const struct bcm6368_usbh_hw bcm6362_hw = { + .pll_clr = 0, + .setup_clr = 0, +}; + +static const struct bcm6368_usbh_hw bcm6368_hw = { + .pll_clr = 0, + .setup_clr = 0, +}; + +static const struct bcm6368_usbh_hw bcm63268_hw = { + .pll_clr = USBH_PLL_IDDQ_PWRDN | USBH_PLL_PWRDN_DELAY, + .setup_clr = USBH_SETUP_IPP, +}; + +static const struct udevice_id bcm6368_usbh_ids[] = { + { + .compatible = "brcm,bcm6328-usbh", + .data = (ulong)&bcm6328_hw, + }, { + .compatible = "brcm,bcm6362-usbh", + .data = (ulong)&bcm6362_hw, + }, { + .compatible = "brcm,bcm6368-usbh", + .data = (ulong)&bcm6368_hw, + }, { + .compatible = "brcm,bcm63268-usbh", + .data = (ulong)&bcm63268_hw, + }, { /* sentinel */ } +}; + +static int bcm6368_usbh_probe(struct udevice *dev) +{ + struct bcm6368_usbh_priv *priv = dev_get_priv(dev); + const struct bcm6368_usbh_hw *hw = + (const struct bcm6368_usbh_hw *)dev_get_driver_data(dev); +#if defined(CONFIG_POWER_DOMAIN) + struct power_domain pwr_dom; +#endif + struct reset_ctl rst_ctl; + struct clk clk; + fdt_addr_t addr; + fdt_size_t size; + int ret; + + addr = devfdt_get_addr_size_index(dev, 0, &size); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->regs = ioremap(addr, size); + priv->hw = hw; + + /* enable usbh clock */ + ret = clk_get_by_name(dev, "usbh", &clk); + if (ret < 0) + return ret; + + ret = clk_enable(&clk); + if (ret < 0) + return ret; + + ret = clk_free(&clk); + if (ret < 0) + return ret; + +#if defined(CONFIG_POWER_DOMAIN) + /* enable power domain */ + ret = power_domain_get(dev, &pwr_dom); + if (ret < 0) + return ret; + + ret = power_domain_on(&pwr_dom); + if (ret < 0) + return ret; + + ret = power_domain_free(&pwr_dom); + if (ret < 0) + return ret; +#endif + + /* perform reset */ + ret = reset_get_by_index(dev, 0, &rst_ctl); + if (ret < 0) + return ret; + + ret = reset_deassert(&rst_ctl); + if (ret < 0) + return ret; + + ret = reset_free(&rst_ctl); + if (ret < 0) + return ret; + + /* enable usb_ref clock */ + ret = clk_get_by_name(dev, "usb_ref", &clk); + if (!ret) { + ret = clk_enable(&clk); + if (ret < 0) + return ret; + + ret = clk_free(&clk); + if (ret < 0) + return ret; + } + + mdelay(100); + + return 0; +} + +U_BOOT_DRIVER(bcm6368_usbh) = { + .name = "bcm6368-usbh", + .id = UCLASS_PHY, + .of_match = bcm6368_usbh_ids, + .ops = &bcm6368_usbh_ops, + .priv_auto_alloc_size = sizeof(struct bcm6368_usbh_priv), + .probe = bcm6368_usbh_probe, +}; diff --git a/include/configs/bmips_bcm6318.h b/include/configs/bmips_bcm6318.h index 454a7b7f7ba..5541cc5cf6a 100644 --- a/include/configs/bmips_bcm6318.h +++ b/include/configs/bmips_bcm6318.h @@ -14,6 +14,13 @@ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE 0x80000000 +/* USB */ +#define CONFIG_EHCI_DESC_BIG_ENDIAN +#define CONFIG_EHCI_MMIO_BIG_ENDIAN +#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_OHCI_NEW + /* U-Boot */ #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 diff --git a/include/configs/bmips_bcm63268.h b/include/configs/bmips_bcm63268.h index ac0a6700f7c..042479b5159 100644 --- a/include/configs/bmips_bcm63268.h +++ b/include/configs/bmips_bcm63268.h @@ -14,6 +14,13 @@ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE 0x80000000 +/* USB */ +#define CONFIG_EHCI_DESC_BIG_ENDIAN +#define CONFIG_EHCI_MMIO_BIG_ENDIAN +#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_OHCI_NEW + /* U-Boot */ #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 diff --git a/include/configs/bmips_bcm6328.h b/include/configs/bmips_bcm6328.h index 41c7838a232..2cb9b5540eb 100644 --- a/include/configs/bmips_bcm6328.h +++ b/include/configs/bmips_bcm6328.h @@ -14,6 +14,13 @@ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE 0x80000000 +/* USB */ +#define CONFIG_EHCI_DESC_BIG_ENDIAN +#define CONFIG_EHCI_MMIO_BIG_ENDIAN +#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_OHCI_NEW + /* U-Boot */ #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 diff --git a/include/configs/bmips_bcm6348.h b/include/configs/bmips_bcm6348.h index e9f53d68117..6c9c33b822f 100644 --- a/include/configs/bmips_bcm6348.h +++ b/include/configs/bmips_bcm6348.h @@ -14,6 +14,11 @@ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE 0x80000000 +/* USB */ +#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_OHCI_NEW + /* U-Boot */ #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 diff --git a/include/configs/bmips_bcm6358.h b/include/configs/bmips_bcm6358.h index 5d018a34814..e3113ee309c 100644 --- a/include/configs/bmips_bcm6358.h +++ b/include/configs/bmips_bcm6358.h @@ -14,6 +14,13 @@ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE 0x80000000 +/* USB */ +#define CONFIG_EHCI_DESC_BIG_ENDIAN +#define CONFIG_EHCI_MMIO_BIG_ENDIAN +#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_OHCI_NEW + /* U-Boot */ #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 diff --git a/include/configs/bmips_bcm6362.h b/include/configs/bmips_bcm6362.h new file mode 100644 index 00000000000..2f92ac11354 --- /dev/null +++ b/include/configs/bmips_bcm6362.h @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_BMIPS_BCM6362_H +#define __CONFIG_BMIPS_BCM6362_H + +/* CPU */ +#define CONFIG_SYS_MIPS_TIMER_FREQ 200000000 + +/* RAM */ +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_SYS_SDRAM_BASE 0x80000000 + +/* USB */ +#define CONFIG_EHCI_DESC_BIG_ENDIAN +#define CONFIG_EHCI_MMIO_BIG_ENDIAN +#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_OHCI_NEW + +/* U-Boot */ +#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 + +#if defined(CONFIG_BMIPS_BOOT_RAM) +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SYS_INIT_SP_OFFSET 0x2000 +#endif + +#endif /* __CONFIG_BMIPS_BCM6362_H */ diff --git a/include/configs/bmips_bcm6368.h b/include/configs/bmips_bcm6368.h index ce35fae6a0f..ad8877b7d3a 100644 --- a/include/configs/bmips_bcm6368.h +++ b/include/configs/bmips_bcm6368.h @@ -14,6 +14,13 @@ #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE 0x80000000 +/* USB */ +#define CONFIG_EHCI_DESC_BIG_ENDIAN +#define CONFIG_EHCI_MMIO_BIG_ENDIAN +#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 +#define CONFIG_USB_OHCI_NEW + /* U-Boot */ #define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_SDRAM_BASE + 0x100000 diff --git a/include/configs/netgear_dgnd3700v2.h b/include/configs/netgear_dgnd3700v2.h new file mode 100644 index 00000000000..0c3823b1432 --- /dev/null +++ b/include/configs/netgear_dgnd3700v2.h @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <configs/bmips_common.h> +#include <configs/bmips_bcm6362.h> + +#define CONFIG_REMAKE_ELF + +#define CONFIG_ENV_SIZE (8 * 1024) + diff --git a/include/dt-bindings/clock/bcm6362-clock.h b/include/dt-bindings/clock/bcm6362-clock.h new file mode 100644 index 00000000000..6b11a9f5ac3 --- /dev/null +++ b/include/dt-bindings/clock/bcm6362-clock.h @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com> + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_CLOCK_BCM6362_H +#define __DT_BINDINGS_CLOCK_BCM6362_H + +#define BCM6362_CLK_GLESS 0 +#define BCM6362_CLK_ADSL_QPROC 1 +#define BCM6362_CLK_ADSL_AFE 2 +#define BCM6362_CLK_ADSL 3 +#define BCM6362_CLK_MIPS 4 +#define BCM6362_CLK_WLAN_OCP 5 +#define BCM6362_CLK_SWPKT_USB 7 +#define BCM6362_CLK_SWPKT_SAR 8 +#define BCM6362_CLK_SAR 9 +#define BCM6362_CLK_ROBOSW 10 +#define BCM6362_CLK_PCM 11 +#define BCM6362_CLK_USBD 12 +#define BCM6362_CLK_USBH 13 +#define BCM6362_CLK_IPSEC 14 +#define BCM6362_CLK_SPI 15 +#define BCM6362_CLK_HSSPI 16 +#define BCM6362_CLK_PCIE 17 +#define BCM6362_CLK_FAP 18 +#define BCM6362_CLK_PHYMIPS 19 +#define BCM6362_CLK_NAND 20 + +#endif /* __DT_BINDINGS_CLOCK_BCM6362_H */ diff --git a/include/dt-bindings/power-domain/bcm6362-power-domain.h b/include/dt-bindings/power-domain/bcm6362-power-domain.h new file mode 100644 index 00000000000..3178b00b577 --- /dev/null +++ b/include/dt-bindings/power-domain/bcm6362-power-domain.h @@ -0,0 +1,25 @@ +/* + * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_POWER_DOMAIN_BCM6362_H +#define __DT_BINDINGS_POWER_DOMAIN_BCM6362_H + +#define BCM6362_PWR_SAR 0 +#define BCM6362_PWR_IPSEC 1 +#define BCM6362_PWR_MIPS 2 +#define BCM6362_PWR_DECT 3 +#define BCM6362_PWR_USBH 4 +#define BCM6362_PWR_USBD 5 +#define BCM6362_PWR_ROBOSW 6 +#define BCM6362_PWR_PCM 7 +#define BCM6362_PWR_PERIPH 8 +#define BCM6362_PWR_ADSL_PHY 9 +#define BCM6362_PWR_GMII_PADS 10 +#define BCM6362_PWR_FAP 11 +#define BCM6362_PWR_PCIE 12 +#define BCM6362_PWR_WLAN_PADS 13 + +#endif /* __DT_BINDINGS_POWER_DOMAIN_BCM6362_H */ diff --git a/include/dt-bindings/reset/bcm6362-reset.h b/include/dt-bindings/reset/bcm6362-reset.h new file mode 100644 index 00000000000..ffa46a62f6e --- /dev/null +++ b/include/dt-bindings/reset/bcm6362-reset.h @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2018 Ãlvaro Fernández Rojas <noltari@gmail.com> + * + * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DT_BINDINGS_RESET_BCM6362_H +#define __DT_BINDINGS_RESET_BCM6362_H + +#define BCM6362_RST_SPI 0 +#define BCM6362_RST_IPSEC 1 +#define BCM6362_RST_EPHY 2 +#define BCM6362_RST_SAR 3 +#define BCM6362_RST_ENETSW 4 +#define BCM6362_RST_USBD 5 +#define BCM6362_RST_USBH 6 +#define BCM6362_RST_PCM 7 +#define BCM6362_RST_PCIE_CORE 8 +#define BCM6362_RST_PCIE 9 +#define BCM6362_RST_PCIE_EXT 10 +#define BCM6362_RST_WLAN_SHIM 11 +#define BCM6362_RST_DDR_PHY 12 +#define BCM6362_RST_FAP 13 +#define BCM6362_RST_WLAN_UBUS 14 + +#endif /* __DT_BINDINGS_RESET_BCM6362_H */ |