diff options
28 files changed, 739 insertions, 230 deletions
diff --git a/.travis.yml b/.travis.yml index e4e7e653f6d..6662ca126ab 100644 --- a/.travis.yml +++ b/.travis.yml @@ -50,6 +50,7 @@ install: - . /tmp/venv/bin/activate - pip install pytest==2.8.7 - pip install python-subunit + - pip install pyelftools - grub-mkimage -o ~/grub_x86.efi -O i386-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd - grub-mkimage -o ~/grub_x64.efi -O x86_64-efi normal echo lsefimmap lsefi lsefisystab efinet tftp minicmd - mkdir ~/grub2-arm @@ -250,7 +250,7 @@ config BUILD_TARGET default "u-boot-with-spl.sfp" if TARGET_SOCFPGA_GEN5 default "u-boot-spl.kwb" if ARCH_MVEBU && SPL default "u-boot-elf.srec" if RCAR_GEN3 - default "u-boot.itb" if SPL_LOAD_FIT && ARCH_SUNXI + default "u-boot.itb" if SPL_LOAD_FIT && (ROCKCHIP_RK3399 || ARCH_SUNXI) default "u-boot.kwb" if KIRKWOOD default "u-boot-with-spl.bin" if ARCH_AT91 && SPL_NAND_SUPPORT help @@ -1847,7 +1847,8 @@ clean: $(clean-dirs) -o -name modules.builtin -o -name '.tmp_*.o.*' \ -o -name 'dsdt.aml' -o -name 'dsdt.asl.tmp' -o -name 'dsdt.c' \ -o -name '*.efi' -o -name '*.gcno' -o -name '*.so' \) \ - -type f -print | xargs rm -f + -type f -print | xargs rm -f \ + bl31.c bl31.elf bl31_*.bin image.map # mrproper - Delete all generated files, including .config # diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 4dfc2c6309d..1d6367a3bf3 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -93,7 +93,8 @@ dtb-$(CONFIG_ROCKCHIP_RK3288) += \ rk3288-vyasa.dtb dtb-$(CONFIG_ROCKCHIP_RK3328) += \ - rk3328-evb.dtb + rk3328-evb.dtb \ + rk3328-rock64.dtb dtb-$(CONFIG_ROCKCHIP_RK3368) += \ rk3368-lion.dtb \ diff --git a/arch/arm/dts/rk3328-rock64-u-boot.dtsi b/arch/arm/dts/rk3328-rock64-u-boot.dtsi new file mode 100644 index 00000000000..b077436cbc3 --- /dev/null +++ b/arch/arm/dts/rk3328-rock64-u-boot.dtsi @@ -0,0 +1,34 @@ +/* + * (C) Copyright 2018 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/ { + aliases { + mmc0 = &emmc; + mmc1 = &sdmmc; + }; + + chosen { + u-boot,spl-boot-order = &emmc, &sdmmc; + }; +}; + +&cru { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; + +&emmc { + u-boot,dm-pre-reloc; + fifo-mode; +}; + +&sdmmc { + u-boot,dm-pre-reloc; + fifo-mode; +}; diff --git a/arch/arm/dts/rk3328-rock64.dts b/arch/arm/dts/rk3328-rock64.dts new file mode 100644 index 00000000000..7bcc53fcced --- /dev/null +++ b/arch/arm/dts/rk3328-rock64.dts @@ -0,0 +1,294 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2017 PINE64 + */ + +/dts-v1/; +#include "rk3328.dtsi" + +/ { + model = "Pine64 Rock64"; + compatible = "pine64,rock64", "rockchip,rk3328"; + + chosen { + stdout-path = "serial2:1500000n8"; + }; + + gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + + vcc_sd: sdmmc-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0m1_gpio>; + regulator-name = "vcc_sd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc_io>; + }; + + vcc_host_5v: vcc-host-5v-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb30_host_drv>; + regulator-name = "vcc_host_5v"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&usb20_host_drv>; + regulator-name = "vcc_host1_5v"; + regulator-always-on; + regulator-boot-on; + vin-supply = <&vcc_sys>; + }; + + vcc_sys: vcc-sys { + compatible = "regulator-fixed"; + regulator-name = "vcc_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&cpu1 { + cpu-supply = <&vdd_arm>; +}; + +&cpu2 { + cpu-supply = <&vdd_arm>; +}; + +&cpu3 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + bus-width = <8>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + vmmc-supply = <&vcc_io>; + vqmmc-supply = <&vcc18_emmc>; + status = "okay"; +}; + +&gmac2io { + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; + clock_in_out = "input"; + phy-supply = <&vcc_io>; + phy-mode = "rgmii"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_pins>; + snps,force_thresh_dma_mode; + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + tx_delay = <0x24>; + rx_delay = <0x18>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + rk805: rk805@18 { + compatible = "rockchip,rk805"; + reg = <0x18>; + interrupt-parent = <&gpio2>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + #clock-cells = <1>; + clock-output-names = "xin32k", "rk805-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc_sys>; + vcc2-supply = <&vcc_sys>; + vcc3-supply = <&vcc_sys>; + vcc4-supply = <&vcc_sys>; + vcc5-supply = <&vcc_io>; + vcc6-supply = <&vcc_sys>; + + regulators { + vdd_logic: DCDC_REG1 { + regulator-name = "vdd_logic"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-min-microvolt = <712500>; + regulator-max-microvolt = <1450000>; + regulator-ramp-delay = <12500>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <950000>; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc_io: DCDC_REG4 { + regulator-name = "vcc_io"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_18: LDO_REG1 { + regulator-name = "vdd_18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc18_emmc: LDO_REG2 { + regulator-name = "vcc_18emmc"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd_10: LDO_REG3 { + regulator-name = "vdd_10"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1000000>; + }; + }; + }; + }; +}; + +&io_domains { + status = "okay"; + + vccio1-supply = <&vcc_io>; + vccio2-supply = <&vcc18_emmc>; + vccio3-supply = <&vcc_io>; + vccio4-supply = <&vcc_18>; + vccio5-supply = <&vcc_io>; + vccio6-supply = <&vcc_io>; + pmuio-supply = <&vcc_io>; +}; + +&pinctrl { + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + usb2 { + usb20_host_drv: usb20-host-drv { + rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb3 { + usb30_host_drv: usb30-host-drv { + rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + disable-wp; + max-frequency = <150000000>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_dectn &sdmmc0_bus4>; + vmmc-supply = <&vcc_sd>; + status = "okay"; +}; + +&spi0 { + status = "okay"; + + spiflash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + + /* maximum speed for Rockchip SPI */ + spi-max-frequency = <50000000>; + }; +}; + +&uart2 { + status = "okay"; +}; + +&usb20_otg { + dr_mode = "host"; + status = "okay"; +}; + +&usb_host0_ehci { + status = "okay"; +}; + +&usb_host0_ohci { + status = "okay"; +}; diff --git a/arch/arm/dts/rk3399-gru.dtsi b/arch/arm/dts/rk3399-gru.dtsi index ca0fc391b2c..0e2e0471808 100644 --- a/arch/arm/dts/rk3399-gru.dtsi +++ b/arch/arm/dts/rk3399-gru.dtsi @@ -629,7 +629,6 @@ ap_i2c_audio: &i2c8 { &uart2 { status = "okay"; - u-boot,dm-pre-reloc; }; &usb_host0_ohci { diff --git a/arch/arm/dts/rk3399-puma.dtsi b/arch/arm/dts/rk3399-puma.dtsi index 897e0bda853..74368da5506 100644 --- a/arch/arm/dts/rk3399-puma.dtsi +++ b/arch/arm/dts/rk3399-puma.dtsi @@ -639,7 +639,6 @@ }; &uart0 { - u-boot,dm-pre-reloc; pinctrl-names = "default"; pinctrl-0 = <&uart0_xfer &uart0_cts>; status = "okay"; diff --git a/arch/arm/dts/rk3399-u-boot.dtsi b/arch/arm/dts/rk3399-u-boot.dtsi index 0786c1193ab..fcfce9ae021 100644 --- a/arch/arm/dts/rk3399-u-boot.dtsi +++ b/arch/arm/dts/rk3399-u-boot.dtsi @@ -10,3 +10,11 @@ &spi1 { u-boot,dm-pre-reloc; }; + +&uart0 { + u-boot,dm-pre-reloc; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index c05e3c3f486..1624b084b97 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -109,6 +109,13 @@ endif config ROCKCHIP_RK3328 bool "Support Rockchip RK3328" select ARM64 + select SUPPORT_SPL + select SPL + imply SPL_SERIAL_SUPPORT + imply SPL_SEPARATE_BSS + select ENABLE_ARM_SOC_BOOT0_HOOK + select DEBUG_UART_BOARD_INIT + select SYS_NS16550 help The Rockchip RK3328 is a ARM-based SoC with a quad-core Cortex-A53. including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two @@ -158,6 +165,7 @@ config ROCKCHIP_RK3399 select SPL select SPL_ATF select SPL_ATF_NO_PLATFORM_PARAM if SPL_ATF + select SPL_BOARD_INIT if SPL select SPL_LOAD_FIT select SPL_CLK if SPL select SPL_PINCTRL if SPL @@ -183,6 +191,7 @@ config ROCKCHIP_RK3399 imply TPL_LIBCOMMON_SUPPORT imply TPL_LIBGENERIC_SUPPORT imply TPL_SYS_MALLOC_SIMPLE + imply TPL_BOARD_INIT imply TPL_BOOTROM_SUPPORT imply TPL_DRIVERS_MISC_SUPPORT imply TPL_OF_CONTROL diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 846c82d70a9..23760a959ae 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -18,6 +18,7 @@ obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK322X) += rk322x-board-spl.o spl-boot-order.o obj-spl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o +obj-spl-$(CONFIG_ROCKCHIP_RK3328) += rk3328-board-spl.o obj-spl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-spl.o spl-boot-order.o obj-spl-$(CONFIG_ROCKCHIP_RK3399) += rk3399-board-spl.o spl-boot-order.o diff --git a/arch/arm/mach-rockchip/make_fit_atf.py b/arch/arm/mach-rockchip/make_fit_atf.py index 212bd0a8543..45ec105887a 100755 --- a/arch/arm/mach-rockchip/make_fit_atf.py +++ b/arch/arm/mach-rockchip/make_fit_atf.py @@ -12,6 +12,7 @@ import os import sys import getopt +import logging # pip install pyelftools from elftools.elf.elffile import ELFFile @@ -89,13 +90,17 @@ def append_conf_section(file, cnt, dtname, segments): file.write('\t\tconfig_%d {\n' % cnt) file.write('\t\t\tdescription = "%s";\n' % dtname) file.write('\t\t\tfirmware = "atf_1";\n') - file.write('\t\t\tloadables = "uboot",') + file.write('\t\t\tloadables = "uboot"') + if segments != 0: + file.write(',') for i in range(1, segments): file.write('"atf_%d"' % (i)) if i != (segments - 1): file.write(',') else: file.write(';\n') + if segments == 0: + file.write(';\n') file.write('\t\t\tfdt = "fdt_1";\n') file.write('\t\t};\n') file.write('\n') @@ -171,8 +176,18 @@ def generate_atf_binary(bl31_file_name): def main(): uboot_elf = "./u-boot" - bl31_elf = "./bl31.elf" fit_its = sys.stdout + if "BL31" in os.environ: + bl31_elf=os.getenv("BL31"); + elif os.path.isfile("./bl31.elf"): + bl31_elf = "./bl31.elf" + else: + os.system("echo 'int main(){}' > bl31.c") + os.system("${CROSS_COMPILE}gcc -c bl31.c -o bl31.elf") + bl31_elf = "./bl31.elf" + logging.basicConfig(format='%(levelname)s:%(message)s', level=logging.DEBUG) + logging.warning(' BL31 file bl31.elf NOT found, resulting binary is non-functional') + logging.warning(' Please read Building section in doc/README.rockchip') opts, args = getopt.getopt(sys.argv[1:], "o:u:b:h") for opt, val in opts: diff --git a/arch/arm/mach-rockchip/rk3328-board-spl.c b/arch/arm/mach-rockchip/rk3328-board-spl.c new file mode 100644 index 00000000000..7f49d056a07 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3328-board-spl.c @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2016 Rockchip Electronics Co., Ltd + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <dm/pinctrl.h> +#include <ram.h> +#include <spl.h> +#include <asm/io.h> + +DECLARE_GLOBAL_DATA_PTR; + +void board_debug_uart_init(void) +{ +} + +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + preloader_console_init(); + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return; + } +} + +u32 spl_boot_mode(const u32 boot_device) +{ + return MMCSD_MODE_RAW; +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_MMC1; +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif diff --git a/arch/arm/mach-rockchip/rk3399-board-spl.c b/arch/arm/mach-rockchip/rk3399-board-spl.c index 800ca800223..890d80025f6 100644 --- a/arch/arm/mach-rockchip/rk3399-board-spl.c +++ b/arch/arm/mach-rockchip/rk3399-board-spl.c @@ -11,13 +11,16 @@ #include <spl.h> #include <spl_gpio.h> #include <syscon.h> +#include <asm/gpio.h> #include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> #include <asm/arch-rockchip/clock.h> +#include <asm/arch-rockchip/cru_rk3399.h> #include <asm/arch-rockchip/grf_rk3399.h> #include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/periph.h> #include <asm/arch-rockchip/sys_proto.h> +#include <power/regulator.h> #include <dm/pinctrl.h> void board_return_to_bootrom(void) @@ -161,7 +164,7 @@ void board_init_f(ulong dummy) * printhex8(0x1234); * printascii("string"); */ - printascii("U-Boot SPL board init\n"); + debug("U-Boot SPL board init\n"); #endif ret = spl_early_init(); @@ -202,6 +205,66 @@ void board_init_f(ulong dummy) } } +#if defined(SPL_GPIO_SUPPORT) +static void rk3399_force_power_on_reset(void) +{ + ofnode node; + struct gpio_desc sysreset_gpio; + + debug("%s: trying to force a power-on reset\n", __func__); + + node = ofnode_path("/config"); + if (!ofnode_valid(node)) { + debug("%s: no /config node?\n", __func__); + return; + } + + if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0, + &sysreset_gpio, GPIOD_IS_OUT)) { + debug("%s: could not find a /config/sysreset-gpio\n", __func__); + return; + } + + dm_gpio_set_value(&sysreset_gpio, 1); +} +#endif + +void spl_board_init(void) +{ +#if defined(SPL_GPIO_SUPPORT) + struct rk3399_cru *cru = rockchip_get_cru(); + + /* + * The RK3399 resets only 'almost all logic' (see also in the TRM + * "3.9.4 Global software reset"), when issuing a software reset. + * This may cause issues during boot-up for some configurations of + * the application software stack. + * + * To work around this, we test whether the last reset reason was + * a power-on reset and (if not) issue an overtemp-reset to reset + * the entire module. + * + * While this was previously fixed by modifying the various places + * that could generate a software reset (e.g. U-Boot's sysreset + * driver, the ATF or Linux), we now have it here to ensure that + * we no longer have to track this through the various components. + */ + if (cru->glb_rst_st != 0) + rk3399_force_power_on_reset(); +#endif + +#if defined(SPL_DM_REGULATOR) + /* + * Turning the eMMC and SPI back on (if disabled via the Qseven + * BIOS_ENABLE) signal is done through a always-on regulator). + */ + if (regulators_enable_boot_on(false)) + debug("%s: Cannot enable boot on regulator\n", __func__); +#endif + + preloader_console_init(); +} + #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { diff --git a/arch/arm/mach-rockchip/rk3399-board-tpl.c b/arch/arm/mach-rockchip/rk3399-board-tpl.c index 86d3ffe97ca..4a301249b49 100644 --- a/arch/arm/mach-rockchip/rk3399-board-tpl.c +++ b/arch/arm/mach-rockchip/rk3399-board-tpl.c @@ -8,6 +8,7 @@ #include <dm.h> #include <ram.h> #include <spl.h> +#include <version.h> #include <asm/io.h> #include <asm/arch-rockchip/bootrom.h> @@ -46,7 +47,7 @@ void board_init_f(ulong dummy) * printhex8(0x1234); * printascii("string"); */ - printascii("U-Boot TPL board init\n"); + debug("U-Boot TPL board init\n"); #endif ret = spl_early_init(); if (ret) { @@ -73,6 +74,12 @@ u32 spl_boot_device(void) return BOOT_DEVICE_BOOTROM; } +void spl_board_init(void) +{ + puts("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " + U_BOOT_TIME " " U_BOOT_TZ ")\n"); +} + #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { diff --git a/board/rockchip/evb_rk3328/MAINTAINERS b/board/rockchip/evb_rk3328/MAINTAINERS index 2ee6e462a61..c661d2e06ae 100644 --- a/board/rockchip/evb_rk3328/MAINTAINERS +++ b/board/rockchip/evb_rk3328/MAINTAINERS @@ -4,3 +4,9 @@ S: Maintained F: board/rockchip/evb_rk3328 F: include/configs/evb_rk3328.h F: configs/evb-rk3328_defconfig + +ROCK64-RK3328 +M: Matwey V. Kornilov <matwey.kornilov@gmail.com> +S: Maintained +F: configs/rock64-rk3328_defconfig +F: arch/arm/dts/rk3328-rock64-u-boot.dtsi diff --git a/board/rockchip/evb_rk3399/evb-rk3399.c b/board/rockchip/evb_rk3399/evb-rk3399.c index bf2ad98c473..eb1b832274a 100644 --- a/board/rockchip/evb_rk3399/evb-rk3399.c +++ b/board/rockchip/evb_rk3399/evb-rk3399.c @@ -6,46 +6,14 @@ #include <common.h> #include <dm.h> #include <dm/pinctrl.h> -#include <dm/uclass-internal.h> #include <asm/arch-rockchip/periph.h> #include <power/regulator.h> -#include <spl.h> int board_init(void) { - struct udevice *pinctrl, *regulator; + struct udevice *regulator; int ret; - /* - * The PWM do not have decicated interrupt number in dts and can - * not get periph_id by pinctrl framework, so let's init them here. - * The PWM2 and PWM3 are for pwm regulater. - */ - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("%s: Cannot find pinctrl device\n", __func__); - goto out; - } - - /* Enable pwm0 for panel backlight */ - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM0); - if (ret) { - debug("%s PWM0 pinctrl init fail! (ret=%d)\n", __func__, ret); - goto out; - } - - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM2); - if (ret) { - debug("%s PWM2 pinctrl init fail!\n", __func__); - goto out; - } - - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_PWM3); - if (ret) { - debug("%s PWM3 pinctrl init fail!\n", __func__); - goto out; - } - ret = regulators_enable_boot_on(false); if (ret) debug("%s: Cannot enable boot on regulator\n", __func__); @@ -65,30 +33,3 @@ int board_init(void) out: return 0; } - -void spl_board_init(void) -{ - struct udevice *pinctrl; - int ret; - - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("%s: Cannot find pinctrl device\n", __func__); - goto err; - } - - /* Enable debug UART */ - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); - if (ret) { - debug("%s: Failed to set up console UART\n", __func__); - goto err; - } - - preloader_console_init(); - return; -err: - printf("%s: Error %d\n", __func__, ret); - - /* No way to report error here */ - hang(); -} diff --git a/board/theobroma-systems/puma_rk3399/README b/board/theobroma-systems/puma_rk3399/README index f67dfb451ff..9b31b0b3790 100644 --- a/board/theobroma-systems/puma_rk3399/README +++ b/board/theobroma-systems/puma_rk3399/README @@ -60,7 +60,7 @@ Creating a SPL image for SD-Card/eMMC Creating a SPL image for SPI-NOR > tools/mkimage -n rk3399 -T rkspi -d spl/u-boot-spl.bin spl_nor.img Create the FIT image containing U-Boot proper, ATF, M0 Firmware, devicetree - > make CROSS_COMPILE=aarch64-linux-gnu- u-boot.itb + > make CROSS_COMPILE=aarch64-linux-gnu- Flash the image =============== diff --git a/board/theobroma-systems/puma_rk3399/fit_spl_atf.its b/board/theobroma-systems/puma_rk3399/fit_spl_atf.its deleted file mode 100644 index 530f059f3da..00000000000 --- a/board/theobroma-systems/puma_rk3399/fit_spl_atf.its +++ /dev/null @@ -1,58 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ OR X11 */ -/* - * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH - * - * Minimal dts for a SPL FIT image payload. - */ - -/dts-v1/; - -/ { - description = "FIT image with U-Boot proper, ATF bl31, M0 Firmware, DTB"; - #address-cells = <1>; - - images { - uboot { - description = "U-Boot (64-bit)"; - data = /incbin/("../../../u-boot-nodtb.bin"); - type = "standalone"; - os = "U-Boot"; - arch = "arm64"; - compression = "none"; - load = <0x00200000>; - }; - atf { - description = "ARM Trusted Firmware"; - data = /incbin/("../../../bl31-rk3399.bin"); - type = "firmware"; - arch = "arm64"; - os = "arm-trusted-firmware"; - compression = "none"; - load = <0x1000>; - entry = <0x1000>; - }; - pmu { - description = "Cortex-M0 firmware"; - data = /incbin/("../../../rk3399m0.bin"); - type = "pmu-firmware"; - compression = "none"; - load = <0x180000>; - }; - fdt { - description = "RK3399-Q7 (Puma) flat device-tree"; - data = /incbin/("../../../u-boot.dtb"); - type = "flat_dt"; - compression = "none"; - }; - }; - - configurations { - default = "conf"; - conf { - description = "Theobroma Systems RK3399-Q7 (Puma) SoM"; - firmware = "atf"; - loadables = "uboot", "pmu"; - fdt = "fdt"; - }; - }; -}; diff --git a/board/theobroma-systems/puma_rk3399/fit_spl_atf.sh b/board/theobroma-systems/puma_rk3399/fit_spl_atf.sh new file mode 100755 index 00000000000..420e7daf4ce --- /dev/null +++ b/board/theobroma-systems/puma_rk3399/fit_spl_atf.sh @@ -0,0 +1,94 @@ +#!/bin/sh +# +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 Jagan Teki <jagan@amarulasolutions.com> +# +# Based on the board/sunxi/mksunxi_fit_atf.sh +# +# Script to generate FIT image source for 64-bit puma boards with +# U-Boot proper, ATF, PMU firmware and devicetree. +# +# usage: $0 <dt_name> [<dt_name> [<dt_name] ...] + +[ -z "$BL31" ] && BL31="bl31.bin" + +if [ ! -f $BL31 ]; then + echo "WARNING: BL31 file $BL31 NOT found, resulting binary is non-functional" >&2 + echo "Please read Building section in doc/README.rockchip" >&2 + BL31=/dev/null +fi + +[ -z "$PMUM0" ] && PMUM0="rk3399m0.bin" + +if [ ! -f $PMUM0 ]; then + echo "WARNING: PMUM0 file $PMUM0 NOT found, resulting binary is non-functional" >&2 + echo "Please read Building section in doc/README.rockchip" >&2 + PMUM0=/dev/null +fi + +cat << __HEADER_EOF +/* SPDX-License-Identifier: GPL-2.0+ OR X11 */ +/* + * Copyright (C) 2017 Theobroma Systems Design und Consulting GmbH + * + * Minimal dts for a SPL FIT image payload. + */ + +/dts-v1/; + +/ { + description = "FIT image with U-Boot proper, ATF bl31, M0 Firmware, DTB"; + #address-cells = <1>; + + images { + uboot { + description = "U-Boot (64-bit)"; + data = /incbin/("u-boot-nodtb.bin"); + type = "standalone"; + arch = "arm64"; + compression = "none"; + load = <0x4a000000>; + }; + atf { + description = "ARM Trusted Firmware"; + data = /incbin/("$BL31"); + type = "firmware"; + arch = "arm64"; + os = "arm-trusted-firmware"; + compression = "none"; + load = <0x1000>; + entry = <0x1000>; + }; + pmu { + description = "Cortex-M0 firmware"; + data = /incbin/("$PMUM0"); + type = "pmu-firmware"; + compression = "none"; + load = <0x180000>; + }; + fdt { + description = "RK3399-Q7 (Puma) flat device-tree"; + data = /incbin/("u-boot.dtb"); + type = "flat_dt"; + compression = "none"; + }; +__HEADER_EOF + +cat << __CONF_HEADER_EOF + }; + + configurations { + default = "conf"; + conf { + description = "Theobroma Systems RK3399-Q7 (Puma) SoM"; + firmware = "atf"; + loadables = "uboot", "pmu"; + fdt = "fdt"; + }; +__CONF_HEADER_EOF + +cat << __ITS_EOF + }; +}; +__ITS_EOF diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c index c6b509c109c..251cd2d5667 100644 --- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c +++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c @@ -13,10 +13,8 @@ #include <dm/pinctrl.h> #include <dm/uclass-internal.h> #include <asm/io.h> -#include <asm/gpio.h> #include <asm/setup.h> #include <asm/arch-rockchip/clock.h> -#include <asm/arch-rockchip/cru_rk3399.h> #include <asm/arch-rockchip/hardware.h> #include <asm/arch-rockchip/grf_rk3399.h> #include <asm/arch-rockchip/periph.h> @@ -38,62 +36,6 @@ int board_init(void) return 0; } -static void rk3399_force_power_on_reset(void) -{ - ofnode node; - struct gpio_desc sysreset_gpio; - - debug("%s: trying to force a power-on reset\n", __func__); - - node = ofnode_path("/config"); - if (!ofnode_valid(node)) { - debug("%s: no /config node?\n", __func__); - return; - } - - if (gpio_request_by_name_nodev(node, "sysreset-gpio", 0, - &sysreset_gpio, GPIOD_IS_OUT)) { - debug("%s: could not find a /config/sysreset-gpio\n", __func__); - return; - } - - dm_gpio_set_value(&sysreset_gpio, 1); -} - -void spl_board_init(void) -{ - int ret; - struct rk3399_cru *cru = rockchip_get_cru(); - - /* - * The RK3399 resets only 'almost all logic' (see also in the TRM - * "3.9.4 Global software reset"), when issuing a software reset. - * This may cause issues during boot-up for some configurations of - * the application software stack. - * - * To work around this, we test whether the last reset reason was - * a power-on reset and (if not) issue an overtemp-reset to reset - * the entire module. - * - * While this was previously fixed by modifying the various places - * that could generate a software reset (e.g. U-Boot's sysreset - * driver, the ATF or Linux), we now have it here to ensure that - * we no longer have to track this through the various components. - */ - if (cru->glb_rst_st != 0) - rk3399_force_power_on_reset(); - - /* - * Turning the eMMC and SPI back on (if disabled via the Qseven - * BIOS_ENABLE) signal is done through a always-on regulator). - */ - ret = regulators_enable_boot_on(false); - if (ret) - debug("%s: Cannot enable boot on regulator\n", __func__); - - preloader_console_init(); -} - static void setup_macaddr(void) { #if CONFIG_IS_ENABLED(CMD_NET) diff --git a/board/vamrs/rock960_rk3399/README b/board/vamrs/rock960_rk3399/README index d14399090e2..c5c675c4ead 100644 --- a/board/vamrs/rock960_rk3399/README +++ b/board/vamrs/rock960_rk3399/README @@ -61,7 +61,6 @@ Compile the U-Boot > export CROSS_COMPILE=aarch64-linux-gnu- > make rock960-rk3399_defconfig > make - > make u-boot.itb Compile the rkdeveloptool ========================= diff --git a/board/vamrs/rock960_rk3399/rock960-rk3399.c b/board/vamrs/rock960_rk3399/rock960-rk3399.c index 0f5ef3a09a4..2eb7120e84b 100644 --- a/board/vamrs/rock960_rk3399/rock960-rk3399.c +++ b/board/vamrs/rock960_rk3399/rock960-rk3399.c @@ -5,11 +5,7 @@ #include <common.h> #include <dm.h> -#include <dm/pinctrl.h> -#include <dm/uclass-internal.h> -#include <asm/arch-rockchip/periph.h> #include <power/regulator.h> -#include <spl.h> int board_init(void) { @@ -21,30 +17,3 @@ int board_init(void) return 0; } - -void spl_board_init(void) -{ - struct udevice *pinctrl; - int ret; - - ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); - if (ret) { - debug("%s: Cannot find pinctrl device\n", __func__); - goto err; - } - - /* Enable debug UART */ - ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); - if (ret) { - debug("%s: Failed to set up console UART\n", __func__); - goto err; - } - - preloader_console_init(); - return; -err: - printf("%s: Error %d\n", __func__, ret); - - /* No way to report error here */ - hang(); -} diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index aff9c32362d..92d6817ad5f 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -1,7 +1,10 @@ CONFIG_ARM=y CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_SYS_TEXT_BASE=0x00200000 CONFIG_ROCKCHIP_RK3328=y +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y CONFIG_NR_DRAM_BANKS=1 CONFIG_DEBUG_UART_BASE=0xFF130000 CONFIG_DEBUG_UART_CLOCK=24000000 @@ -19,11 +22,15 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_DEFAULT_DEVICE_TREE="rk3328-evb" +CONFIG_SPL_OF_CONTROL=y CONFIG_ENV_IS_IN_MMC=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y CONFIG_CLK=y +CONFIG_SPL_CLK=y CONFIG_FASTBOOT_BUF_ADDR=0x800800 CONFIG_FASTBOOT_FLASH=y CONFIG_FASTBOOT_FLASH_MMC_DEV=1 diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig index 03f0bfdb59d..5cb2273a151 100644 --- a/configs/puma-rk3399_defconfig +++ b/configs/puma-rk3399_defconfig @@ -15,13 +15,12 @@ CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI_SUPPORT=y CONFIG_DEBUG_UART=y -CONFIG_SPL_FIT_SOURCE="board/theobroma-systems/puma_rk3399/fit_spl_atf.its" +CONFIG_SPL_FIT_GENERATOR="board/theobroma-systems/puma_rk3399/fit_spl_atf.sh" CONFIG_DEFAULT_FDT_FILE="rockchip/rk3399-puma-haikou.dtb" CONFIG_MISC_INIT_R=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_DISPLAY_BOARDINFO_LATE=y CONFIG_SPL_TEXT_BASE=0xff8c2000 -CONFIG_SPL_BOARD_INIT=y # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_LEGACY_IMAGE_SUPPORT is not set CONFIG_SPL_STACK_R=y diff --git a/configs/rock64-rk3328_defconfig b/configs/rock64-rk3328_defconfig new file mode 100644 index 00000000000..6529dedfb6f --- /dev/null +++ b/configs/rock64-rk3328_defconfig @@ -0,0 +1,91 @@ +CONFIG_SMBIOS_MANUFACTURER="pine64" +CONFIG_SMBIOS_PRODUCT_NAME="rock64_rk3328" +CONFIG_ARM=y +CONFIG_ARCH_ROCKCHIP=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SYS_TEXT_BASE=0x00200000 +CONFIG_ROCKCHIP_RK3328=y +CONFIG_ROCKCHIP_SPL_RESERVE_IRAM=0x40000 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_DEBUG_UART_BASE=0xFF130000 +CONFIG_DEBUG_UART_CLOCK=24000000 +CONFIG_DEBUG_UART=y +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_ANDROID_BOOT_IMAGE is not set +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-rockchip/make_fit_atf.py" +CONFIG_DEFAULT_FDT_FILE="rockchip/rk3328-rock64.dtb" +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_SPL_STACK_R=y +CONFIG_SPL_ATF=y +CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y +CONFIG_FASTBOOT_BUF_ADDR=0x800800 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=1 +CONFIG_CMD_BOOTZ=y +CONFIG_CMD_GPT=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_USB=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_TIME=y +CONFIG_DEFAULT_DEVICE_TREE="rk3328-rock64" +CONFIG_SPL_OF_CONTROL=y +CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CLK=y +CONFIG_SPL_CLK=y +CONFIG_FASTBOOT_CMD_OEM_FORMAT=y +CONFIG_ROCKCHIP_GPIO=y +CONFIG_SYS_I2C_ROCKCHIP=y +CONFIG_MMC_DW=y +CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_SPI_FLASH=y +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_SPL_PINCTRL=y +CONFIG_PINCTRL_ROCKCHIP_RK3328=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_RK8XX=y +CONFIG_REGULATOR_PWM=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_REGULATOR_RK8XX=y +CONFIG_PWM_ROCKCHIP=y +CONFIG_RAM=y +CONFIG_SPL_RAM=y +CONFIG_DM_RESET=y +CONFIG_BAUDRATE=1500000 +CONFIG_DEBUG_UART_SHIFT=2 +CONFIG_SYSRESET=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_OHCI_HCD=y +CONFIG_USB_OHCI_GENERIC=y +CONFIG_USB_DWC2=y +CONFIG_USB_DWC3=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_MANUFACTURER="Rockchip" +CONFIG_USB_GADGET_VENDOR_NUM=0x2207 +CONFIG_USB_GADGET_PRODUCT_NUM=0x330a +CONFIG_USB_GADGET_DWC2_OTG=y +CONFIG_USE_TINY_PRINTF=y +CONFIG_SPL_TINY_MEMSET=y +CONFIG_ERRNO_STR=y diff --git a/doc/README.rockchip b/doc/README.rockchip index 264f7e4994f..02e2497b158 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -48,9 +48,10 @@ Two RK3036 boards are supported: - EVB RK3036 - use evb-rk3036 configuration - Kylin - use kylin_rk3036 configuration -One RK3328 board is supported: +Two RK3328 board are supported: - - EVB RK3328 + - EVB RK3328 - use evb-rk3328_defconfig + - Pine64 Rock64 board - use rock64-rk3328_defconfig Size RK3399 boards are supported (aarch64): @@ -103,7 +104,6 @@ For example: => cd /path/to/u-boot => make nanopi-neo4-rk3399_defconfig => make - => make u-boot.itb - Get the rkbin @@ -137,8 +137,8 @@ For example: => cd arm-trusted-firmware => make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 bl31 - (copy bl31.bin into U-Boot root dir) - => cp build/rk3399/release/bl31/bl31.bin /path/to/u-boot/bl31-rk3399.bin + (export bl31.bin) + => export BL31=/path/to/arm-trusted-firmware/build/rk3399/release/bl31/bl31.bin For rest of rk3399 boards. @@ -149,8 +149,8 @@ For example: => make realclean => make CROSS_COMPILE=aarch64-linux-gnu- PLAT=rk3399 - (copy bl31.elf into U-Boot root dir) - => cp build/rk3399/release/bl31/bl31.elf /path/to/u-boot + (export bl31.elf) + => export BL31=/path/to/arm-trusted-firmware/build/rk3399/release/bl31/bl31.elf - Compile PMU M0 firmware @@ -162,15 +162,14 @@ For example: (export cross compiler path for Cortex-M0 PMU) => make CROSS_COMPILE=arm-cortex_m0-eabi- - (copy rk3399m0.bin into U-Boot root dir) - => cp rk3399m0.bin /path/to/u-boot + (export rk3399m0.bin) + => export PMUM0=/path/to/rk3399-cortex-m0/rk3399m0.bin - Compile U-Boot => cd /path/to/u-boot => make orangepi-rk3399_defconfig => make - => make u-boot.itb (Get spl/u-boot-spl-dtb.bin, u-boot.itb images and some boards would get spl/u-boot-spl.bin since it doesn't enable CONFIG_SPL_OF_CONTROL @@ -310,6 +309,31 @@ tools/mkimage -n rk3188 -T rksd -d spl/u-boot-spl.bin out truncate -s %2048 u-boot.bin cat u-boot.bin | split -b 512 --filter='openssl rc4 -K 7C4E0304550509072D2C7B38170D1711' >> out +Booting from an SD card on Pine64 Rock64 (RK3328) +================================================= + +For Rock64 rk3328 board the following three parts are required: +TPL, SPL, and the u-boot image tree blob. While u-boot-spl.bin and +u-boot.itb are to be compiled as usual, TPL is currently not +implemented in u-boot, so you need to pick one from rkbin: + + - Get the rkbin + + => git clone https://github.com/rockchip-linux/rkbin.git + + - Create TPL/SPL image + + => tools/mkimage -n rk3328 -T rksd -d rkbin/bin/rk33/rk3328_ddr_333MHz_v1.16.bin idbloader.img + => cat spl/u-boot-spl.bin >> idbloader.img + + - Write TPL/SPL image at 64 sector + + => sudo dd if=idbloader.img of=/dev/mmcblk0 seek=64 + + - Write u-boot image tree blob at 16384 sector + + => sudo dd if=u-boot.itb of=/dev/mmcblk0 seek=16384 + Booting from an SD card on RK3399 ================================= diff --git a/include/configs/rk3328_common.h b/include/configs/rk3328_common.h index 71aad7029a5..2a81c803b60 100644 --- a/include/configs/rk3328_common.h +++ b/include/configs/rk3328_common.h @@ -16,6 +16,10 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x00300000 #define CONFIG_SYS_LOAD_ADDR 0x00800800 +#define CONFIG_SPL_STACK 0x00400000 +#define CONFIG_SPL_MAX_SIZE 0x100000 +#define CONFIG_SPL_BSS_START_ADDR 0x2000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */ |