diff options
| -rw-r--r-- | arch/powerpc/cpu/mpc83xx/traps.c | 7 | ||||
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/traps.c | 7 | ||||
| -rw-r--r-- | cmd/Kconfig | 7 | ||||
| -rw-r--r-- | cmd/Makefile | 1 | ||||
| -rw-r--r-- | cmd/bedbug.c | 410 | ||||
| -rw-r--r-- | common/Makefile | 1 | ||||
| -rw-r--r-- | common/bedbug.c | 1254 | ||||
| -rw-r--r-- | common/board_r.c | 9 | ||||
| -rw-r--r-- | doc/README.bedbug | 56 | ||||
| -rw-r--r-- | include/bedbug/bedbug.h | 40 | ||||
| -rw-r--r-- | include/bedbug/ppc.h | 408 | ||||
| -rw-r--r-- | include/bedbug/regs.h | 400 | ||||
| -rw-r--r-- | include/bedbug/tables.h | 601 | ||||
| -rw-r--r-- | include/bedbug/type.h | 29 | ||||
| -rw-r--r-- | post/lib_powerpc/string.c | 1 |
15 files changed, 1 insertions, 3230 deletions
diff --git a/arch/powerpc/cpu/mpc83xx/traps.c b/arch/powerpc/cpu/mpc83xx/traps.c index 22e451c58d6..94e6323d736 100644 --- a/arch/powerpc/cpu/mpc83xx/traps.c +++ b/arch/powerpc/cpu/mpc83xx/traps.c @@ -204,15 +204,8 @@ void UnknownException(struct pt_regs *regs) _exception(0, regs); } -#if defined(CONFIG_CMD_BEDBUG) -extern void do_bedbug_breakpoint(struct pt_regs *); -#endif - void DebugException(struct pt_regs *regs) { printf("Debugger trap at @ %lx\n", regs->nip ); show_regs(regs); -#if defined(CONFIG_CMD_BEDBUG) - do_bedbug_breakpoint( regs ); -#endif } diff --git a/arch/powerpc/cpu/mpc85xx/traps.c b/arch/powerpc/cpu/mpc85xx/traps.c index def47285ba3..97ed24a6eb4 100644 --- a/arch/powerpc/cpu/mpc85xx/traps.c +++ b/arch/powerpc/cpu/mpc85xx/traps.c @@ -60,10 +60,6 @@ static __inline__ unsigned long get_esr(void) #define ESR_DIZ 0x00400000 #define ESR_U0F 0x00008000 -#if defined(CONFIG_CMD_BEDBUG) -extern void do_bedbug_breakpoint(struct pt_regs *); -#endif - /* * Trap & Exception support */ @@ -285,7 +281,4 @@ void DebugException(struct pt_regs *regs) { printf("Debugger trap at @ %lx\n", regs->nip ); show_regs(regs); -#if defined(CONFIG_CMD_BEDBUG) - do_bedbug_breakpoint( regs ); -#endif } diff --git a/cmd/Kconfig b/cmd/Kconfig index dd7ab8df91a..84ede90eee9 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -2324,13 +2324,6 @@ endmenu menu "Debug commands" -config CMD_BEDBUG - bool "bedbug" - help - The bedbug (emBEDded deBUGger) command provides debugging features - for some PowerPC processors. For details please see the - documentation in doc/README.bedbug. - config CMD_CBSYSINFO bool "cbsysinfo" depends on X86 diff --git a/cmd/Makefile b/cmd/Makefile index 6623d7eaa05..fb133e37037 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -22,7 +22,6 @@ obj-$(CONFIG_HAVE_BLOCK_DEVICE) += blk_common.o obj-$(CONFIG_CMD_SOURCE) += source.o obj-$(CONFIG_CMD_BCB) += bcb.o obj-$(CONFIG_CMD_BDI) += bdinfo.o -obj-$(CONFIG_CMD_BEDBUG) += bedbug.o obj-$(CONFIG_CMD_BIND) += bind.o obj-$(CONFIG_CMD_BINOP) += binop.o obj-$(CONFIG_CMD_BLOBLIST) += bloblist.o diff --git a/cmd/bedbug.c b/cmd/bedbug.c deleted file mode 100644 index 0bd67fcf47c..00000000000 --- a/cmd/bedbug.c +++ /dev/null @@ -1,410 +0,0 @@ -/* - * BedBug Functions - */ - -#include <common.h> -#include <cli.h> -#include <command.h> -#include <console.h> -#include <asm/global_data.h> -#include <asm/ptrace.h> -#include <linux/ctype.h> -#include <net.h> -#include <bedbug/type.h> -#include <bedbug/bedbug.h> -#include <bedbug/regs.h> -#include <bedbug/ppc.h> - -DECLARE_GLOBAL_DATA_PTR; - -extern void show_regs __P ((struct pt_regs *)); -extern int run_command __P ((const char *, int)); - -ulong dis_last_addr = 0; /* Last address disassembled */ -ulong dis_last_len = 20; /* Default disassembler length */ -CPU_DEBUG_CTX bug_ctx; /* Bedbug context structure */ - - -/* ====================================================================== - * U-Boot's puts function does not append a newline, so the bedbug stuff - * will use this for the output of the dis/assembler. - * ====================================================================== */ - -int bedbug_puts (const char *str) -{ - /* -------------------------------------------------- */ - - printf ("%s\r\n", str); - return 0; -} /* bedbug_puts */ - - -/* ====================================================================== - * Initialize the bug_ctx structure used by the bedbug debugger. This is - * specific to the CPU since each has different debug registers and - * settings. - * ====================================================================== */ - -int bedbug_init(void) -{ - /* -------------------------------------------------- */ - return 0; -} /* bedbug_init */ - - -/* ====================================================================== - * Entry point from the interpreter to the disassembler. Repeated calls - * will resume from the last disassembled address. - * ====================================================================== */ -int do_bedbug_dis(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - ulong addr; /* Address to start disassembly from */ - ulong len; /* # of instructions to disassemble */ - - /* -------------------------------------------------- */ - - /* Setup to go from the last address if none is given */ - addr = dis_last_addr; - len = dis_last_len; - - if (argc < 2) - return CMD_RET_USAGE; - - if ((flag & CMD_FLAG_REPEAT) == 0) { - /* New command */ - addr = hextoul(argv[1], NULL); - - /* If an extra param is given then it is the length */ - if (argc > 2) - len = hextoul(argv[2], NULL); - } - - /* Run the disassembler */ - disppc ((unsigned char *) addr, 0, len, bedbug_puts, F_RADHEX); - - dis_last_addr = addr + (len * 4); - dis_last_len = len; - return 0; -} /* do_bedbug_dis */ - -U_BOOT_CMD (ds, 3, 1, do_bedbug_dis, - "disassemble memory", - "ds <address> [# instructions]"); - -/* ====================================================================== - * Entry point from the interpreter to the assembler. Assembles - * instructions in consecutive memory locations until a '.' (period) is - * entered on a line by itself. - * ====================================================================== */ -int do_bedbug_asm(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - long mem_addr; /* Address to assemble into */ - unsigned long instr; /* Machine code for text */ - char prompt[15]; /* Prompt string for user input */ - int asm_err; /* Error code from the assembler */ - - /* -------------------------------------------------- */ - int rcode = 0; - - if (argc < 2) - return CMD_RET_USAGE; - - printf ("\nEnter '.' when done\n"); - mem_addr = hextoul(argv[1], NULL); - - while (1) { - putc ('\n'); - disppc ((unsigned char *) mem_addr, 0, 1, bedbug_puts, - F_RADHEX); - - sprintf (prompt, "%08lx: ", mem_addr); - cli_readline(prompt); - - if (console_buffer[0] && strcmp (console_buffer, ".")) { - if ((instr = - asmppc (mem_addr, console_buffer, - &asm_err)) != 0) { - *(unsigned long *) mem_addr = instr; - mem_addr += 4; - } else { - printf ("*** Error: %s ***\n", - asm_error_str (asm_err)); - rcode = 1; - } - } else { - break; - } - } - return rcode; -} /* do_bedbug_asm */ - -U_BOOT_CMD (as, 2, 0, do_bedbug_asm, - "assemble memory", "as <address>"); - -/* ====================================================================== - * Used to set a break point from the interpreter. Simply calls into the - * CPU-specific break point set routine. - * ====================================================================== */ - -int do_bedbug_break(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - /* -------------------------------------------------- */ - if (bug_ctx.do_break) - (*bug_ctx.do_break) (cmdtp, flag, argc, argv); - return 0; - -} /* do_bedbug_break */ - -U_BOOT_CMD (break, 3, 0, do_bedbug_break, - "set or clear a breakpoint", - " - Set or clear a breakpoint\n" - "break <address> - Break at an address\n" - "break off <bp#> - Disable breakpoint.\n" - "break show - List breakpoints."); - -/* ====================================================================== - * Called from the debug interrupt routine. Simply calls the CPU-specific - * breakpoint handling routine. - * ====================================================================== */ - -void do_bedbug_breakpoint (struct pt_regs *regs) -{ - /* -------------------------------------------------- */ - - if (bug_ctx.break_isr) - (*bug_ctx.break_isr) (regs); - - return; -} /* do_bedbug_breakpoint */ - - -/* ====================================================================== - * Called from the CPU-specific breakpoint handling routine. Enter a - * mini main loop until the stopped flag is cleared from the breakpoint - * context. - * - * This handles the parts of the debugger that are common to all CPU's. - * ====================================================================== */ - -void bedbug_main_loop (unsigned long addr, struct pt_regs *regs) -{ - int len; /* Length of command line */ - int flag; /* Command flags */ - int rc = 0; /* Result from run_command */ - char prompt_str[20]; /* Prompt string */ - static char lastcommand[CONFIG_SYS_CBSIZE] = { 0 }; /* previous command */ - /* -------------------------------------------------- */ - - if (bug_ctx.clear) - (*bug_ctx.clear) (bug_ctx.current_bp); - - printf ("Breakpoint %d: ", bug_ctx.current_bp); - disppc ((unsigned char *) addr, 0, 1, bedbug_puts, F_RADHEX); - - bug_ctx.stopped = 1; - bug_ctx.regs = regs; - - sprintf (prompt_str, "BEDBUG.%d =>", bug_ctx.current_bp); - - /* A miniature main loop */ - while (bug_ctx.stopped) { - len = cli_readline(prompt_str); - - flag = 0; /* assume no special flags for now */ - - if (len > 0) - strcpy (lastcommand, console_buffer); - else if (len == 0) - flag |= CMD_FLAG_REPEAT; - - if (len == -1) - printf ("<INTERRUPT>\n"); - else - rc = run_command_repeatable(lastcommand, flag); - - if (rc <= 0) { - /* invalid command or not repeatable, forget it */ - lastcommand[0] = 0; - } - } - - bug_ctx.regs = NULL; - bug_ctx.current_bp = 0; - - return; -} /* bedbug_main_loop */ - - -/* ====================================================================== - * Interpreter command to continue from a breakpoint. Just clears the - * stopped flag in the context so that the breakpoint routine will - * return. - * ====================================================================== */ -int do_bedbug_continue(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - /* -------------------------------------------------- */ - - if (!bug_ctx.stopped) { - printf ("Not at a breakpoint\n"); - return 1; - } - - bug_ctx.stopped = 0; - return 0; -} /* do_bedbug_continue */ - -U_BOOT_CMD (continue, 1, 0, do_bedbug_continue, - "continue from a breakpoint", - ""); - -/* ====================================================================== - * Interpreter command to continue to the next instruction, stepping into - * subroutines. Works by calling the find_next_addr() routine to compute - * the address passes control to the CPU-specific set breakpoint routine - * for the current breakpoint number. - * ====================================================================== */ -int do_bedbug_step(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - unsigned long addr; /* Address to stop at */ - - /* -------------------------------------------------- */ - - if (!bug_ctx.stopped) { - printf ("Not at a breakpoint\n"); - return 1; - } - - if (!find_next_address((unsigned char *) &addr, false, bug_ctx.regs)) - return 1; - - if (bug_ctx.set) - (*bug_ctx.set) (bug_ctx.current_bp, addr); - - bug_ctx.stopped = 0; - return 0; -} /* do_bedbug_step */ - -U_BOOT_CMD (step, 1, 1, do_bedbug_step, - "single step execution.", - ""); - -/* ====================================================================== - * Interpreter command to continue to the next instruction, stepping over - * subroutines. Works by calling the find_next_addr() routine to compute - * the address passes control to the CPU-specific set breakpoint routine - * for the current breakpoint number. - * ====================================================================== */ -int do_bedbug_next(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - unsigned long addr; /* Address to stop at */ - - /* -------------------------------------------------- */ - - if (!bug_ctx.stopped) { - printf ("Not at a breakpoint\n"); - return 1; - } - - if (!find_next_address((unsigned char *) &addr, true, bug_ctx.regs)) - return 1; - - if (bug_ctx.set) - (*bug_ctx.set) (bug_ctx.current_bp, addr); - - bug_ctx.stopped = 0; - return 0; -} /* do_bedbug_next */ - -U_BOOT_CMD (next, 1, 1, do_bedbug_next, - "single step execution, stepping over subroutines.", - ""); - -/* ====================================================================== - * Interpreter command to print the current stack. This assumes an EABI - * architecture, so it starts with GPR R1 and works back up the stack. - * ====================================================================== */ -int do_bedbug_stack(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - unsigned long sp; /* Stack pointer */ - unsigned long func; /* LR from stack */ - int depth; /* Stack iteration level */ - int skip = 1; /* Flag to skip the first entry */ - unsigned long top; /* Top of memory address */ - - /* -------------------------------------------------- */ - - if (!bug_ctx.stopped) { - printf ("Not at a breakpoint\n"); - return 1; - } - - top = gd->ram_start + gd->ram_size; - depth = 0; - - printf ("Depth PC\n"); - printf ("----- --------\n"); - printf ("%5d %08lx\n", depth++, bug_ctx.regs->nip); - - sp = bug_ctx.regs->gpr[1]; - func = *(unsigned long *) (sp + 4); - - while ((func < top) && (sp < top)) { - if (!skip) - printf ("%5d %08lx\n", depth++, func); - else - --skip; - - sp = *(unsigned long *) sp; - func = *(unsigned long *) (sp + 4); - } - return 0; -} /* do_bedbug_stack */ - -U_BOOT_CMD (where, 1, 1, do_bedbug_stack, - "Print the running stack.", - ""); - -/* ====================================================================== - * Interpreter command to dump the registers. Calls the CPU-specific - * show registers routine. - * ====================================================================== */ -int do_bedbug_rdump(struct cmd_tbl *cmdtp, int flag, int argc, - char *const argv[]) -{ - /* -------------------------------------------------- */ - - if (!bug_ctx.stopped) { - printf ("Not at a breakpoint\n"); - return 1; - } - - show_regs (bug_ctx.regs); - return 0; -} /* do_bedbug_rdump */ - -U_BOOT_CMD (rdump, 1, 1, do_bedbug_rdump, - "Show registers.", ""); -/* ====================================================================== */ - - -/* - * Copyright (c) 2001 William L. Pitts - * All rights reserved. - * - * Redistribution and use in source and binary forms are freely - * permitted provided that the above copyright notice and this - * paragraph and the following disclaimer are duplicated in all - * such forms. - * - * This software is provided "AS IS" and without any express or - * implied warranties, including, without limitation, the implied - * warranties of merchantability and fitness for a particular - * purpose. - */ diff --git a/common/Makefile b/common/Makefile index 24be05c368d..3eff7196016 100644 --- a/common/Makefile +++ b/common/Makefile @@ -17,7 +17,6 @@ obj-y += board_r.o obj-$(CONFIG_DISPLAY_BOARDINFO) += board_info.o obj-$(CONFIG_DISPLAY_BOARDINFO_LATE) += board_info.o -obj-$(CONFIG_CMD_BEDBUG) += bedbug.o obj-$(CONFIG_FDT_SIMPLEFB) += fdt_simplefb.o obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += fdt_support.o obj-$(CONFIG_MII) += miiphyutil.o diff --git a/common/bedbug.c b/common/bedbug.c deleted file mode 100644 index c76fa4898c8..00000000000 --- a/common/bedbug.c +++ /dev/null @@ -1,1254 +0,0 @@ -/* $Id$ */ - -#include <common.h> -#include <asm/ptrace.h> - -#include <linux/ctype.h> -#include <bedbug/bedbug.h> -#include <bedbug/ppc.h> -#include <bedbug/regs.h> -#include <bedbug/tables.h> - -#define Elf32_Word unsigned long - -/* USE_SOURCE_CODE enables some symbolic debugging functions of this - code. This is only useful if the program will have access to the - source code for the binary being examined. -*/ - -/* #define USE_SOURCE_CODE 1 */ - -#ifdef USE_SOURCE_CODE -extern int line_info_from_addr __P ((Elf32_Word, char *, char *, int *)); -extern struct symreflist *symByAddr; -extern char *symbol_name_from_addr __P ((Elf32_Word, int, int *)); -#endif /* USE_SOURCE_CODE */ - -int print_operands __P ((struct ppc_ctx *)); -int get_operand_value __P ((struct opcode *, unsigned long, - enum OP_FIELD, unsigned long *)); -struct opcode *find_opcode __P ((unsigned long)); -struct opcode *find_opcode_by_name __P ((char *)); -char *spr_name __P ((int)); -int spr_value __P ((char *)); -char *tbr_name __P ((int)); -int tbr_value __P ((char *)); -int parse_operand __P ((unsigned long, struct opcode *, - struct operand *, char *, int *)); -int get_word __P ((char **, char *)); -long read_number __P ((char *)); -int downstring __P ((char *)); - - -/*====================================================================== - * Entry point for the PPC disassembler. - * - * Arguments: - * memaddr The address to start disassembling from. - * - * virtual If this value is non-zero, then this will be - * used as the base address for the output and - * symbol lookups. If this value is zero then - * memaddr is used as the absolute address. - * - * num_instr The number of instructions to disassemble. Since - * each instruction is 32 bits long, this can be - * computed if you know the total size of the region. - * - * pfunc The address of a function that is called to print - * each line of output. The function should take a - * single character pointer as its parameters a la puts. - * - * flags Sets options for the output. This is a - * bitwise-inclusive-OR of the following - * values. Note that only one of the radix - * options may be set. - * - * F_RADOCTAL - output radix is unsigned base 8. - * F_RADUDECIMAL - output radix is unsigned base 10. - * F_RADSDECIMAL - output radix is signed base 10. - * F_RADHEX - output radix is unsigned base 16. - * F_SIMPLE - use simplified mnemonics. - * F_SYMBOL - lookup symbols for addresses. - * F_INSTR - output raw instruction. - * F_LINENO - show line # info if available. - * - * Returns true if the area was successfully disassembled or false if - * a problem was encountered with accessing the memory. - */ - -int disppc (unsigned char *memaddr, unsigned char *virtual, int num_instr, - int (*pfunc) (const char *), unsigned long flags) -{ - int i; - struct ppc_ctx ctx; - -#ifdef USE_SOURCE_CODE - int line_no = 0; - int last_line_no = 0; - char funcname[128] = { 0 }; - char filename[256] = { 0 }; - char last_funcname[128] = { 0 }; - int symoffset; - char *symname; - char *cursym = (char *) 0; -#endif /* USE_SOURCE_CODE */ - /*------------------------------------------------------------*/ - - ctx.flags = flags; - ctx.virtual = virtual; - - /* Figure out the output radix before we go any further */ - - if (ctx.flags & F_RADOCTAL) { - /* Unsigned octal output */ - strcpy (ctx.radix_fmt, "O%o"); - } else if (ctx.flags & F_RADUDECIMAL) { - /* Unsigned decimal output */ - strcpy (ctx.radix_fmt, "%u"); - } else if (ctx.flags & F_RADSDECIMAL) { - /* Signed decimal output */ - strcpy (ctx.radix_fmt, "%d"); - } else { - /* Unsigned hex output */ - strcpy (ctx.radix_fmt, "0x%x"); - } - - if (ctx.virtual == 0) { - ctx.virtual = memaddr; - } -#ifdef USE_SOURCE_CODE - if (ctx.flags & F_SYMBOL) { - if (symByAddr == 0) /* no symbols loaded */ - ctx.flags &= ~F_SYMBOL; - else { - cursym = (char *) 0; - symoffset = 0; - } - } -#endif /* USE_SOURCE_CODE */ - - /* format each line as "XXXXXXXX: <symbol> IIIIIIII disassembly" where, - XXXXXXXX is the memory address in hex, - <symbol> is the symbolic location if F_SYMBOL is set. - IIIIIIII is the raw machine code in hex if F_INSTR is set, - and disassembly is the disassembled machine code with numbers - formatted according to the 'radix' parameter */ - - for (i = 0; i < num_instr; ++i, memaddr += 4, ctx.virtual += 4) { -#ifdef USE_SOURCE_CODE - if (ctx.flags & F_LINENO) { - if ((line_info_from_addr ((Elf32_Word) ctx.virtual, - filename, funcname, &line_no) == true) && - ((line_no != last_line_no) || - (strcmp (last_funcname, funcname) != 0))) { - print_source_line (filename, funcname, line_no, pfunc); - } - last_line_no = line_no; - strcpy (last_funcname, funcname); - } -#endif /* USE_SOURCE_CODE */ - - sprintf (ctx.data, "%08lx: ", (unsigned long) ctx.virtual); - ctx.datalen = 10; - -#ifdef USE_SOURCE_CODE - if (ctx.flags & F_SYMBOL) { - if ((symname = - symbol_name_from_addr((Elf32_Word) ctx.virtual, - true, 0)) != 0) { - cursym = symname; - symoffset = 0; - } else { - if ((cursym == 0) && - ((symname = - symbol_name_from_addr((Elf32_Word) ctx.virtual, - false, &symoffset)) != 0)) { - cursym = symname; - } else { - symoffset += 4; - } - } - - if (cursym != 0) { - sprintf (&ctx.data[ctx.datalen], "<%s+", cursym); - ctx.datalen = strlen (ctx.data); - sprintf (&ctx.data[ctx.datalen], ctx.radix_fmt, symoffset); - strcat (ctx.data, ">"); - ctx.datalen = strlen (ctx.data); - } - } -#endif /* USE_SOURCE_CODE */ - - ctx.instr = INSTRUCTION (memaddr); - - if (ctx.flags & F_INSTR) { - /* Find the opcode structure for this opcode. If one is not found - then it must be an illegal instruction */ - sprintf (&ctx.data[ctx.datalen], - " %02lx %02lx %02lx %02lx ", - ((ctx.instr >> 24) & 0xff), - ((ctx.instr >> 16) & 0xff), ((ctx.instr >> 8) & 0xff), - (ctx.instr & 0xff)); - ctx.datalen += 18; - } else { - strcat (ctx.data, " "); - ctx.datalen += 3; - } - - if ((ctx.op = find_opcode (ctx.instr)) == 0) { - /* Illegal Opcode */ - sprintf (&ctx.data[ctx.datalen], " .long 0x%08lx", - ctx.instr); - ctx.datalen += 24; - (*pfunc) (ctx.data); - continue; - } - - if (((ctx.flags & F_SIMPLE) == 0) || - (ctx.op->hfunc == 0) || - ((*ctx.op->hfunc) (&ctx) == false)) { - sprintf (&ctx.data[ctx.datalen], "%-7s ", ctx.op->name); - ctx.datalen += 8; - print_operands (&ctx); - } - - (*pfunc) (ctx.data); - } - - return true; -} /* disppc */ - - - -/*====================================================================== - * Called by the disassembler to print the operands for an instruction. - * - * Arguments: - * ctx A pointer to the disassembler context record. - * - * always returns 0. - */ - -int print_operands (struct ppc_ctx *ctx) -{ - int open_parens = 0; - int field; - unsigned long operand; - struct operand *opr; - -#ifdef USE_SOURCE_CODE - char *symname; - int offset; -#endif /* USE_SOURCE_CODE */ - /*------------------------------------------------------------*/ - - /* Walk through the operands and list each in order */ - for (field = 0; ctx->op->fields[field] != 0; ++field) { - if (ctx->op->fields[field] > n_operands) { - continue; /* bad operand ?! */ - } - - opr = &operands[ctx->op->fields[field] - 1]; - - if (opr->hint & OH_SILENT) { - continue; - } - - if ((field > 0) && !open_parens) { - strcat (ctx->data, ","); - ctx->datalen++; - } - - operand = (ctx->instr >> opr->shift) & ((1 << opr->bits) - 1); - - if (opr->hint & OH_ADDR) { - if ((operand & (1 << (opr->bits - 1))) != 0) { - operand = operand - (1 << opr->bits); - } - - if (ctx->op->hint & H_RELATIVE) - operand = (operand << 2) + (unsigned long) ctx->virtual; - else - operand = (operand << 2); - - - sprintf (&ctx->data[ctx->datalen], "0x%lx", operand); - ctx->datalen = strlen (ctx->data); - -#ifdef USE_SOURCE_CODE - if ((ctx->flags & F_SYMBOL) && - ((symname = - symbol_name_from_addr (operand, 0, &offset)) != 0)) { - sprintf (&ctx->data[ctx->datalen], " <%s", symname); - if (offset != 0) { - strcat (ctx->data, "+"); - ctx->datalen = strlen (ctx->data); - sprintf (&ctx->data[ctx->datalen], ctx->radix_fmt, - offset); - } - strcat (ctx->data, ">"); - } -#endif /* USE_SOURCE_CODE */ - } - - else if (opr->hint & OH_REG) { - if ((operand == 0) && - (opr->field == O_rA) && (ctx->op->hint & H_RA0_IS_0)) { - strcat (ctx->data, "0"); - } else { - sprintf (&ctx->data[ctx->datalen], "r%d", (short) operand); - } - - if (open_parens) { - strcat (ctx->data, ")"); - open_parens--; - } - } - - else if (opr->hint & OH_SPR) { - strcat (ctx->data, spr_name (operand)); - } - - else if (opr->hint & OH_TBR) { - strcat (ctx->data, tbr_name (operand)); - } - - else if (opr->hint & OH_LITERAL) { - switch (opr->field) { - case O_cr2: - strcat (ctx->data, "cr2"); - ctx->datalen += 3; - break; - - default: - break; - } - } - - else { - sprintf (&ctx->data[ctx->datalen], ctx->radix_fmt, - (unsigned short) operand); - - if (open_parens) { - strcat (ctx->data, ")"); - open_parens--; - } - - else if (opr->hint & OH_OFFSET) { - strcat (ctx->data, "("); - open_parens++; - } - } - - ctx->datalen = strlen (ctx->data); - } - - return 0; -} /* print_operands */ - - - -/*====================================================================== - * Called to get the value of an arbitrary operand with in an instruction. - * - * Arguments: - * op The pointer to the opcode structure to which - * the operands belong. - * - * instr The instruction (32 bits) containing the opcode - * and the operands to print. By the time that - * this routine is called the operand has already - * been added to the output. - * - * field The field (operand) to get the value of. - * - * value The address of an unsigned long to be filled in - * with the value of the operand if it is found. This - * will only be filled in if the function returns - * true. This may be passed as 0 if the value is - * not required. - * - * Returns true if the operand was found or false if it was not. - */ - -int get_operand_value (struct opcode *op, unsigned long instr, - enum OP_FIELD field, unsigned long *value) -{ - int i; - struct operand *opr; - - /*------------------------------------------------------------*/ - - if (field > n_operands) { - return false; /* bad operand ?! */ - } - - /* Walk through the operands and list each in order */ - for (i = 0; op->fields[i] != 0; ++i) { - if (op->fields[i] != field) { - continue; - } - - opr = &operands[op->fields[i] - 1]; - - if (value) { - *value = (instr >> opr->shift) & ((1 << opr->bits) - 1); - } - return true; - } - - return false; -} /* operand_value */ - - - -/*====================================================================== - * Called by the disassembler to match an opcode value to an opcode structure. - * - * Arguments: - * instr The instruction (32 bits) to match. This value - * may contain operand values as well as the opcode - * since they will be masked out anyway for this - * search. - * - * Returns the address of an opcode struct (from the opcode table) if the - * operand successfully matched an entry, or 0 if no match was found. - */ - -struct opcode *find_opcode (unsigned long instr) -{ - struct opcode *ptr; - int top = 0; - int bottom = n_opcodes - 1; - int idx; - - /*------------------------------------------------------------*/ - - while (top <= bottom) { - idx = (top + bottom) >> 1; - ptr = &opcodes[idx]; - - if ((instr & ptr->mask) < ptr->opcode) { - bottom = idx - 1; - } else if ((instr & ptr->mask) > ptr->opcode) { - top = idx + 1; - } else { - return ptr; - } - } - - return (struct opcode *) 0; -} /* find_opcode */ - - - -/*====================================================================== - * Called by the assembler to match an opcode name to an opcode structure. - * - * Arguments: - * name The text name of the opcode, e.g. "b", "mtspr", etc. - * - * The opcodes are sorted numerically by their instruction binary code - * so a search for the name cannot use the binary search used by the - * other find routine. - * - * Returns the address of an opcode struct (from the opcode table) if the - * name successfully matched an entry, or 0 if no match was found. - */ - -struct opcode *find_opcode_by_name (char *name) -{ - int idx; - - /*------------------------------------------------------------*/ - - downstring (name); - - for (idx = 0; idx < n_opcodes; ++idx) { - if (!strcmp (name, opcodes[idx].name)) - return &opcodes[idx]; - } - - return (struct opcode *) 0; -} /* find_opcode_by_name */ - - - -/*====================================================================== - * Convert the 'spr' operand from its numeric value to its symbolic name. - * - * Arguments: - * value The value of the 'spr' operand. This value should - * be unmodified from its encoding in the instruction. - * the split-field computations will be performed - * here before the switch. - * - * Returns the address of a character array containing the name of the - * special purpose register defined by the 'value' parameter, or the - * address of a character array containing "???" if no match was found. - */ - -char *spr_name (int value) -{ - unsigned short spr; - static char other[10]; - int i; - - /*------------------------------------------------------------*/ - - /* spr is a 10 bit field whose interpretation has the high and low - five-bit fields reversed from their encoding in the operand */ - - spr = ((value >> 5) & 0x1f) | ((value & 0x1f) << 5); - - for (i = 0; i < n_sprs; ++i) { - if (spr == spr_map[i].spr_val) - return spr_map[i].spr_name; - } - - sprintf (other, "%d", spr); - return other; -} /* spr_name */ - - - -/*====================================================================== - * Convert the 'spr' operand from its symbolic name to its numeric value - * - * Arguments: - * name The symbolic name of the 'spr' operand. The - * split-field encoding will be done by this routine. - * NOTE: name can be a number. - * - * Returns the numeric value for the spr appropriate for encoding a machine - * instruction. Returns 0 if unable to find the SPR. - */ - -int spr_value (char *name) -{ - struct spr_info *sprp; - int spr; - int i; - - /*------------------------------------------------------------*/ - - if (!name || !*name) - return 0; - - if (isdigit ((int) name[0])) { - i = htonl (read_number (name)); - spr = ((i >> 5) & 0x1f) | ((i & 0x1f) << 5); - return spr; - } - - downstring (name); - - for (i = 0; i < n_sprs; ++i) { - sprp = &spr_map[i]; - - if (strcmp (name, sprp->spr_name) == 0) { - /* spr is a 10 bit field whose interpretation has the high and low - five-bit fields reversed from their encoding in the operand */ - i = htonl (sprp->spr_val); - spr = ((i >> 5) & 0x1f) | ((i & 0x1f) << 5); - - return spr; - } - } - - return 0; -} /* spr_value */ - - - -/*====================================================================== - * Convert the 'tbr' operand from its numeric value to its symbolic name. - * - * Arguments: - * value The value of the 'tbr' operand. This value should - * be unmodified from its encoding in the instruction. - * the split-field computations will be performed - * here before the switch. - * - * Returns the address of a character array containing the name of the - * time base register defined by the 'value' parameter, or the address - * of a character array containing "???" if no match was found. - */ - -char *tbr_name (int value) -{ - unsigned short tbr; - - /*------------------------------------------------------------*/ - - /* tbr is a 10 bit field whose interpretation has the high and low - five-bit fields reversed from their encoding in the operand */ - - tbr = ((value >> 5) & 0x1f) | ((value & 0x1f) << 5); - - if (tbr == 268) - return "TBL"; - - else if (tbr == 269) - return "TBU"; - - - return "???"; -} /* tbr_name */ - - - -/*====================================================================== - * Convert the 'tbr' operand from its symbolic name to its numeric value. - * - * Arguments: - * name The symbolic name of the 'tbr' operand. The - * split-field encoding will be done by this routine. - * - * Returns the numeric value for the spr appropriate for encoding a machine - * instruction. Returns 0 if unable to find the TBR. - */ - -int tbr_value (char *name) -{ - int tbr; - int val; - - /*------------------------------------------------------------*/ - - if (!name || !*name) - return 0; - - downstring (name); - - if (isdigit ((int) name[0])) { - val = read_number (name); - - if (val != 268 && val != 269) - return 0; - } else if (strcmp (name, "tbl") == 0) - val = 268; - else if (strcmp (name, "tbu") == 0) - val = 269; - else - return 0; - - /* tbr is a 10 bit field whose interpretation has the high and low - five-bit fields reversed from their encoding in the operand */ - - val = htonl (val); - tbr = ((val >> 5) & 0x1f) | ((val & 0x1f) << 5); - return tbr; -} /* tbr_name */ - - - -/*====================================================================== - * The next several functions (handle_xxx) are the routines that handle - * disassembling the opcodes with simplified mnemonics. - * - * Arguments: - * ctx A pointer to the disassembler context record. - * - * Returns true if the simpler form was printed or false if it was not. - */ - -int handle_bc (struct ppc_ctx *ctx) -{ - unsigned long bo; - unsigned long bi; - static struct opcode blt = { B_OPCODE (16, 0, 0), B_MASK, {O_BD, 0}, - 0, "blt", H_RELATIVE - }; - static struct opcode bne = - { B_OPCODE (16, 0, 0), B_MASK, {O_cr2, O_BD, 0}, - 0, "bne", H_RELATIVE - }; - static struct opcode bdnz = { B_OPCODE (16, 0, 0), B_MASK, {O_BD, 0}, - 0, "bdnz", H_RELATIVE - }; - - /*------------------------------------------------------------*/ - - if (get_operand_value(ctx->op, ctx->instr, O_BO, &bo) == false) - return false; - - if (get_operand_value(ctx->op, ctx->instr, O_BI, &bi) == false) - return false; - - if ((bo == 12) && (bi == 0)) { - ctx->op = &blt; - sprintf (&ctx->data[ctx->datalen], "%-7s ", ctx->op->name); - ctx->datalen += 8; - print_operands (ctx); - return true; - } else if ((bo == 4) && (bi == 10)) { - ctx->op = =⃥ - sprintf (&ctx->data[ctx->datalen], "%-7s ", ctx->op->name); - ctx->datalen += 8; - print_operands (ctx); - return true; - } else if ((bo == 16) && (bi == 0)) { - ctx->op = &bdnz; - sprintf (&ctx->data[ctx->datalen], "%-7s ", ctx->op->name); - ctx->datalen += 8; - print_operands (ctx); - return true; - } - - return false; -} /* handle_blt */ - - - -/*====================================================================== - * Outputs source line information for the disassembler. This should - * be modified in the future to lookup the actual line of source code - * from the file, but for now this will do. - * - * Arguments: - * filename The address of a character array containing the - * absolute path and file name of the source file. - * - * funcname The address of a character array containing the - * name of the function (not C++ demangled (yet)) - * to which this code belongs. - * - * line_no An integer specifying the source line number that - * generated this code. - * - * pfunc The address of a function to call to print the output. - * - * - * Returns true if it was able to output the line info, or false if it was - * not. - */ - -int print_source_line (char *filename, char *funcname, - int line_no, int (*pfunc) (const char *)) -{ - char out_buf[256]; - - /*------------------------------------------------------------*/ - - (*pfunc) (""); /* output a newline */ - sprintf (out_buf, "%s %s(): line %d", filename, funcname, line_no); - (*pfunc) (out_buf); - - return true; -} /* print_source_line */ - - - -/*====================================================================== - * Entry point for the PPC assembler. - * - * Arguments: - * asm_buf An array of characters containing the assembly opcode - * and operands to convert to a POWERPC machine - * instruction. - * - * Returns the machine instruction or zero. - */ - -unsigned long asmppc (unsigned long memaddr, char *asm_buf, int *err) -{ - struct opcode *opc; - struct operand *oper[MAX_OPERANDS]; - unsigned long instr; - unsigned long param; - char *ptr = asm_buf; - char scratch[20]; - int i; - int w_operands = 0; /* wanted # of operands */ - int n_operands = 0; /* # of operands read */ - int asm_debug = 0; - - /*------------------------------------------------------------*/ - - if (err) - *err = 0; - - if (get_word (&ptr, scratch) == 0) - return 0; - - /* Lookup the opcode structure based on the opcode name */ - if ((opc = find_opcode_by_name (scratch)) == (struct opcode *) 0) { - if (err) - *err = E_ASM_BAD_OPCODE; - return 0; - } - - if (asm_debug) { - printf ("asmppc: Opcode = \"%s\"\n", opc->name); - } - - for (i = 0; i < 8; ++i) { - if (opc->fields[i] == 0) - break; - ++w_operands; - } - - if (asm_debug) { - printf ("asmppc: Expecting %d operands\n", w_operands); - } - - instr = opc->opcode; - - /* read each operand */ - while (n_operands < w_operands) { - - oper[n_operands] = &operands[opc->fields[n_operands] - 1]; - - if (oper[n_operands]->hint & OH_SILENT) { - /* Skip silent operands, they are covered in opc->opcode */ - - if (asm_debug) { - printf ("asmppc: Operand %d \"%s\" SILENT\n", n_operands, - oper[n_operands]->name); - } - - ++n_operands; - continue; - } - - if (get_word (&ptr, scratch) == 0) - break; - - if (asm_debug) { - printf ("asmppc: Operand %d \"%s\" : \"%s\"\n", n_operands, - oper[n_operands]->name, scratch); - } - - if ((param = parse_operand (memaddr, opc, oper[n_operands], - scratch, err)) == -1) - return 0; - - instr |= param; - ++n_operands; - } - - if (n_operands < w_operands) { - if (err) - *err = E_ASM_NUM_OPERANDS; - return 0; - } - - if (asm_debug) { - printf ("asmppc: Instruction = 0x%08lx\n", instr); - } - - return instr; -} /* asmppc */ - - - -/*====================================================================== - * Called by the assembler to interpret a single operand - * - * Arguments: - * ctx A pointer to the disassembler context record. - * - * Returns 0 if the operand is ok, or -1 if it is bad. - */ - -int parse_operand (unsigned long memaddr, struct opcode *opc, - struct operand *oper, char *txt, int *err) -{ - long data; - long mask; - int is_neg = 0; - - /*------------------------------------------------------------*/ - - mask = (1 << oper->bits) - 1; - - if (oper->hint & OH_ADDR) { - data = read_number (txt); - - if (opc->hint & H_RELATIVE) - data = data - memaddr; - - if (data < 0) - is_neg = 1; - - data >>= 2; - data &= (mask >> 1); - - if (is_neg) - data |= 1 << (oper->bits - 1); - } - - else if (oper->hint & OH_REG) { - if (txt[0] == 'r' || txt[0] == 'R') - txt++; - else if (txt[0] == '%' && (txt[1] == 'r' || txt[1] == 'R')) - txt += 2; - - data = read_number (txt); - if (data > 31) { - if (err) - *err = E_ASM_BAD_REGISTER; - return -1; - } - - data = htonl (data); - } - - else if (oper->hint & OH_SPR) { - if ((data = spr_value (txt)) == 0) { - if (err) - *err = E_ASM_BAD_SPR; - return -1; - } - } - - else if (oper->hint & OH_TBR) { - if ((data = tbr_value (txt)) == 0) { - if (err) - *err = E_ASM_BAD_TBR; - return -1; - } - } - - else { - data = htonl (read_number (txt)); - } - - return (data & mask) << oper->shift; -} /* parse_operand */ - - -char *asm_error_str (int err) -{ - switch (err) { - case E_ASM_BAD_OPCODE: - return "Bad opcode"; - case E_ASM_NUM_OPERANDS: - return "Bad number of operands"; - case E_ASM_BAD_REGISTER: - return "Bad register number"; - case E_ASM_BAD_SPR: - return "Bad SPR name or number"; - case E_ASM_BAD_TBR: - return "Bad TBR name or number"; - } - - return ""; -} /* asm_error_str */ - - - -/*====================================================================== - * Copy a word from one buffer to another, ignores leading white spaces. - * - * Arguments: - * src The address of a character pointer to the - * source buffer. - * dest A pointer to a character buffer to write the word - * into. - * - * Returns the number of non-white space characters copied, or zero. - */ - -int get_word (char **src, char *dest) -{ - char *ptr = *src; - int nchars = 0; - - /*------------------------------------------------------------*/ - - /* Eat white spaces */ - while (*ptr && isblank (*ptr)) - ptr++; - - if (*ptr == 0) { - *src = ptr; - return 0; - } - - /* Find the text of the word */ - while (*ptr && !isblank (*ptr) && (*ptr != ',')) - dest[nchars++] = *ptr++; - ptr = (*ptr == ',') ? ptr + 1 : ptr; - dest[nchars] = 0; - - *src = ptr; - return nchars; -} /* get_word */ - - - -/*====================================================================== - * Convert a numeric string to a number, be aware of base notations. - * - * Arguments: - * txt The numeric string. - * - * Returns the converted numeric value. - */ - -long read_number (char *txt) -{ - long val; - int is_neg = 0; - - /*------------------------------------------------------------*/ - - if (txt == 0 || *txt == 0) - return 0; - - if (*txt == '-') { - is_neg = 1; - ++txt; - } - - if (txt[0] == '0' && (txt[1] == 'x' || txt[1] == 'X')) /* hex */ - val = hextoul(&txt[2], NULL); - else /* decimal */ - val = dectoul(txt, NULL); - - if (is_neg) - val = -val; - - return val; -} /* read_number */ - - -int downstring (char *s) -{ - if (!s || !*s) - return 0; - - while (*s) { - if (isupper (*s)) - *s = tolower (*s); - s++; - } - - return 0; -} /* downstring */ - - - -/*====================================================================== - * Examines the instruction at the current address and determines the - * next address to be executed. This will take into account branches - * of different types so that a "step" and "next" operations can be - * supported. - * - * Arguments: - * nextaddr The address (to be filled in) of the next - * instruction to execute. This will only be a valid - * address if true is returned. - * - * step_over A flag indicating how to compute addresses for - * branch statements: - * true = Step over the branch (next) - * false = step into the branch (step) - * - * Returns true if it was able to compute the address. Returns false if - * it has a problem reading the current instruction or one of the registers. - */ - -int find_next_address (unsigned char *nextaddr, int step_over, - struct pt_regs *regs) -{ - unsigned long pc; /* SRR0 register from PPC */ - unsigned long ctr; /* CTR register from PPC */ - unsigned long cr; /* CR register from PPC */ - unsigned long lr; /* LR register from PPC */ - unsigned long instr; /* instruction at SRR0 */ - unsigned long next; /* computed instruction for 'next' */ - unsigned long step; /* computed instruction for 'step' */ - unsigned long addr = 0; /* target address operand */ - unsigned long aa = 0; /* AA operand */ - unsigned long lk = 0; /* LK operand */ - unsigned long bo = 0; /* BO operand */ - unsigned long bi = 0; /* BI operand */ - struct opcode *op = 0; /* opcode structure for 'instr' */ - int ctr_ok = 0; - int cond_ok = 0; - int conditional = 0; - int branch = 0; - - /*------------------------------------------------------------*/ - - if (nextaddr == 0 || regs == 0) { - printf ("find_next_address: bad args"); - return false; - } - - pc = regs->nip & 0xfffffffc; - instr = INSTRUCTION (pc); - - if ((op = find_opcode (instr)) == (struct opcode *) 0) { - printf ("find_next_address: can't parse opcode 0x%lx", instr); - return false; - } - - ctr = regs->ctr; - cr = regs->ccr; - lr = regs->link; - - switch (op->opcode) { - case B_OPCODE (16, 0, 0): /* bc */ - case B_OPCODE (16, 0, 1): /* bcl */ - case B_OPCODE (16, 1, 0): /* bca */ - case B_OPCODE (16, 1, 1): /* bcla */ - if (!get_operand_value (op, instr, O_BD, &addr) || - !get_operand_value (op, instr, O_BO, &bo) || - !get_operand_value (op, instr, O_BI, &bi) || - !get_operand_value (op, instr, O_AA, &aa) || - !get_operand_value (op, instr, O_LK, &lk)) - return false; - - if ((addr & (1 << 13)) != 0) - addr = addr - (1 << 14); - addr <<= 2; - conditional = 1; - branch = 1; - break; - - case I_OPCODE (18, 0, 0): /* b */ - case I_OPCODE (18, 0, 1): /* bl */ - case I_OPCODE (18, 1, 0): /* ba */ - case I_OPCODE (18, 1, 1): /* bla */ - if (!get_operand_value (op, instr, O_LI, &addr) || - !get_operand_value (op, instr, O_AA, &aa) || - !get_operand_value (op, instr, O_LK, &lk)) - return false; - - if ((addr & (1 << 23)) != 0) - addr = addr - (1 << 24); - addr <<= 2; - conditional = 0; - branch = 1; - break; - - case XL_OPCODE (19, 528, 0): /* bcctr */ - case XL_OPCODE (19, 528, 1): /* bcctrl */ - if (!get_operand_value (op, instr, O_BO, &bo) || - !get_operand_value (op, instr, O_BI, &bi) || - !get_operand_value (op, instr, O_LK, &lk)) - return false; - - addr = ctr; - aa = 1; - conditional = 1; - branch = 1; - break; - - case XL_OPCODE (19, 16, 0): /* bclr */ - case XL_OPCODE (19, 16, 1): /* bclrl */ - if (!get_operand_value (op, instr, O_BO, &bo) || - !get_operand_value (op, instr, O_BI, &bi) || - !get_operand_value (op, instr, O_LK, &lk)) - return false; - - addr = lr; - aa = 1; - conditional = 1; - branch = 1; - break; - - default: - conditional = 0; - branch = 0; - break; - } - - if (conditional) { - switch ((bo & 0x1e) >> 1) { - case 0: /* 0000y */ - if (--ctr != 0) - ctr_ok = 1; - - cond_ok = !(cr & (1 << (31 - bi))); - break; - - case 1: /* 0001y */ - if (--ctr == 0) - ctr_ok = 1; - - cond_ok = !(cr & (1 << (31 - bi))); - break; - - case 2: /* 001zy */ - ctr_ok = 1; - cond_ok = !(cr & (1 << (31 - bi))); - break; - - case 4: /* 0100y */ - if (--ctr != 0) - ctr_ok = 1; - - cond_ok = cr & (1 << (31 - bi)); - break; - - case 5: /* 0101y */ - if (--ctr == 0) - ctr_ok = 1; - - cond_ok = cr & (1 << (31 - bi)); - break; - - case 6: /* 011zy */ - ctr_ok = 1; - cond_ok = cr & (1 << (31 - bi)); - break; - - case 8: /* 1z00y */ - if (--ctr != 0) - ctr_ok = cond_ok = 1; - break; - - case 9: /* 1z01y */ - if (--ctr == 0) - ctr_ok = cond_ok = 1; - break; - - case 10: /* 1z1zz */ - ctr_ok = cond_ok = 1; - break; - } - } - - if (branch && (!conditional || (ctr_ok && cond_ok))) { - if (aa) - step = addr; - else - step = addr + pc; - - if (lk) - next = pc + 4; - else - next = step; - } else { - step = next = pc + 4; - } - - if (step_over == true) - *(unsigned long *) nextaddr = next; - else - *(unsigned long *) nextaddr = step; - - return true; -} /* find_next_address */ - - -/* - * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks - * All rights reserved. - * - * Redistribution and use in source and binary forms are freely - * permitted provided that the above copyright notice and this - * paragraph and the following disclaimer are duplicated in all - * such forms. - * - * This software is provided "AS IS" and without any express or - * implied warranties, including, without limitation, the implied - * warranties of merchantability and fitness for a particular - * purpose. - */ diff --git a/common/board_r.c b/common/board_r.c index 760c2d05ed0..f81d21a282b 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -23,10 +23,6 @@ #include <asm/cache.h> #include <asm/global_data.h> #include <u-boot/crc.h> -/* TODO: can we just include all these headers whether needed or not? */ -#if defined(CONFIG_CMD_BEDBUG) -#include <bedbug/type.h> -#endif #include <binman.h> #include <command.h> #include <console.h> @@ -37,6 +33,7 @@ #include <ide.h> #include <init.h> #include <initcall.h> +/* TODO: can we just include all these headers whether needed or not? */ #if defined(CONFIG_CMD_KGDB) #include <kgdb.h> #endif @@ -820,10 +817,6 @@ static init_fnc_t init_sequence_r[] = { */ last_stage_init, #endif -#ifdef CONFIG_CMD_BEDBUG - INIT_FUNC_WATCHDOG_RESET - bedbug_init, -#endif #if defined(CONFIG_PRAM) initr_mem, #endif diff --git a/doc/README.bedbug b/doc/README.bedbug deleted file mode 100644 index 1a2acd0f145..00000000000 --- a/doc/README.bedbug +++ /dev/null @@ -1,56 +0,0 @@ -BEDBUG Support for U-Boot --------------------------- - -These changes implement the bedbug (emBEDded deBUGger) debugger in U-Boot. - -##################### -### Modifications ### -##################### - -./common/Makefile - Included cmd_bedbug.c and bedbug.c in the Makefile. - -./common/board.c - Added call to initialize debugger on startup. - -./include/ppc_asm.tmpl - Added code to handle critical exceptions - -################# -### New Stuff ### -################# - -./include/bedbug/ppc.h -./include/bedbug/regs.h -./include/bedbug/bedbug.h -./include/bedbug/elf.h [obsoleted by new include/elf.h] -./include/bedbug/tables.h -./include/cmd_bedbug.h -./common/cmd_bedbug.c -./common/bedbug.c - Bedbug library includes code for assembling and disassembling - PowerPC instructions to/from memory as well as handling - hardware breakpoints and stepping through code. These - routines are common to all PowerPC processors. - -Bedbug support for the MPC860 ------------------------------ - -Changes: - - common/cmd_bedbug.c - Added call to initialize 860 debugger. - - arch/powerpc/cpu/mpc8xx/Makefile - Added new file "bedbug_860.c" to the makefile - - arch/powerpc/cpu/mpc8xx/start.S - Added handler for InstructionBreakpoint (0xfd00) - - arch/powerpc/cpu/mpc8xx/traps.c - Added new routine DebugException() - -New Files: - - arch/powerpc/cpu/mpc8xx/bedbug_860.c - CPU-specific routines for 860 debug registers. diff --git a/include/bedbug/bedbug.h b/include/bedbug/bedbug.h deleted file mode 100644 index 0c5d687f83e..00000000000 --- a/include/bedbug/bedbug.h +++ /dev/null @@ -1,40 +0,0 @@ -/* $Id$ */ - -#ifndef _BEDBUG_H -#define _BEDBUG_H - -#ifndef NULL -#define NULL 0 -#endif - -#define _USE_PROTOTYPES - -#ifndef isblank -#define isblank(c) isspace((int)(c)) -#endif - -#ifndef __P -#if defined(_USE_PROTOTYPES) && (defined(__STDC__) || defined(__cplusplus)) -#define __P(protos) protos /* full-blown ANSI C */ -#else -#define __P(protos) () /* traditional C preprocessor */ -#endif -#endif - -#endif /* _BEDBUG_H */ - - -/* - * Copyright (c) 2001 William L. Pitts - * All rights reserved. - * - * Redistribution and use in source and binary forms are freely - * permitted provided that the above copyright notice and this - * paragraph and the following disclaimer are duplicated in all - * such forms. - * - * This software is provided "AS IS" and without any express or - * implied warranties, including, without limitation, the implied - * warranties of merchantability and fitness for a particular - * purpose. - */ diff --git a/include/bedbug/ppc.h b/include/bedbug/ppc.h deleted file mode 100644 index 76d86fdbf76..00000000000 --- a/include/bedbug/ppc.h +++ /dev/null @@ -1,408 +0,0 @@ -/* $Id$ */ - -#ifndef _PPC_H -#define _PPC_H - -/*====================================================================== - * - * OPERANDS - * - *======================================================================*/ - -enum OP_FIELD { - O_AA = 1, O_BD, O_BI, O_BO, O_crbD, O_crbA, O_crbB, O_CRM, O_d, O_frC, O_frD, - O_frS, O_IMM, O_LI, O_LK, O_MB, O_ME, O_NB, O_OE, O_rA, O_rB, O_Rc, O_rD, - O_rS, O_SH, O_SIMM, O_SR, O_TO, O_UIMM, O_crfD, O_crfS, O_L, O_spr, O_tbr, - O_cr2 }; - -struct operand { - enum OP_FIELD field; /* The operand identifier from the - enum above */ - - char * name; /* Symbolic name of this operand */ - - unsigned int bits; /* The number of bits used by this - operand */ - - unsigned int shift; /* How far to the right the operand - should be shifted so that it is - aligned at the beginning of the - word */ - - unsigned int hint; /* A bitwise-inclusive-OR of the - values shown below. These are used - tell the disassembler how to print - this operand */ -}; - -/* Values for operand hint */ -#define OH_SILENT 0x01 /* dont print this operand */ -#define OH_ADDR 0x02 /* this operand is an address */ -#define OH_REG 0x04 /* this operand is a register */ -#define OH_SPR 0x08 /* this operand is an SPR */ -#define OH_TBR 0x10 /* this operand is a TBR */ -#define OH_OFFSET 0x20 /* this operand is an offset */ -#define OH_LITERAL 0x40 /* a literal string */ - - -/*====================================================================== - * - * OPCODES - * - *======================================================================*/ - -/* From the MPCxxx instruction set documentation, all instructions are - * 32 bits long and word aligned. Bits 0-5 always specify the primary - * opcode. Many instructions also have an extended opcode. - */ - -#define GET_OPCD(i) (((unsigned long)(i) >> 26) & 0x3f) -#define MAKE_OPCODE(i) ((((unsigned long)(i)) & 0x3f) << 26) - -/* The MPC860 User's Manual, Appendix D.4 contains the definitions of the - * instruction forms - */ - - -/*------------------------------------------------- - * I-Form Instructions: - * bX - *------------------------------------------------- - * OPCD | LI |AA|LK - *-------------------------------------------------*/ - -#define I_OPCODE(i,aa,lk) (MAKE_OPCODE(i) | (((aa) & 0x1) << 1) | ((lk) & 0x1)) -#define I_MASK I_OPCODE(0x3f,0x1,0x1) - - -/*------------------------------------------------- - * B-Form Instructions: - * bcX - *------------------------------------------------- - * OPCD | BO | BI | BD |AA|LK - *-------------------------------------------------*/ - -#define B_OPCODE(i,aa,lk) (MAKE_OPCODE(i) | (((aa) & 0x1) << 1) | ((lk) & 0x1)) -#define B_MASK B_OPCODE(0x3f,0x1,0x1) - - -/*------------------------------------------------- - * SC-Form Instructions: - * sc - *------------------------------------------------- - * OPCD | 00000 | 00000 | 00000000000000 |1|0 - *-------------------------------------------------*/ - -#define SC_OPCODE(i) (MAKE_OPCODE(i) | 0x2) -#define SC_MASK SC_OPCODE(0x3f) - - -/*------------------------------------------------- - * D-Form Instructions: - * addi addic addic. addis andi. andis. cmpi cmpli - * lbz lbzu lha lhau lhz lhzu lmw lwz lwzu mulli - * ori oris stb stbu sth sthu stmw stw stwu subfic - * twi xori xoris - *------------------------------------------------- - * OPCD | D | A | d - * OPCD | D | A | SIMM - * OPCD | S | A | d - * OPCD | S | A | UIMM - * OPCD |crfD|0|L| A | SIMM - * OPCD |crfD|0|L| A | UIMM - * OPCD | TO | A | SIMM - *-------------------------------------------------*/ - -#define D_OPCODE(i) MAKE_OPCODE(i) -#define D_MASK MAKE_OPCODE(0x3f) - - -/*------------------------------------------------- - * DS-Form Instructions: - * (none supported by MPC860) - *------------------------------------------------- - * OPCD | D | A | ds |XO - * OPCD | S | A | ds |XO - *-------------------------------------------------*/ - -#define DS_OPCODE(i,xo) (MAKE_OPCODE(i) | ((xo) & 0x3)) -#define DS_MASK DS_OPCODE(0x3f,0x1) - - -/*--------------------------------------------------- - * X-Form Instructions: - * andX andcX cmp cmpl cntlzwX dcbf dcbi dcbst dcbt - * dcbtst dcbz eciwx ecowx eieio eqvX extsbX extshX - * icbi lbzux lbxz lhaux lhax lhbrx lhzux lhxz lswi - * lswx lwarx lwbrx lwzux lwxz mcrfs mcrxr mfcr - * mfmsr mfsr mfsrin mtmsr mtsr mtsrin nandX norX - * orX orcX slwX srawX srawiX srwX stbux stbx - * sthbrx sthuxsthx stswi stswx stwbrx stwcx. stwux - * stwx sync tlbie tlbld tlbli tlbsync tw xorX - *--------------------------------------------------- - * OPCD | D | A | B | XO |0 - * OPCD | D | A | NB | XO |0 - * OPCD | D | 00000 | B | XO |0 - * OPCD | D | 00000 | 00000 | XO |0 - * OPCD | D |0| SR | 00000 | XO |0 - * OPCD | S | A | B | XO |Rc - * OPCD | S | A | B | XO |1 - * OPCD | S | A | B | XO |0 - * OPCD | S | A | NB | XO |0 - * OPCD | S | A | 00000 | XO |Rc - * OPCD | S | 00000 | B | XO |0 - * OPCD | S | 00000 | 00000 | XO |0 - * OPCD | S |0| SR | 00000 | XO |0 - * OPCD | S | A | SH | XO |Rc - * OPCD |crfD|0|L| A | SH | XO |0 - * OPCD |crfD |00| A | B | XO |0 - * OPCD |crfD |00|crfS |00| 00000 | XO |0 - * OPCD |crfD |00| 00000 | 00000 | XO |0 - * OPCD |crfD |00| 00000 | IMM |0| XO |Rc - * OPCD | TO | A | B | XO |0 - * OPCD | D | 00000 | B | XO |Rc - * OPCD | D | 00000 | 00000 | XO |Rc - * OPCD | crbD | 00000 | 00000 | XO |Rc - * OPCD | 00000 | A | B | XO |0 - * OPCD | 00000 | 00000 | B | XO |0 - * OPCD | 00000 | 00000 | 00000 | XO |0 - *---------------------------------------------------*/ - -#define X_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \ - ((rc) & 0x1)) -#define X_MASK X_OPCODE(0x3f,0x3ff,0x1) - - -/*--------------------------------------------------- - * XL-Form Instructions: - * bcctrX bclrX crand crandc creqv crnand crnor cror - * croc crxorisync mcrf rfi - *--------------------------------------------------- - * OPCD | BO | BI | 00000 | XO |LK - * OPCD | crbD | crbA | crbB | XO |0 - * OPCD |crfD |00|crfS |00| 00000 | XO |0 - * OPCD | 00000 | 00000 | 00000 | XO |0 - *---------------------------------------------------*/ - -#define XL_OPCODE(i,xo,lk) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \ - ((lk) & 0x1)) -#define XL_MASK XL_OPCODE(0x3f,0x3ff,0x1) - - -/*--------------------------------------------------- - * XFX-Form Instructions: - * mfspr mftb mtcrf mtspr - *--------------------------------------------------- - * OPCD | D | spr | XO |0 - * OPCD | D |0| CRM |0| XO |0 - * OPCD | S | spr | XO |0 - * OPCD | D | tbr | XO |0 - *---------------------------------------------------*/ - -#define XFX_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \ - ((rc) & 0x1)) -#define XFX_MASK XFX_OPCODE(0x3f,0x3ff,0x1) - - -/*--------------------------------------------------- - * XFL-Form Instructions: - * (none supported by MPC860) - *--------------------------------------------------- - * OPCD |0| FM |0| B | XO |0 - *---------------------------------------------------*/ - -#define XFL_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \ - ((rc) & 0x1)) -#define XFL_MASK XFL_OPCODE(0x3f,0x3ff,0x1) - - -/*--------------------------------------------------- - * XS-Form Instructions: - * (none supported by MPC860) - *--------------------------------------------------- - * OPCD | S | A | sh | XO |sh|LK - *---------------------------------------------------*/ - -#define XS_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x1ff) << 2) | \ - ((rc) & 0x1)) -#define XS_MASK XS_OPCODE(0x3f,0x1ff,0x1) - - -/*--------------------------------------------------- - * XO-Form Instructions: - * addX addcXaddeX addmeX addzeX divwX divwuX mulhwX - * mulhwuX mullwX negX subfX subfcX subfeX subfmeX - * subfzeX - *--------------------------------------------------- - * OPCD | D | A | B |OE| XO |Rc - * OPCD | D | A | B |0 | XO |Rc - * OPCD | D | A | 00000 |OE| XO |Rc - *---------------------------------------------------*/ - -#define XO_OPCODE(i,xo,oe,rc) (MAKE_OPCODE(i) | (((oe) & 0x1) << 10) | \ - (((xo) & 0x1ff) << 1) | ((rc) & 0x1)) -#define XO_MASK XO_OPCODE(0x3f,0x1ff,0x1,0x1) - - -/*--------------------------------------------------- - * A-Form Instructions: - * (none supported by MPC860) - *--------------------------------------------------- - * OPCD | D | A | B |00000| XO |Rc - * OPCD | D | A | B | C | XO |Rc - * OPCD | D | A | 00000 | C | XO |Rc - * OPCD | D | 00000 | B |00000| XO |Rc - *---------------------------------------------------*/ - -#define A_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x1f) << 1) | \ - ((rc) & 0x1)) -#define A_MASK A_OPCODE(0x3f,0x1f,0x1) - - -/*--------------------------------------------------- - * M-Form Instructions: - * rlwimiX rlwinmX rlwnmX - *--------------------------------------------------- - * OPCD | S | A | SH | MB | ME |Rc - * OPCD | S | A | B | MB | ME |Rc - *---------------------------------------------------*/ - -#define M_OPCODE(i,rc) (MAKE_OPCODE(i) | ((rc) & 0x1)) -#define M_MASK M_OPCODE(0x3f,0x1) - - -/*--------------------------------------------------- - * MD-Form Instructions: - * (none supported by MPC860) - *--------------------------------------------------- - * OPCD | S | A | sh | mb | XO |sh|Rc - * OPCD | S | A | sh | me | XO |sh|Rc - *---------------------------------------------------*/ - -#define MD_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x7) << 2) | \ - ((rc) & 0x1)) -#define MD_MASK MD_OPCODE(0x3f,0x7,0x1) - - -/*--------------------------------------------------- - * MDS-Form Instructions: - * (none supported by MPC860) - *--------------------------------------------------- - * OPCD | S | A | B | mb | XO |Rc - * OPCD | S | A | B | me | XO |Rc - *---------------------------------------------------*/ - -#define MDS_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0xf) << 1) | \ - ((rc) & 0x1)) -#define MDS_MASK MDS_OPCODE(0x3f,0xf,0x1) - -#define INSTRUCTION( memaddr ) ntohl(*(unsigned long *)(memaddr)) - -#define MAX_OPERANDS 8 - -struct ppc_ctx; - -struct opcode { - unsigned long opcode; /* The complete opcode as produced by - one of the XXX_OPCODE macros above */ - - unsigned long mask; /* The mask to use on an instruction - before comparing with the opcode - field to see if it matches */ - - enum OP_FIELD fields[MAX_OPERANDS]; - /* An array defining the operands for - this opcode. The values of the - array are the operand identifiers */ - - int (*hfunc)(struct ppc_ctx *); - /* Address of a function to handle the given - mnemonic */ - - char * name; /* The symbolic name of this opcode */ - - unsigned int hint; /* A bitwise-inclusive-OR of the - values shown below. These are used - tell the disassembler how to print - some operands for this opcode */ -}; - -/* values for opcode hints */ -#define H_RELATIVE 0x1 /* The address operand is relative */ -#define H_IMM_HIGH 0x2 /* [U|S]IMM field shifted high */ -#define H_RA0_IS_0 0x4 /* If rA = 0 then treat as literal 0 */ - -struct ppc_ctx { - struct opcode * op; - unsigned long instr; - unsigned int flags; - int datalen; - char data[ 256 ]; - char radix_fmt[ 8 ]; - unsigned char * virtual; -}; - - -/*====================================================================== - * - * FUNCTIONS - * - *======================================================================*/ - -/* Values for flags as passed to various ppc routines */ -#define F_RADOCTAL 0x1 /* output radix = unsigned octal */ -#define F_RADUDECIMAL 0x2 /* output radix = unsigned decimal */ -#define F_RADSDECIMAL 0x4 /* output radix = signed decimal */ -#define F_RADHEX 0x8 /* output radix = unsigned hex */ -#define F_SIMPLE 0x10 /* use simplified mnemonics */ -#define F_SYMBOL 0x20 /* use symbol lookups for addresses */ -#define F_INSTR 0x40 /* output the raw instruction */ -#define F_LOCALMEM 0x80 /* retrieve opcodes from local memory - rather than from the HMI */ -#define F_LINENO 0x100 /* show line number info if available */ -#define F_VALIDONLY 0x200 /* cache: valid entries only */ - -/* Values for assembler error codes */ -#define E_ASM_BAD_OPCODE 1 -#define E_ASM_NUM_OPERANDS 2 -#define E_ASM_BAD_REGISTER 3 -#define E_ASM_BAD_SPR 4 -#define E_ASM_BAD_TBR 5 - -extern int disppc __P((unsigned char *,unsigned char *,int, - int (*)(const char *), unsigned long)); -extern int print_source_line __P((char *,char *,int, - int (*pfunc)(const char *))); -extern int find_next_address __P((unsigned char *,int,struct pt_regs *)); -extern int handle_bc __P((struct ppc_ctx *)); -extern unsigned long asmppc __P((unsigned long,char*,int*)); -extern char *asm_error_str __P((int)); - -/*====================================================================== - * - * GLOBAL VARIABLES - * - *======================================================================*/ - -extern struct operand operands[]; -extern const unsigned int n_operands; -extern struct opcode opcodes[]; -extern const unsigned int n_opcodes; - -#endif /* _PPC_H */ - - -/* - * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks - * All rights reserved. - * - * Redistribution and use in source and binary forms are freely - * permitted provided that the above copyright notice and this - * paragraph and the following disclaimer are duplicated in all - * such forms. - * - * This software is provided "AS IS" and without any express or - * implied warranties, including, without limitation, the implied - * warranties of merchantability and fitness for a particular - * purpose. - */ diff --git a/include/bedbug/regs.h b/include/bedbug/regs.h deleted file mode 100644 index 304a336cc20..00000000000 --- a/include/bedbug/regs.h +++ /dev/null @@ -1,400 +0,0 @@ -/* $Id$ */ - -#ifndef _REGS_H -#define _REGS_H - -/* Special Purpose Registers */ - -#define SPR_CR -1 -#define SPR_MSR -2 - -#define SPR_XER 1 -#define SPR_LR 8 -#define SPR_CTR 9 -#define SPR_DSISR 18 -#define SPR_DAR 19 -#define SPR_DEC 22 -#define SPR_SRR0 26 -#define SPR_SRR1 27 -#define SPR_EIE 80 -#define SPR_EID 81 -#define SPR_CMPA 144 -#define SPR_CMPB 145 -#define SPR_CMPC 146 -#define SPR_CMPD 147 -#define SPR_ICR 148 -#define SPR_DER 149 -#define SPR_COUNTA 150 -#define SPR_COUNTB 151 -#define SPR_CMPE 152 -#define SPR_CMPF 153 -#define SPR_CMPG 154 -#define SPR_CMPH 155 -#define SPR_LCTRL1 156 -#define SPR_LCTRL2 157 -#define SPR_ICTRL 158 -#define SPR_BAR 159 -#define SPR_USPRG0 256 -#define SPR_SPRG4_RO 260 -#define SPR_SPRG5_RO 261 -#define SPR_SPRG6_RO 262 -#define SPR_SPRG7_RO 263 -#define SPR_SPRG0 272 -#define SPR_SPRG1 273 -#define SPR_SPRG2 274 -#define SPR_SPRG3 275 -#define SPR_SPRG4 276 -#define SPR_SPRG5 277 -#define SPR_SPRG6 278 -#define SPR_SPRG7 279 -#define SPR_EAR 282 /* MPC603e core */ -#define SPR_TBL 284 -#define SPR_TBU 285 -#define SPR_PVR 287 -#define SPR_IC_CST 560 -#define SPR_IC_ADR 561 -#define SPR_IC_DAT 562 -#define SPR_DC_CST 568 -#define SPR_DC_ADR 569 -#define SPR_DC_DAT 570 -#define SPR_DPDR 630 -#define SPR_IMMR 638 -#define SPR_MI_CTR 784 -#define SPR_MI_AP 786 -#define SPR_MI_EPN 787 -#define SPR_MI_TWC 789 -#define SPR_MI_RPN 790 -#define SPR_MD_CTR 792 -#define SPR_M_CASID 793 -#define SPR_MD_AP 794 -#define SPR_MD_EPN 795 -#define SPR_M_TWB 796 -#define SPR_MD_TWC 797 -#define SPR_MD_RPN 798 -#define SPR_M_TW 799 -#define SPR_MI_DBCAM 816 -#define SPR_MI_DBRAM0 817 -#define SPR_MI_DBRAM1 818 -#define SPR_MD_DBCAM 824 -#define SPR_MD_DBRAM0 825 -#define SPR_MD_DBRAM1 826 -#define SPR_ZPR 944 -#define SPR_PID 945 -#define SPR_CCR0 947 -#define SPR_IAC3 948 -#define SPR_IAC4 949 -#define SPR_DVC1 950 -#define SPR_DVC2 951 -#define SPR_SGR 953 -#define SPR_DCWR 954 -#define SPR_SLER 955 -#define SPR_SU0R 956 -#define SPR_DBCR1 957 -#define SPR_ICDBDR 979 -#define SPR_ESR 980 -#define SPR_DEAR 981 -#define SPR_EVPR 982 -#define SPR_TSR 984 -#define SPR_TCR 986 -#define SPR_PIT 987 -#define SPR_SRR2 990 -#define SPR_SRR3 991 -#define SPR_DBSR 1008 -#define SPR_DBCR0 1010 -#define SPR_IABR 1010 /* MPC603e core */ -#define SPR_IAC1 1012 -#define SPR_IAC2 1013 -#define SPR_DAC1 1014 -#define SPR_DAC2 1015 -#define SPR_DCCR 1018 -#define SPR_ICCR 1019 - -/* Bits for the DBCR0 register */ -#define DBCR0_EDM 0x80000000 -#define DBCR0_IDM 0x40000000 -#define DBCR0_RST 0x30000000 -#define DBCR0_IC 0x08000000 -#define DBCR0_BT 0x04000000 -#define DBCR0_EDE 0x02000000 -#define DBCR0_TDE 0x01000000 -#define DBCR0_IA1 0x00800000 -#define DBCR0_IA2 0x00400000 -#define DBCR0_IA12 0x00200000 -#define DBCR0_IA12X 0x00100000 -#define DBCR0_IA3 0x00080000 -#define DBCR0_IA4 0x00040000 -#define DBCR0_IA34 0x00020000 -#define DBCR0_IA34X 0x00010000 -#define DBCR0_IA12T 0x00008000 -#define DBCR0_IA34T 0x00004000 -#define DBCR0_FT 0x00000001 - -/* Bits for the DBCR1 register */ -#define DBCR1_D1R 0x80000000 -#define DBCR1_D2R 0x40000000 -#define DBCR1_D1W 0x20000000 -#define DBCR1_D2W 0x10000000 -#define DBCR1_D1S 0x0C000000 -#define DBCR1_D2S 0x03000000 -#define DBCR1_DA12 0x00800000 -#define DBCR1_DA12X 0x00400000 -#define DBCR1_DV1M 0x000C0000 -#define DBCR1_DV2M 0x00030000 -#define DBCR1_DV1BE 0x0000F000 -#define DBCR1_DV2BE 0x00000F00 - -/* - * DBSR bits which have conflicting definitions on true Book E versus PPC40x - */ -#ifdef CONFIG_BOOKE -#define DBSR_IA1 0x00800000 /* Instr Address Compare 1 Event */ -#define DBSR_IA2 0x00400000 /* Instr Address Compare 2 Event */ -#define DBSR_IA3 0x00200000 /* Instr Address Compare 3 Event */ -#define DBSR_IA4 0x00100000 /* Instr Address Compare 4 Event */ -#endif -#define DBSR_IA1 0x04000000 /* Instr Address Compare 1 Event */ -#define DBSR_IA2 0x02000000 /* Instr Address Compare 2 Event */ -#define DBSR_IA3 0x00080000 /* Instr Address Compare 3 Event */ -#define DBSR_IA4 0x00040000 /* Instr Address Compare 4 Event */ - -struct spr_info { - int spr_val; - char spr_name[ 10 ]; -}; - -extern struct spr_info spr_map[]; -extern const unsigned int n_sprs; - - -#define SET_REGISTER( str, val ) \ -({ unsigned long __value = (val); \ - asm volatile( str : : "r" (__value)); \ - __value; }) - -#define GET_REGISTER( str ) \ -({ unsigned long __value; \ - asm volatile( str : "=r" (__value) : ); \ - __value; }) - -#define GET_CR() GET_REGISTER( "mfcr %0" ) -#define SET_CR(val) SET_REGISTER( "mtcr %0", val ) -#define GET_MSR() GET_REGISTER( "mfmsr %0" ) -#define SET_MSR(val) SET_REGISTER( "mtmsr %0", val ) -#define GET_XER() GET_REGISTER( "mfspr %0,1" ) -#define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val ) -#define GET_LR() GET_REGISTER( "mfspr %0,8" ) -#define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val ) -#define GET_CTR() GET_REGISTER( "mfspr %0,9" ) -#define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val ) -#define GET_DSISR() GET_REGISTER( "mfspr %0,18" ) -#define SET_DSISR(val) SET_REGISTER( "mtspr 18,%0", val ) -#define GET_DAR() GET_REGISTER( "mfspr %0,19" ) -#define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val ) -#define GET_DEC() GET_REGISTER( "mfspr %0,22" ) -#define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val ) -#define GET_SRR0() GET_REGISTER( "mfspr %0,26" ) -#define SET_SRR0(val) SET_REGISTER( "mtspr 26,%0", val ) -#define GET_SRR1() GET_REGISTER( "mfspr %0,27" ) -#define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val ) -#define GET_EIE() GET_REGISTER( "mfspr %0,80" ) -#define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val ) -#define GET_EID() GET_REGISTER( "mfspr %0,81" ) -#define SET_EID(val) SET_REGISTER( "mtspr 81,%0", val ) -#define GET_CMPA() GET_REGISTER( "mfspr %0,144" ) -#define SET_CMPA(val) SET_REGISTER( "mtspr 144,%0", val ) -#define GET_CMPB() GET_REGISTER( "mfspr %0,145" ) -#define SET_CMPB(val) SET_REGISTER( "mtspr 145,%0", val ) -#define GET_CMPC() GET_REGISTER( "mfspr %0,146" ) -#define SET_CMPC(val) SET_REGISTER( "mtspr 146,%0", val ) -#define GET_CMPD() GET_REGISTER( "mfspr %0,147" ) -#define SET_CMPD(val) SET_REGISTER( "mtspr 147,%0", val ) -#define GET_ICR() GET_REGISTER( "mfspr %0,148" ) -#define SET_ICR(val) SET_REGISTER( "mtspr 148,%0", val ) -#define GET_DER() GET_REGISTER( "mfspr %0,149" ) -#define SET_DER(val) SET_REGISTER( "mtspr 149,%0", val ) -#define GET_COUNTA() GET_REGISTER( "mfspr %0,150" ) -#define SET_COUNTA(val) SET_REGISTER( "mtspr 150,%0", val ) -#define GET_COUNTB() GET_REGISTER( "mfspr %0,151" ) -#define SET_COUNTB(val) SET_REGISTER( "mtspr 151,%0", val ) -#define GET_CMPE() GET_REGISTER( "mfspr %0,152" ) -#define SET_CMPE(val) SET_REGISTER( "mtspr 152,%0", val ) -#define GET_CMPF() GET_REGISTER( "mfspr %0,153" ) -#define SET_CMPF(val) SET_REGISTER( "mtspr 153,%0", val ) -#define GET_CMPG() GET_REGISTER( "mfspr %0,154" ) -#define SET_CMPG(val) SET_REGISTER( "mtspr 154,%0", val ) -#define GET_CMPH() GET_REGISTER( "mfspr %0,155" ) -#define SET_CMPH(val) SET_REGISTER( "mtspr 155,%0", val ) -#define GET_LCTRL1() GET_REGISTER( "mfspr %0,156" ) -#define SET_LCTRL1(val) SET_REGISTER( "mtspr 156,%0", val ) -#define GET_LCTRL2() GET_REGISTER( "mfspr %0,157" ) -#define SET_LCTRL2(val) SET_REGISTER( "mtspr 157,%0", val ) -#define GET_ICTRL() GET_REGISTER( "mfspr %0,158" ) -#define SET_ICTRL(val) SET_REGISTER( "mtspr 158,%0", val ) -#define GET_BAR() GET_REGISTER( "mfspr %0,159" ) -#define SET_BAR(val) SET_REGISTER( "mtspr 159,%0", val ) -#define GET_USPRG0() GET_REGISTER( "mfspr %0,256" ) -#define SET_USPRG0(val) SET_REGISTER( "mtspr 256,%0", val ) -#define GET_SPRG4_RO() GET_REGISTER( "mfspr %0,260" ) -#define SET_SPRG4_RO(val) SET_REGISTER( "mtspr 260,%0", val ) -#define GET_SPRG5_RO() GET_REGISTER( "mfspr %0,261" ) -#define SET_SPRG5_RO(val) SET_REGISTER( "mtspr 261,%0", val ) -#define GET_SPRG6_RO() GET_REGISTER( "mfspr %0,262" ) -#define SET_SPRG6_RO(val) SET_REGISTER( "mtspr 262,%0", val ) -#define GET_SPRG7_RO() GET_REGISTER( "mfspr %0,263" ) -#define SET_SPRG7_RO(val) SET_REGISTER( "mtspr 263,%0", val ) -#define GET_SPRG0() GET_REGISTER( "mfspr %0,272" ) -#define SET_SPRG0(val) SET_REGISTER( "mtspr 272,%0", val ) -#define GET_SPRG1() GET_REGISTER( "mfspr %0,273" ) -#define SET_SPRG1(val) SET_REGISTER( "mtspr 273,%0", val ) -#define GET_SPRG2() GET_REGISTER( "mfspr %0,274" ) -#define SET_SPRG2(val) SET_REGISTER( "mtspr 274,%0", val ) -#define GET_SPRG3() GET_REGISTER( "mfspr %0,275" ) -#define SET_SPRG3(val) SET_REGISTER( "mtspr 275,%0", val ) -#define GET_SPRG4() GET_REGISTER( "mfspr %0,276" ) -#define SET_SPRG4(val) SET_REGISTER( "mtspr 276,%0", val ) -#define GET_SPRG5() GET_REGISTER( "mfspr %0,277" ) -#define SET_SPRG5(val) SET_REGISTER( "mtspr 277,%0", val ) -#define GET_SPRG6() GET_REGISTER( "mfspr %0,278" ) -#define SET_SPRG6(val) SET_REGISTER( "mtspr 278,%0", val ) -#define GET_SPRG7() GET_REGISTER( "mfspr %0,279" ) -#define SET_SPRG7(val) SET_REGISTER( "mtspr 279,%0", val ) -#define GET_EAR() GET_REGISTER( "mfspr %0,282" ) -#define SET_EAR(val) SET_REGISTER( "mtspr 282,%0", val ) -#define GET_TBL() GET_REGISTER( "mfspr %0,284" ) -#define SET_TBL(val) SET_REGISTER( "mtspr 284,%0", val ) -#define GET_TBU() GET_REGISTER( "mfspr %0,285" ) -#define SET_TBU(val) SET_REGISTER( "mtspr 285,%0", val ) -#define GET_PVR() GET_REGISTER( "mfspr %0,287" ) -#define SET_PVR(val) SET_REGISTER( "mtspr 287,%0", val ) -#define GET_IC_CST() GET_REGISTER( "mfspr %0,560" ) -#define SET_IC_CST(val) SET_REGISTER( "mtspr 560,%0", val ) -#define GET_IC_ADR() GET_REGISTER( "mfspr %0,561" ) -#define SET_IC_ADR(val) SET_REGISTER( "mtspr 561,%0", val ) -#define GET_IC_DAT() GET_REGISTER( "mfspr %0,562" ) -#define SET_IC_DAT(val) SET_REGISTER( "mtspr 562,%0", val ) -#define GET_DC_CST() GET_REGISTER( "mfspr %0,568" ) -#define SET_DC_CST(val) SET_REGISTER( "mtspr 568,%0", val ) -#define GET_DC_ADR() GET_REGISTER( "mfspr %0,569" ) -#define SET_DC_ADR(val) SET_REGISTER( "mtspr 569,%0", val ) -#define GET_DC_DAT() GET_REGISTER( "mfspr %0,570" ) -#define SET_DC_DAT(val) SET_REGISTER( "mtspr 570,%0", val ) -#define GET_DPDR() GET_REGISTER( "mfspr %0,630" ) -#define SET_DPDR(val) SET_REGISTER( "mtspr 630,%0", val ) -#define GET_IMMR() GET_REGISTER( "mfspr %0,638" ) -#define SET_IMMR(val) SET_REGISTER( "mtspr 638,%0", val ) -#define GET_MI_CTR() GET_REGISTER( "mfspr %0,784" ) -#define SET_MI_CTR(val) SET_REGISTER( "mtspr 784,%0", val ) -#define GET_MI_AP() GET_REGISTER( "mfspr %0,786" ) -#define SET_MI_AP(val) SET_REGISTER( "mtspr 786,%0", val ) -#define GET_MI_EPN() GET_REGISTER( "mfspr %0,787" ) -#define SET_MI_EPN(val) SET_REGISTER( "mtspr 787,%0", val ) -#define GET_MI_TWC() GET_REGISTER( "mfspr %0,789" ) -#define SET_MI_TWC(val) SET_REGISTER( "mtspr 789,%0", val ) -#define GET_MI_RPN() GET_REGISTER( "mfspr %0,790" ) -#define SET_MI_RPN(val) SET_REGISTER( "mtspr 790,%0", val ) -#define GET_MD_CTR() GET_REGISTER( "mfspr %0,792" ) -#define SET_MD_CTR(val) SET_REGISTER( "mtspr 792,%0", val ) -#define GET_M_CASID() GET_REGISTER( "mfspr %0,793" ) -#define SET_M_CASID(val) SET_REGISTER( "mtspr 793,%0", val ) -#define GET_MD_AP() GET_REGISTER( "mfspr %0,794" ) -#define SET_MD_AP(val) SET_REGISTER( "mtspr ,794%0", val ) -#define GET_MD_EPN() GET_REGISTER( "mfspr %0,795" ) -#define SET_MD_EPN(val) SET_REGISTER( "mtspr 795,%0", val ) -#define GET_M_TWB() GET_REGISTER( "mfspr %0,796" ) -#define SET_M_TWB(val) SET_REGISTER( "mtspr 796,%0", val ) -#define GET_MD_TWC() GET_REGISTER( "mfspr %0,797" ) -#define SET_MD_TWC(val) SET_REGISTER( "mtspr 797,%0", val ) -#define GET_MD_RPN() GET_REGISTER( "mfspr %0,798" ) -#define SET_MD_RPN(val) SET_REGISTER( "mtspr 798,%0", val ) -#define GET_M_TW() GET_REGISTER( "mfspr %0,799" ) -#define SET_M_TW(val) SET_REGISTER( "mtspr 799,%0", val ) -#define GET_MI_DBCAM() GET_REGISTER( "mfspr %0,816" ) -#define SET_MI_DBCAM(val) SET_REGISTER( "mtspr 816,%0", val ) -#define GET_MI_DBRAM0() GET_REGISTER( "mfspr %0,817" ) -#define SET_MI_DBRAM0(val) SET_REGISTER( "mtspr 817,%0", val ) -#define GET_MI_DBRAM1() GET_REGISTER( "mfspr %0,818" ) -#define SET_MI_DBRAM1(val) SET_REGISTER( "mtspr 818,%0", val ) -#define GET_MD_DBCAM() GET_REGISTER( "mfspr %0,824" ) -#define SET_MD_DBCA(val) SET_REGISTER( "mtspr 824,%0", val ) -#define GET_MD_DBRAM0() GET_REGISTER( "mfspr %0,825" ) -#define SET_MD_DBRAM0(val) SET_REGISTER( "mtspr 825,%0", val ) -#define GET_MD_DBRAM1() GET_REGISTER( "mfspr %0,826" ) -#define SET_MD_DBRAM1(val) SET_REGISTER( "mtspr 826,%0", val ) -#define GET_ZPR() GET_REGISTER( "mfspr %0,944" ) -#define SET_ZPR(val) SET_REGISTER( "mtspr 944,%0", val ) -#define GET_PID() GET_REGISTER( "mfspr %0,945" ) -#define SET_PID(val) SET_REGISTER( "mtspr 945,%0", val ) -#define GET_CCR0() GET_REGISTER( "mfspr %0,947" ) -#define SET_CCR0(val) SET_REGISTER( "mtspr 947,%0", val ) -#define GET_IAC3() GET_REGISTER( "mfspr %0,948" ) -#define SET_IAC3(val) SET_REGISTER( "mtspr 948,%0", val ) -#define GET_IAC4() GET_REGISTER( "mfspr %0,949" ) -#define SET_IAC4(val) SET_REGISTER( "mtspr 949,%0", val ) -#define GET_DVC1() GET_REGISTER( "mfspr %0,950" ) -#define SET_DVC1(val) SET_REGISTER( "mtspr 950,%0", val ) -#define GET_DVC2() GET_REGISTER( "mfspr %0,951" ) -#define SET_DVC2(val) SET_REGISTER( "mtspr 951,%0", val ) -#define GET_SGR() GET_REGISTER( "mfspr %0,953" ) -#define SET_SGR(val) SET_REGISTER( "mtspr 953,%0", val ) -#define GET_DCWR() GET_REGISTER( "mfspr %0,954" ) -#define SET_DCWR(val) SET_REGISTER( "mtspr 954,%0", val ) -#define GET_SLER() GET_REGISTER( "mfspr %0,955" ) -#define SET_SLER(val) SET_REGISTER( "mtspr 955,%0", val ) -#define GET_SU0R() GET_REGISTER( "mfspr %0,956" ) -#define SET_SU0R(val) SET_REGISTER( "mtspr 956,%0", val ) -#define GET_DBCR1() GET_REGISTER( "mfspr %0,957" ) -#define SET_DBCR1(val) SET_REGISTER( "mtspr 957,%0", val ) -#define GET_ICDBDR() GET_REGISTER( "mfspr %0,979" ) -#define SET_ICDBDR(val) SET_REGISTER( "mtspr 979,%0", val ) -#define GET_ESR() GET_REGISTER( "mfspr %0,980" ) -#define SET_ESR(val) SET_REGISTER( "mtspr 980,%0", val ) -#define GET_DEAR() GET_REGISTER( "mfspr %0,981" ) -#define SET_DEAR(val) SET_REGISTER( "mtspr 981,%0", val ) -#define GET_EVPR() GET_REGISTER( "mfspr %0,982" ) -#define SET_EVPR(val) SET_REGISTER( "mtspr 982,%0", val ) -#define GET_TSR() GET_REGISTER( "mfspr %0,984" ) -#define SET_TSR(val) SET_REGISTER( "mtspr 984,%0", val ) -#define GET_TCR() GET_REGISTER( "mfspr %0,986" ) -#define SET_TCR(val) SET_REGISTER( "mtspr 986,%0", val ) -#define GET_PIT() GET_REGISTER( "mfspr %0,987" ) -#define SET_PIT(val) SET_REGISTER( "mtspr 987,%0", val ) -#define GET_SRR2() GET_REGISTER( "mfspr %0,990" ) -#define SET_SRR2(val) SET_REGISTER( "mtspr 990,%0", val ) -#define GET_SRR3() GET_REGISTER( "mfspr %0,991" ) -#define SET_SRR3(val) SET_REGISTER( "mtspr 991,%0", val ) -#define GET_DBSR() GET_REGISTER( "mfspr %0,1008" ) -#define SET_DBSR(val) SET_REGISTER( "mtspr 1008,%0", val ) -#define GET_DBCR0() GET_REGISTER( "mfspr %0,1010" ) -#define SET_DBCR0(val) SET_REGISTER( "mtspr 1010,%0", val ) -#define GET_IABR() GET_REGISTER( "mfspr %0,1010" ) -#define SET_IABR(val) SET_REGISTER( "mtspr 1010,%0", val ) -#define GET_IAC1() GET_REGISTER( "mfspr %0,1012" ) -#define SET_IAC1(val) SET_REGISTER( "mtspr 1012,%0", val ) -#define GET_IAC2() GET_REGISTER( "mfspr %0,1013" ) -#define SET_IAC2(val) SET_REGISTER( "mtspr 1013,%0", val ) -#define GET_DAC1() GET_REGISTER( "mfspr %0,1014" ) -#define SET_DAC1(val) SET_REGISTER( "mtspr 1014,%0", val ) -#define GET_DAC2() GET_REGISTER( "mfspr %0,1015" ) -#define SET_DAC2(val) SET_REGISTER( "mtspr 1015,%0", val ) -#define GET_DCCR() GET_REGISTER( "mfspr %0,1018" ) -#define SET_DCCR(val) SET_REGISTER( "mtspr 1018,%0", val ) -#define GET_ICCR() GET_REGISTER( "mfspr %0,1019" ) -#define SET_ICCR(val) SET_REGISTER( "mtspr 1019,%0", val ) - -#endif /* _REGS_H */ - - -/* - * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks - * All rights reserved. - * - * Redistribution and use in source and binary forms are freely - * permitted provided that the above copyright notice and this - * paragraph and the following disclaimer are duplicated in all - * such forms. - * - * This software is provided "AS IS" and without any express or - * implied warranties, including, without limitation, the implied - * warranties of merchantability and fitness for a particular - * purpose. - */ diff --git a/include/bedbug/tables.h b/include/bedbug/tables.h deleted file mode 100644 index e675de3209f..00000000000 --- a/include/bedbug/tables.h +++ /dev/null @@ -1,601 +0,0 @@ -/* $Id$ */ - -#ifndef TABLES_H -#define TABLES_H - -/* This is only included by common/bedbug.c, and depends on the following - * files to already be included - * common.h - * bedbug/bedbug.h - * bedbug/ppc.h - * bedbug/regs.h - */ - -struct operand operands[] = { - /*Field Name Bits Shift Hint Position */ - /*----- ------ ----- ----- ---- ------------ */ - { O_AA, "O_AA", 1, 1, OH_SILENT }, /* 30 */ - { O_BD, "O_BD", 14, 2, OH_ADDR }, /* 16-29 */ - { O_BI, "O_BI", 5, 16, 0 }, /* 11-15 */ - { O_BO, "O_BO", 5, 21, 0 }, /* 6-10 */ - { O_crbD, "O_crbD", 5, 21, 0 }, /* 6-10 */ - { O_crbA, "O_crbA", 5, 16, 0 }, /* 11-15 */ - { O_crbB, "O_crbB", 5, 11, 0 }, /* 16-20 */ - { O_CRM, "O_CRM", 8, 12, 0 }, /* 12-19 */ - { O_d, "O_d", 15, 0, OH_OFFSET }, /* 16-31 */ - { O_frC, "O_frC", 5, 6, 0 }, /* 21-25 */ - { O_frD, "O_frD", 5, 21, 0 }, /* 6-10 */ - { O_frS, "O_frS", 5, 21, 0 }, /* 6-10 */ - { O_IMM, "O_IMM", 4, 12, 0 }, /* 16-19 */ - { O_LI, "O_LI", 24, 2, OH_ADDR }, /* 6-29 */ - { O_LK, "O_LK", 1, 0, OH_SILENT }, /* 31 */ - { O_MB, "O_MB", 5, 6, 0 }, /* 21-25 */ - { O_ME, "O_ME", 5, 1, 0 }, /* 26-30 */ - { O_NB, "O_NB", 5, 11, 0 }, /* 16-20 */ - { O_OE, "O_OE", 1, 10, OH_SILENT }, /* 21 */ - { O_rA, "O_rA", 5, 16, OH_REG }, /* 11-15 */ - { O_rB, "O_rB", 5, 11, OH_REG }, /* 16-20 */ - { O_Rc, "O_Rc", 1, 0, OH_SILENT }, /* 31 */ - { O_rD, "O_rD", 5, 21, OH_REG }, /* 6-10 */ - { O_rS, "O_rS", 5, 21, OH_REG }, /* 6-10 */ - { O_SH, "O_SH", 5, 11, 0 }, /* 16-20 */ - { O_SIMM, "O_SIMM", 16, 0, 0 }, /* 16-31 */ - { O_SR, "O_SR", 4, 16, 0 }, /* 12-15 */ - { O_TO, "O_TO", 5, 21, 0 }, /* 6-10 */ - { O_UIMM, "O_UIMM", 16, 0, 0 }, /* 16-31 */ - { O_crfD, "O_crfD", 3, 23, 0 }, /* 6- 8 */ - { O_crfS, "O_crfS", 3, 18, 0 }, /* 11-13 */ - { O_L, "O_L", 1, 21, 0 }, /* 10 */ - { O_spr, "O_spr", 10, 11, OH_SPR }, /* 11-20 */ - { O_tbr, "O_tbr", 10, 11, OH_TBR }, /* 11-20 */ - { O_cr2, "O_cr2", 0, 0, OH_LITERAL }, /* "cr2" */ -}; - -const unsigned int n_operands = sizeof(operands) / sizeof(operands[0]); - -/* A note about the fields array in the opcodes structure: - The operands are listed in the order they appear in the output. - - This table is arranged in numeric order of the opcode. Note that some - opcodes have defined bits in odd places so not all forms of a command - will be in the same place. This is done so that a binary search can be - done to find the opcodes. Note that table D.2 in the MPC860 User's - Manual "Instructions Sorted by Opcode" does not account for these - bit locations */ - -struct opcode opcodes[] = { - { D_OPCODE(3), D_MASK, {O_TO, O_rA, O_SIMM, 0}, - 0, "twi", 0 }, - { D_OPCODE(7), D_MASK, {O_rD, O_rA, O_SIMM, 0}, - 0, "mulli", 0 }, - { D_OPCODE(8), D_MASK, {O_rD, O_rA, O_SIMM, 0}, - 0, "subfic", 0 }, - { D_OPCODE(10), D_MASK, {O_crfD, O_L, O_rA, O_UIMM, 0}, - 0, "cmpli", 0 }, - { D_OPCODE(11), D_MASK, {O_crfD, O_L, O_rA, O_SIMM, 0}, - 0, "cmpi", 0 }, - { D_OPCODE(12), D_MASK, {O_rD, O_rA, O_SIMM, 0}, - 0, "addic", 0 }, - { D_OPCODE(13), D_MASK, {O_rD, O_rA, O_SIMM, 0}, - 0, "addic.", 0 }, - { D_OPCODE(14), D_MASK, {O_rD, O_rA, O_SIMM, 0}, - 0, "addi", H_RA0_IS_0 }, - { D_OPCODE(15), D_MASK, {O_rD, O_rA, O_SIMM, 0}, - 0, "addis", H_RA0_IS_0|H_IMM_HIGH }, - { B_OPCODE(16,0,0), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0}, - handle_bc, "bc", H_RELATIVE }, - { B_OPCODE(16,0,1), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0}, - 0, "bcl", H_RELATIVE }, - { B_OPCODE(16,1,0), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0}, - 0, "bca", 0 }, - { B_OPCODE(16,1,1), B_MASK, {O_BO, O_BI, O_BD, O_AA, O_LK, 0}, - 0, "bcla", 0 }, - { SC_OPCODE(17), SC_MASK, {0}, - 0, "sc", 0 }, - { I_OPCODE(18,0,0), I_MASK, {O_LI, O_AA, O_LK, 0}, - 0, "b", H_RELATIVE }, - { I_OPCODE(18,0,1), I_MASK, {O_LI, O_AA, O_LK, 0}, - 0, "bl", H_RELATIVE }, - { I_OPCODE(18,1,0), I_MASK, {O_LI, O_AA, O_LK, 0}, - 0, "ba", 0 }, - { I_OPCODE(18,1,1), I_MASK, {O_LI, O_AA, O_LK, 0}, - 0, "bla", 0 }, - { XL_OPCODE(19,0,0), XL_MASK, {O_crfD, O_crfS}, - 0, "mcrf", 0 }, - { XL_OPCODE(19,16,0), XL_MASK, {O_BO, O_BI, O_LK, 0}, - 0, "bclr", 0 }, - { XL_OPCODE(19,16,1), XL_MASK, {O_BO, O_BI, O_LK, 0}, - 0, "bclrl", 0 }, - { XL_OPCODE(19,33,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, - 0, "crnor", 0 }, - { XL_OPCODE(19,50,0), XL_MASK, {0}, - 0, "rfi", 0 }, - { XL_OPCODE(19,129,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, - 0, "crandc", 0 }, - { XL_OPCODE(19,150,0), XL_MASK, {0}, - 0, "isync", 0 }, - { XL_OPCODE(19,193,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, - 0, "crxor", 0 }, - { XL_OPCODE(19,225,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, - 0, "crnand", 0 }, - { XL_OPCODE(19,257,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, - 0, "crand", 0 }, - { XL_OPCODE(19,289,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, - 0, "creqv", 0 }, - { XL_OPCODE(19,417,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, - 0, "crorc", 0 }, - { XL_OPCODE(19,449,0), XL_MASK, {O_crbD, O_crbA, O_crbB, 0}, - 0, "cror", 0 }, - { XL_OPCODE(19,528,0), XL_MASK, {O_BO, O_BI, O_LK, 0}, - 0, "bcctr", 0 }, - { XL_OPCODE(19,528,1), XL_MASK, {O_BO, O_BI, O_LK, 0}, - 0, "bcctrl", 0 }, - { M_OPCODE(20,0), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0}, - 0, "rlwimi", 0 }, - { M_OPCODE(20,1), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0}, - 0, "rlwimi.", 0 }, - { M_OPCODE(21,0), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0}, - 0, "rlwinm", 0 }, - { M_OPCODE(21,1), M_MASK, {O_rA, O_rS, O_SH, O_MB, O_ME, O_Rc, 0}, - 0, "rlwinm.", 0 }, - { M_OPCODE(23,0), M_MASK, {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0}, - 0, "rlwnm", 0 }, - { M_OPCODE(23,1), M_MASK, {O_rA, O_rS, O_rB, O_MB, O_ME, O_Rc, 0}, - 0, "rlwnm.", 0 }, - { D_OPCODE(24), D_MASK, {O_rA, O_rS, O_UIMM, 0}, - 0, "ori", 0 }, - { D_OPCODE(25), D_MASK, {O_rA, O_rS, O_UIMM, 0}, - 0, "oris", H_IMM_HIGH }, - { D_OPCODE(26), D_MASK, {O_rA, O_rS, O_UIMM, 0}, - 0, "xori", 0 }, - { D_OPCODE(27), D_MASK, {O_rA, O_rS, O_UIMM, 0}, - 0, "xoris", H_IMM_HIGH }, - { D_OPCODE(28), D_MASK, {O_rA, O_rS, O_UIMM, 0}, - 0, "andi.", 0 }, - { D_OPCODE(29), D_MASK, {O_rA, O_rS, O_UIMM, 0}, - 0, "andis.", H_IMM_HIGH }, - { X_OPCODE(31,0,0), X_MASK, {O_crfD, O_L, O_rA, O_rB, 0}, - 0, "cmp", 0 }, - { X_OPCODE(31,4,0), X_MASK, {O_TO, O_rA, O_rB, 0}, - 0, "tw", 0 }, - { XO_OPCODE(31,8,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subfc", 0 }, - { XO_OPCODE(31,8,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subfc.", 0 }, - { XO_OPCODE(31,10,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "addc", 0 }, - { XO_OPCODE(31,10,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "addc.", 0 }, - { XO_OPCODE(31,11,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0}, - 0, "mulhwu", 0 }, - { XO_OPCODE(31,11,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0}, - 0, "mulhwu.", 0 }, - { X_OPCODE(31,19,0), X_MASK, {O_rD, 0}, - 0, "mfcr", 0 }, - { X_OPCODE(31,20,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lwarx", H_RA0_IS_0 }, - { X_OPCODE(31,23,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lwzx", H_RA0_IS_0 }, - { X_OPCODE(31,24,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "slw", 0 }, - { X_OPCODE(31,24,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "slw.", 0 }, - { X_OPCODE(31,26,0), X_MASK, {O_rA, O_rS, O_Rc, 0 }, - 0, "cntlzw", 0 }, - { X_OPCODE(31,26,1), X_MASK, {O_rA, O_rS, O_Rc, 0}, - 0, "cntlzw.", 0 }, - { X_OPCODE(31,28,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "and", 0 }, - { X_OPCODE(31,28,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "and.", 0 }, - { X_OPCODE(31,32,0), X_MASK, {O_crfD, O_L, O_rA, O_rB, 0}, - 0, "cmpl", 0 }, - { XO_OPCODE(31,40,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subf", 0 }, - { XO_OPCODE(31,40,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subf.", 0 }, - { X_OPCODE(31,54,0), X_MASK, {O_rA, O_rB, 0}, - 0, "dcbst", H_RA0_IS_0 }, - { X_OPCODE(31,55,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lwzux", 0 }, - { X_OPCODE(31,60,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "andc", 0 }, - { X_OPCODE(31,60,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "andc.", 0 }, - { XO_OPCODE(31,75,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0}, - 0, "mulhw", 0 }, - { XO_OPCODE(31,75,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_Rc, 0}, - 0, "mulhw.", 0 }, - { X_OPCODE(31,83,0), X_MASK, {O_rD, 0}, - 0, "mfmsr", 0 }, - { X_OPCODE(31,86,0), X_MASK, {O_rA, O_rB, 0}, - 0, "dcbf", H_RA0_IS_0 }, - { X_OPCODE(31,87,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lbzx", H_RA0_IS_0 }, - { XO_OPCODE(31,104,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "neg", 0 }, - { XO_OPCODE(31,104,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "neg.", 0 }, - { X_OPCODE(31,119,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lbzux", 0 }, - { X_OPCODE(31,124,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "nor", 0 }, - { X_OPCODE(31,124,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "nor.", 0 }, - { XO_OPCODE(31,136,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subfe", 0 }, - { XO_OPCODE(31,136,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subfe.", 0 }, - { XO_OPCODE(31,138,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "adde", 0 }, - { XO_OPCODE(31,138,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "adde.", 0 }, - { XFX_OPCODE(31,144,0), XFX_MASK, {O_CRM, O_rS, 0}, - 0, "mtcrf", 0 }, - { X_OPCODE(31,146,0), X_MASK, {O_rS, 0}, - 0, "mtmsr", 0 }, - { X_OPCODE(31,150,1), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "stwcx.", 0 }, - { X_OPCODE(31,151,0), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "stwx", 0 }, - { X_OPCODE(31,183,0), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "stwux", 0 }, - { XO_OPCODE(31,200,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "subfze", 0 }, - { XO_OPCODE(31,200,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "subfze.", 0 }, - { XO_OPCODE(31,202,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "addze", 0 }, - { XO_OPCODE(31,202,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "addze.", 0 }, - { X_OPCODE(31,210,0), X_MASK, {O_SR, O_rS, 0}, - 0, "mtsr", 0 }, - { X_OPCODE(31,215,0), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "stbx", H_RA0_IS_0 }, - { XO_OPCODE(31,232,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "subfme", 0 }, - { XO_OPCODE(31,232,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "subfme.", 0 }, - { XO_OPCODE(31,234,0,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "addme", 0 }, - { XO_OPCODE(31,234,0,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "addme.", 0 }, - { XO_OPCODE(31,235,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "mullw", 0 }, - { XO_OPCODE(31,235,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "mullw.", 0 }, - { X_OPCODE(31,242,0), X_MASK, {O_rS, O_rB, 0}, - 0, "mtsrin", 0 }, - { X_OPCODE(31,246,0), X_MASK, {O_rA, O_rB, 0}, - 0, "dcbtst", H_RA0_IS_0 }, - { X_OPCODE(31,247,0), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "stbux", 0 }, - { XO_OPCODE(31,266,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "add", 0 }, - { XO_OPCODE(31,266,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "add.", 0 }, - { X_OPCODE(31,278,0), X_MASK, {O_rA, O_rB, 0}, - 0, "dcbt", H_RA0_IS_0 }, - { X_OPCODE(31,279,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lhzx", H_RA0_IS_0 }, - { X_OPCODE(31,284,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "eqv", 0 }, - { X_OPCODE(31,284,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "eqv.", 0 }, - { X_OPCODE(31,306,0), X_MASK, {O_rB, 0}, - 0, "tlbie", 0 }, - { X_OPCODE(31,310,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "eciwx", H_RA0_IS_0 }, - { X_OPCODE(31,311,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lhzux", 0 }, - { X_OPCODE(31,316,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "xor", 0 }, - { X_OPCODE(31,316,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "xor.", 0 }, - { XFX_OPCODE(31,339,0), XFX_MASK, {O_rD, O_spr, 0}, - 0, "mfspr", 0 }, - { X_OPCODE(31,343,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lhax", H_RA0_IS_0 }, - { X_OPCODE(31,370,0), X_MASK, {0}, - 0, "tlbia", 0 }, - { XFX_OPCODE(31,371,0), XFX_MASK, {O_rD, O_tbr, 0}, - 0, "mftb", 0 }, - { X_OPCODE(31,375,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lhaux", 0 }, - { X_OPCODE(31,407,0), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "sthx", H_RA0_IS_0 }, - { X_OPCODE(31,412,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "orc", 0 }, - { X_OPCODE(31,412,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "orc.", 0 }, - { X_OPCODE(31,438,0), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "ecowx", H_RA0_IS_0 }, - { X_OPCODE(31,439,0), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "sthux", 0 }, - { X_OPCODE(31,444,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "or", 0 }, - { X_OPCODE(31,444,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "or.", 0 }, - { XO_OPCODE(31,459,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "divwu", 0 }, - { XO_OPCODE(31,459,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "divwu.", 0 }, - { XFX_OPCODE(31,467,0), XFX_MASK, {O_spr, O_rS, 0}, - 0, "mtspr", 0 }, - { X_OPCODE(31,470,0), X_MASK, {O_rA, O_rB, 0}, - 0, "dcbi", H_RA0_IS_0 }, - { X_OPCODE(31,476,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "nand", 0 }, - { X_OPCODE(31,476,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc,0}, - 0, "nand.", 0 }, - { XO_OPCODE(31,491,0,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "divw", 0 }, - { XO_OPCODE(31,491,0,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "divw.", 0 }, - { X_OPCODE(31,512,0), X_MASK, {O_crfD, 0}, - 0, "mcrxr", 0 }, - { XO_OPCODE(31,8,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subfco", 0 }, - { XO_OPCODE(31,8,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subfco.", 0 }, - { XO_OPCODE(31,10,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "addco", 0 }, - { XO_OPCODE(31,10,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "addco.", 0 }, - { X_OPCODE(31,533,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lswx", H_RA0_IS_0 }, - { X_OPCODE(31,534,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lwbrx", H_RA0_IS_0 }, - { X_OPCODE(31,536,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "srw", 0 }, - { X_OPCODE(31,536,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "srw.", 0 }, - { XO_OPCODE(31,40,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subfo", 0 }, - { XO_OPCODE(31,40,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subfo.", 0 }, - { X_OPCODE(31,566,0), X_MASK, {0}, - 0, "tlbsync", 0 }, - { X_OPCODE(31,595,0), X_MASK, {O_rD, O_SR, 0}, - 0, "mfsr", 0 }, - { X_OPCODE(31,597,0), X_MASK, {O_rD, O_rA, O_NB, 0}, - 0, "lswi", H_RA0_IS_0 }, - { X_OPCODE(31,598,0), X_MASK, {0}, - 0, "sync", 0 }, - { XO_OPCODE(31,104,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "nego", 0 }, - { XO_OPCODE(31,104,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "nego.", 0 }, - { XO_OPCODE(31,136,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subfeo", 0 }, - { XO_OPCODE(31,136,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "subfeo.", 0 }, - { XO_OPCODE(31,138,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "addeo", 0 }, - { XO_OPCODE(31,138,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "addeo.", 0 }, - { X_OPCODE(31,659,0), X_MASK, {O_rD, O_rB, 0}, - 0, "mfsrin", 0 }, - { X_OPCODE(31,661,0), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "stswx", H_RA0_IS_0 }, - { X_OPCODE(31,662,0), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "stwbrx", H_RA0_IS_0 }, - { XO_OPCODE(31,200,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "subfzeo", 0 }, - { XO_OPCODE(31,200,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "subfzeo.", 0 }, - { XO_OPCODE(31,202,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "addzeo", 0 }, - { XO_OPCODE(31,202,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "addzeo.", 0 }, - { X_OPCODE(31,725,0), X_MASK, {O_rS, O_rA, O_NB, 0}, - 0, "stswi", H_RA0_IS_0 }, - { XO_OPCODE(31,232,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "subfmeo", 0 }, - { XO_OPCODE(31,232,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "subfmeo.", 0 }, - { XO_OPCODE(31,234,1,0), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "addmeo", 0 }, - { XO_OPCODE(31,234,1,1), XO_MASK, {O_rD, O_rA, O_OE, O_Rc, 0}, - 0, "addmeo.", 0 }, - { XO_OPCODE(31,235,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "mullwo", 0 }, - { XO_OPCODE(31,235,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "mullwo.", 0 }, - { XO_OPCODE(31,266,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "addo", 0 }, - { XO_OPCODE(31,266,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "addo.", 0 }, - { X_OPCODE(31,790,0), X_MASK, {O_rD, O_rA, O_rB, 0}, - 0, "lhbrx", H_RA0_IS_0 }, - { X_OPCODE(31,792,0), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "sraw", 0 }, - { X_OPCODE(31,792,1), X_MASK, {O_rA, O_rS, O_rB, O_Rc, 0}, - 0, "sraw.", 0 }, - { X_OPCODE(31,824,0), X_MASK, {O_rA, O_rS, O_SH, O_Rc, 0}, - 0, "srawi", 0 }, - { X_OPCODE(31,824,1), X_MASK, {O_rA, O_rS, O_SH, O_Rc, 0}, - 0, "srawi.", 0 }, - { X_OPCODE(31,854,0), X_MASK, {0}, - 0, "eieio", 0 }, - { X_OPCODE(31,918,0), X_MASK, {O_rS, O_rA, O_rB, 0}, - 0, "sthbrx", H_RA0_IS_0 }, - { X_OPCODE(31,922,0), X_MASK, {O_rA, O_rS, O_Rc, 0}, - 0, "extsh", 0 }, - { X_OPCODE(31,922,1), X_MASK, {O_rA, O_rS, O_Rc, 0}, - 0, "extsh.", 0 }, - { X_OPCODE(31,954,0), X_MASK, {O_rA, O_rS, O_Rc, 0}, - 0, "extsb", 0 }, - { X_OPCODE(31,954,1), X_MASK, {O_rA, O_rS, O_Rc, 0}, - 0, "extsb.", 0 }, - { XO_OPCODE(31,459,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "divwuo", 0 }, - { XO_OPCODE(31,459,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "divwuo.", 0 }, - { X_OPCODE(31,978,0), X_MASK, {O_rB, 0}, - 0, "tlbld", 0 }, - { X_OPCODE(31,982,0), X_MASK, {O_rA, O_rB, 0}, - 0, "icbi", H_RA0_IS_0 }, - { XO_OPCODE(31,491,1,0), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "divwo", 0 }, - { XO_OPCODE(31,491,1,1), XO_MASK, {O_rD, O_rA, O_rB, O_OE, O_Rc, 0}, - 0, "divwo.", 0 }, - { X_OPCODE(31,1010,0), X_MASK, {O_rB, 0}, - 0, "tlbli", 0 }, - { X_OPCODE(31,1014,0), X_MASK, {O_rA, O_rB, 0}, - 0, "dcbz", H_RA0_IS_0 }, - { D_OPCODE(32), D_MASK, {O_rD, O_d, O_rA, 0}, - 0, "lwz", H_RA0_IS_0 }, - { D_OPCODE(33), D_MASK, {O_rD, O_d, O_rA, 0}, - 0, "lwzu", 0 }, - { D_OPCODE(34), D_MASK, {O_rD, O_d, O_rA, 0}, - 0, "lbz", H_RA0_IS_0 }, - { D_OPCODE(35), D_MASK, {O_rD, O_d, O_rA, 0}, - 0, "lbzu", 0 }, - { D_OPCODE(36), D_MASK, {O_rS, O_d, O_rA, 0}, - 0, "stw", H_RA0_IS_0 }, - { D_OPCODE(37), D_MASK, {O_rS, O_d, O_rA, 0}, - 0, "stwu", 0 }, - { D_OPCODE(38), D_MASK, {O_rS, O_d, O_rA, 0}, - 0, "stb", H_RA0_IS_0 }, - { D_OPCODE(39), D_MASK, {O_rS, O_d, O_rA, 0}, - 0, "stbu", 0 }, - { D_OPCODE(40), D_MASK, {O_rD, O_d, O_rA, 0}, - 0, "lhz", H_RA0_IS_0 }, - { D_OPCODE(41), D_MASK, {O_rD, O_d, O_rA, 0}, - 0, "lhzu", 0 }, - { D_OPCODE(42), D_MASK, {O_rD, O_d, O_rA, 0}, - 0, "lha", H_RA0_IS_0 }, - { D_OPCODE(43), D_MASK, {O_rD, O_d, O_rA, 0}, - 0, "lhau", 0 }, - { D_OPCODE(44), D_MASK, {O_rS, O_d, O_rA, 0}, - 0, "sth", H_RA0_IS_0 }, - { D_OPCODE(45), D_MASK, {O_rS, O_d, O_rA, 0}, - 0, "sthu", 0 }, - { D_OPCODE(46), D_MASK, {O_rD, O_d, O_rA, 0}, - 0, "lmw", H_RA0_IS_0 }, - { D_OPCODE(47), D_MASK, {O_rS, O_d, O_rA, 0}, - 0, "stmw", H_RA0_IS_0 }, -}; - -const unsigned int n_opcodes = sizeof(opcodes) / sizeof(opcodes[0]); - -struct spr_info spr_map[] = { - { SPR_XER, "XER" }, - { SPR_LR, "LR" }, - { SPR_CTR, "CTR" }, - { SPR_DSISR, "DSISR" }, - { SPR_DAR, "DAR" }, - { SPR_DEC, "DEC" }, - { SPR_SRR0, "SRR0" }, - { SPR_SRR1, "SRR1" }, - { SPR_EIE, "EIE" }, - { SPR_EID, "EID" }, - { SPR_CMPA, "CMPA" }, - { SPR_CMPB, "CMPB" }, - { SPR_CMPC, "CMPC" }, - { SPR_CMPD, "CMPD" }, - { SPR_ICR, "ICR" }, - { SPR_DER, "DER" }, - { SPR_COUNTA, "COUNTA" }, - { SPR_COUNTB, "COUNTB" }, - { SPR_CMPE, "CMPE" }, - { SPR_CMPF, "CMPF" }, - { SPR_CMPG, "CMPG" }, - { SPR_CMPH, "CMPH" }, - { SPR_LCTRL1, "LCTRL1" }, - { SPR_LCTRL2, "LCTRL2" }, - { SPR_ICTRL, "ICTRL" }, - { SPR_BAR, "BAR" }, - { SPR_USPRG0, "USPRG0" }, - { SPR_SPRG4_RO, "SPRG4_RO" }, - { SPR_SPRG5_RO, "SPRG5_RO" }, - { SPR_SPRG6_RO, "SPRG6_RO" }, - { SPR_SPRG7_RO, "SPRG7_RO" }, - { SPR_SPRG0, "SPRG0" }, - { SPR_SPRG1, "SPRG1" }, - { SPR_SPRG2, "SPRG2" }, - { SPR_SPRG3, "SPRG3" }, - { SPR_SPRG4, "SPRG4" }, - { SPR_SPRG5, "SPRG5" }, - { SPR_SPRG6, "SPRG6" }, - { SPR_SPRG7, "SPRG7" }, - { SPR_EAR, "EAR" }, - { SPR_TBL, "TBL" }, - { SPR_TBU, "TBU" }, - { SPR_IC_CST, "IC_CST" }, - { SPR_IC_ADR, "IC_ADR" }, - { SPR_IC_DAT, "IC_DAT" }, - { SPR_DC_CST, "DC_CST" }, - { SPR_DC_ADR, "DC_ADR" }, - { SPR_DC_DAT, "DC_DAT" }, - { SPR_DPDR, "DPDR" }, - { SPR_IMMR, "IMMR" }, - { SPR_MI_CTR, "MI_CTR" }, - { SPR_MI_AP, "MI_AP" }, - { SPR_MI_EPN, "MI_EPN" }, - { SPR_MI_TWC, "MI_TWC" }, - { SPR_MI_RPN, "MI_RPN" }, - { SPR_MD_CTR, "MD_CTR" }, - { SPR_M_CASID, "M_CASID" }, - { SPR_MD_AP, "MD_AP" }, - { SPR_MD_EPN, "MD_EPN" }, - { SPR_M_TWB, "M_TWB" }, - { SPR_MD_TWC, "MD_TWC" }, - { SPR_MD_RPN, "MD_RPN" }, - { SPR_M_TW, "M_TW" }, - { SPR_MI_DBCAM, "MI_DBCAM" }, - { SPR_MI_DBRAM0, "MI_DBRAM0" }, - { SPR_MI_DBRAM1, "MI_DBRAM1" }, - { SPR_MD_DBCAM, "MD_DBCAM" }, - { SPR_MD_DBRAM0, "MD_DBRAM0" }, - { SPR_MD_DBRAM1, "MD_DBRAM1" }, - { SPR_ZPR, "ZPR" }, - { SPR_PID, "PID" }, - { SPR_CCR0, "CCR0" }, - { SPR_IAC3, "IAC3" }, - { SPR_IAC4, "IAC4" }, - { SPR_DVC1, "DVC1" }, - { SPR_DVC2, "DVC2" }, - { SPR_SGR, "SGR" }, - { SPR_DCWR, "DCWR" }, - { SPR_SLER, "SLER" }, - { SPR_SU0R, "SU0R" }, - { SPR_DBCR1, "DBCR1" }, - { SPR_ICDBDR, "ICDBDR" }, - { SPR_ESR, "ESR" }, - { SPR_DEAR, "DEAR" }, - { SPR_EVPR, "EVPR" }, - { SPR_TSR, "TSR" }, - { SPR_TCR, "TCR" }, - { SPR_PIT, "PIT" }, - { SPR_SRR2, "SRR2" }, - { SPR_SRR3, "SRR3" }, - { SPR_DBSR, "DBSR" }, - { SPR_DBCR0, "DBCR0" }, - { SPR_IAC1, "IAC1" }, - { SPR_IAC2, "IAC2" }, - { SPR_DAC1, "DAC1" }, - { SPR_DAC2, "DAC2" }, - { SPR_DCCR, "DCCR" }, - { SPR_ICCR, "ICCR" }, -}; - -const unsigned int n_sprs = sizeof(spr_map) / sizeof(spr_map[0]); - -#endif - -/* - * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks - * All rights reserved. - * - * Redistribution and use in source and binary forms are freely - * permitted provided that the above copyright notice and this - * paragraph and the following disclaimer are duplicated in all - * such forms. - * - * This software is provided "AS IS" and without any express or - * implied warranties, including, without limitation, the implied - * warranties of merchantability and fitness for a particular - * purpose. - */ diff --git a/include/bedbug/type.h b/include/bedbug/type.h deleted file mode 100644 index f7a719caf0a..00000000000 --- a/include/bedbug/type.h +++ /dev/null @@ -1,29 +0,0 @@ -#ifndef _TYPE_BEDBUG_H -#define _TYPE_BEDBUG_H - -struct cmd_tbl; - -/* Supporting routines */ -int bedbug_puts (const char *); -int bedbug_init(void); -void bedbug860_init (void); -void do_bedbug_breakpoint (struct pt_regs *); -void bedbug_main_loop (unsigned long, struct pt_regs *); - - -typedef struct { - int hw_debug_enabled; - int stopped; - int current_bp; - struct pt_regs *regs; - - void (*do_break)(struct cmd_tbl *cmd, int flags, int argc, - char *const argv[]); - void (*break_isr) (struct pt_regs *); - int (*find_empty) (void); - int (*set) (int, unsigned long); - int (*clear) (int); -} CPU_DEBUG_CTX; - - -#endif /* _TYPE_BEDBUG_H */ diff --git a/post/lib_powerpc/string.c b/post/lib_powerpc/string.c index fc460ceb9f0..0d8d280b271 100644 --- a/post/lib_powerpc/string.c +++ b/post/lib_powerpc/string.c @@ -26,7 +26,6 @@ extern void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); extern void cpu_post_exec_04 (ulong *code, ulong op1, ulong op2, ulong op3, ulong op4); -#include <bedbug/regs.h> int cpu_post_test_string (void) { int ret = 0; |