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-rw-r--r--arch/arm/dts/Makefile1
-rw-r--r--arch/arm/dts/zynqmp-a2197-m-revA.dts461
l---------board/xilinx/zynqmp/zynqmp-a2197-m-revA1
-rw-r--r--configs/xilinx_zynqmp_a2197_m_revA_defconfig116
-rw-r--r--configs/xilinx_zynqmp_a2197_revA_defconfig2
5 files changed, 580 insertions, 1 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index dd1060acd68..2d95a99d264 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -249,6 +249,7 @@ dtb-$(CONFIG_ARCH_ZYNQMP) += \
avnet-ultrazedev-cc-v1.0-ultrazedev-som-v1.0.dtb \
zynqmp-a2197-revA.dtb \
zynqmp-a2197-g-revA.dtb \
+ zynqmp-a2197-m-revA.dtb \
zynqmp-a2197-p-revA.dtb \
zynqmp-mini.dtb \
zynqmp-mini-emmc0.dtb \
diff --git a/arch/arm/dts/zynqmp-a2197-m-revA.dts b/arch/arm/dts/zynqmp-a2197-m-revA.dts
new file mode 100644
index 00000000000..e4b45eafe42
--- /dev/null
+++ b/arch/arm/dts/zynqmp-a2197-m-revA.dts
@@ -0,0 +1,461 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * dts file for Xilinx Versal a2197 RevA System Controller
+ *
+ * (C) Copyright 2019, Xilinx, Inc.
+ *
+ * Michal Simek <michal.simek@xilinx.com>
+ */
+/dts-v1/;
+
+#include "zynqmp.dtsi"
+#include "zynqmp-clk-ccf.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+ model = "Versal System Controller on a2197 Memory Char board RevA";
+ compatible = "xlnx,zynqmp-a2197-m-revA", "xlnx,zynqmp-a2197-revA",
+ "xlnx,zynqmp-a2197", "xlnx,zynqmp";
+
+ aliases {
+ ethernet0 = &gem0;
+ gpio0 = &gpio;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ mmc0 = &sdhci0;
+ mmc1 = &sdhci1;
+ rtc0 = &rtc;
+ serial0 = &uart0;
+ serial1 = &uart1;
+ serial2 = &dcc;
+ usb0 = &usb0;
+ usb1 = &usb1;
+ spi0 = &qspi;
+ };
+
+ chosen {
+ bootargs = "earlycon";
+ stdout-path = "serial0:115200n8";
+ xlnx,eeprom = <&eeprom>;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>; /* FIXME don't know how big memory is there */
+ };
+};
+
+&qspi {
+ status = "okay";
+ is-dual = <1>;
+ flash@0 {
+ compatible = "m25p80", "spi-flash"; /* 32MB */
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x0>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <108000000>;
+ };
+};
+
+&sdhci0 { /* emmc MIO 13-23 - with some settings 16GB */
+ status = "okay";
+ non-removable;
+ disable-wp;
+ bus-width = <8>;
+ xlnx,mio_bank = <0>; /* FIXME tap delay */
+};
+
+&uart0 { /* uart0 MIO38-39 */
+ status = "okay";
+ u-boot,dm-pre-reloc;
+};
+
+&uart1 { /* uart1 MIO40-41 */
+ status = "okay";
+ u-boot,dm-pre-reloc;
+};
+
+&sdhci1 { /* sd1 MIO45-51 cd in place */
+ status = "disable";
+ no-1-8-v;
+ disable-wp;
+ xlnx,mio_bank = <1>;
+};
+
+&gem0 {
+ status = "okay";
+ phy-handle = <&phy0>;
+ phy-mode = "sgmii"; /* DTG generates this properly 1512 */
+ phy-reset-gpios = <&gpio 142 GPIO_ACTIVE_LOW>;
+ phy0: phy@0 { /* marwell m88e1512 - SGMII */
+ reg = <0>;
+/* xlnx,phy-type = <PHY_TYPE_SGMII>; */
+ };
+/* phy-names = "...";
+ phys = <&lane0 PHY_TYPE_SGMII ... >
+ Note: lane0 sgmii/lane1 usb3 */
+};
+
+&gpio {
+ status = "okay";
+ gpio-line-names = "SCLK_OUT", "MISO_MO1", "MO2", "MO3", "MOSI_MIO0", /* 0 - 4 */
+ "N_SS_OUT", "", "SYS_CTRL0", "SYS_CTRL1", "SYS_CTRL2", /* 5 - 9 */
+ "SYS_CTRL3", "SYS_CTRL4", "SYS_CTRL5", "EMMC_DAT0", "EMMC_DAT1", /* 10 - 14 */
+ "EMMC_DAT2", "EMMC_DAT3", "EMMC_DAT4", "EMMC_DAT5", "EMMC_DAT6", /* 15 - 19 */
+ "EMMC_DAT7", "EMMC_CMD", "EMMC_CLK", "EMMC_RST_B", "", /* 20 - 24 */
+ "", "RXD0_IN", "TXD0_OUT", "TXD1_OUT", "RXD1_IN", /* 25 - 29 */
+ "", "", "", "", "LP_I2C0_PMC_SCL", /* 30 - 34 */
+ "LP_I2C0_PMC_SDA", "LP_I2C1_SCL", "LP_I2C1_SDA", "UART0_RXD_IN", "UART0_TXD_OUT", /* 35 - 39 */
+ "UART1_TXD_OUT", "UART1_RXD_IN", "ETH_RESET_B", "", "", /* 40 - 44 */
+ "SD1_CD_B", "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3", /* 45 - 49 */
+ "SD1_CMD", "SD1_CLK", "USB0_CLK", "USB0_DIR", "USB0_DATA2", /* 50 - 54 */
+ "USB0_NXT", "USB0_DATA0", "USB0_DATA1", "USB0_STP", "USB0_DATA3", /* 55 - 59 */
+ "USB0_DATA4", "USB0_DATA5", "USB0_DATA6", "USB0_DATA7", "USB1_CLK", /* 60 - 64 */
+ "USB1_DIR", "USB1_DATA2", "USB1_NXT", "USB1_DATA0", "USB1_DATA1", /* 65 - 69 */
+ "USB1_STP", "USB1_DATA3", "USB1_DATA4", "USB1_DATA5", "USB1_DATA6", /* 70 - 74 */
+ "USB1_DATA7", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
+ "", "", "", "", "", /* 78 - 79 */
+ "", "", "", "", "", /* 80 - 84 */
+ "", "", "", "", "", /* 85 -89 */
+ "", "", "", "", "", /* 90 - 94 */
+ "", "", "", "", "", /* 95 - 99 */
+ "", "", "", "", "", /* 100 - 104 */
+ "", "", "", "", "", /* 105 - 109 */
+ "", "", "", "", "", /* 110 - 114 */
+ "", "", "", "", "", /* 115 - 119 */
+ "", "", "", "", "", /* 120 - 124 */
+ "", "", "", "", "", /* 125 - 129 */
+ "", "", "", "", "", /* 130 - 134 */
+ "", "", "", "", "", /* 135 - 139 */
+ "", "", "", "", "", /* 140 - 144 */
+ "", "", "", "", "", /* 145 - 149 */
+ "", "", "", "", "", /* 150 - 154 */
+ "", "", "", "", "", /* 155 - 159 */
+ "", "", "", "", "", /* 160 - 164 */
+ "", "", "", "", "", /* 165 - 169 */
+ "", "", "", ""; /* 170 - 174 */
+};
+
+&i2c0 { /* MIO 34-35 - can't stay here */
+ status = "okay";
+ clock-frequency = <400000>;
+ i2c-mux@74 { /* u46 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* FIXME reset connected to SYSCTRL_IIC_MUX0_RESET */
+ i2c@0 { /* PMBUS must be enabled via SW21 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ reg_vcc1v2_lp4: tps544@15 { /* u97 */
+ compatible = "ti,tps544b25";
+ reg = <0x15>;
+ };
+ reg_vcc1v1_lp4: tps544@16 { /* u95 */
+ compatible = "ti,tps544b25";
+ reg = <0x16>;
+ };
+ reg_vdd1_1v8_lp4: tps544@17 { /* u99 */
+ compatible = "ti,tps544b25";
+ reg = <0x17>;
+ };
+ /* UTIL_PMBUS connection */
+ reg_vcc1v8: tps544@13 { /* u92 */
+ compatible = "ti,tps544b25";
+ reg = <0x13>;
+ };
+ reg_vcc3v3: tps544@14 { /* u93 */
+ compatible = "ti,tps544b25";
+ reg = <0x14>;
+ };
+ reg_vcc5v0: tps544@1e { /* u94 */
+ compatible = "ti,tps544b25";
+ reg = <0x1e>;
+ };
+ };
+ i2c@1 { /* PMBUS_INA226 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+ vcc_aux: ina226@42 { /* u86 */
+ compatible = "ti,ina226";
+ reg = <0x42>;
+ shunt-resistor = <5000>;
+ };
+ vcc_ram: ina226@43 { /* u81 */
+ compatible = "ti,ina226";
+ reg = <0x43>;
+ shunt-resistor = <5000>;
+ };
+ vcc1v1_lp4: ina226@46 { /* u96 */
+ compatible = "ti,ina226";
+ reg = <0x46>;
+ shunt-resistor = <5000>;
+ };
+ vcc1v2_lp4: ina226@47 { /* u98 */
+ compatible = "ti,ina226";
+ reg = <0x47>;
+ shunt-resistor = <5000>;
+ };
+ vdd1_1v8_lp4: ina226@48 { /* u100 */
+ compatible = "ti,ina226";
+ reg = <0x48>;
+ shunt-resistor = <5000>;
+ };
+ vcc0v6_lp4: ina226@49 { /* u101 */
+ compatible = "ti,ina226";
+ reg = <0x49>;
+ shunt-resistor = <5000>;
+ };
+ };
+ i2c@2 { /* PMBUS1 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ reg_vccint: tps53681@c0 { /* u69 */
+ compatible = "ti,tps53681"; /* FIXME no linux driver */
+ reg = <0xc0>;
+ };
+ reg_vcc_pmc: tps544@7 { /* u80 */
+ compatible = "ti,tps544b25";
+ reg = <0x7>;
+ };
+ reg_vcc_ram: tps544@8 { /* u82 */
+ compatible = "ti,tps544b25";
+ reg = <0x8>;
+ };
+ reg_vcc_pslp: tps544@9 { /* u83 */
+ compatible = "ti,tps544b25";
+ reg = <0x9>;
+ };
+ reg_vcc_psfp: tps544@a { /* u84 */
+ compatible = "ti,tps544b25";
+ reg = <0xa>;
+ };
+ reg_vccaux: tps544@d { /* u85 */
+ compatible = "ti,tps544b25";
+ reg = <0xd>;
+ };
+ reg_vccaux_pmc: tps544@e { /* u87 */
+ compatible = "ti,tps544b25";
+ reg = <0xe>;
+ };
+ reg_vcco_500: tps544@f { /* u88 */
+ compatible = "ti,tps544b25";
+ reg = <0xf>;
+ };
+ reg_vcco_501: tps544@10 { /* u89 */
+ compatible = "ti,tps544b25";
+ reg = <0x10>;
+ };
+ reg_vcco_502: tps544@11 { /* u90 */
+ compatible = "ti,tps544b25";
+ reg = <0x11>;
+ };
+ reg_vcco_503: tps544@12 { /* u91 */
+ compatible = "ti,tps544b25";
+ reg = <0x12>;
+ };
+ };
+ i2c@3 { /* MEM PMBUS - FIXME bug in schematics */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* reg = <3>; */
+ };
+ i2c@4 { /* LP_I2C_SM */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ /* connected to U20G */
+ };
+ /* 5-7 unused */
+ };
+};
+
+/* TODO sysctrl via J239 */
+/* TODO samtec J212G/H via J242 */
+/* TODO teensy via U30 PCA9543A bus 1 */
+&i2c1 { /* i2c1 MIO 36-37 */
+ status = "okay";
+ clock-frequency = <400000>;
+
+ /* Must be enabled via J242 */
+ eeprom_versal: eeprom@51 { /* x-prc-01-revA u116, x-prc-02-revA u12 */
+ compatible = "atmel,24c02";
+ reg = <0x51>;
+ };
+
+ i2c-mux@74 { /* u35 */
+ compatible = "nxp,pca9548";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x74>;
+ /* FIXME reset connected to SYSCTRL_IIC_MUX1_RESET */
+ dc_i2c: i2c@0 { /* DC_I2C */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0>;
+ /* Use for storing information about SC board */
+ eeprom: eeprom@54 { /* u51 - m24128 16kB FIXME addr */
+ compatible = "atmel,24c08";
+ reg = <0x54>;
+ };
+ si570_ref_clk: clock-generator@5d { /* u26 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>; /* FIXME addr */
+ temperature-stability = <50>;
+ factory-fout = <156250000>; /* FIXME every chip can be different */
+ clock-frequency = <33333333>;
+ clock-output-names = "REF_CLK"; /* FIXME */
+ };
+ /* Connection via Samtec U20D */
+ /* Use for storing information about X-PRC card */
+ x_prc_eeprom: eeprom@52 { /* x-prc-01-revA u120, x-prc-02-revA u16 */
+ compatible = "atmel,24c02";
+ reg = <0x52>;
+ };
+
+ /* Use for setting up certain features on X-PRC card */
+ x_prc_tca9534: gpio@22 { /* x-prc-01-revA u121, x-prc-02-revA u17 */
+ compatible = "nxp,pca9534";
+ reg = <0x22>;
+ gpio-controller; /* IRQ not connected */
+ #gpio-cells = <2>;
+ gpio-line-names = "sw4_1", "sw4_2", "sw4_3", "sw4_4",
+ "", "", "", "";
+ gtr_sel0 {
+ gpio-hog;
+ gpios = <0 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_1";
+ };
+ gtr_sel1 {
+ gpio-hog;
+ gpios = <1 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_2";
+ };
+ gtr_sel2 {
+ gpio-hog;
+ gpios = <2 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_3";
+ };
+ gtr_sel3 {
+ gpio-hog;
+ gpios = <3 0>;
+ input; /* FIXME add meaning */
+ line-name = "sw4_4";
+ };
+ };
+ };
+ i2c@1 { /* UTIL_PMBUS - FIXME incorrect schematics */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ /* reg = <1>; */
+ };
+ i2c@2 { /* C0_LP4 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <2>;
+ si570_c0_lp4: clock-generator@5d { /* u10 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>; /* FIXME addr */
+ temperature-stability = <50>;
+ factory-fout = <30000000>;
+ clock-frequency = <30000000>;
+ clock-output-names = "C0_LP4_SI570_CLK";
+ };
+ };
+ i2c@3 { /* C1_LP4 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <3>;
+ si570_c1_lp4: clock-generator@5d { /* u10 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>; /* FIXME addr */
+ temperature-stability = <50>;
+ factory-fout = <30000000>;
+ clock-frequency = <30000000>;
+ clock-output-names = "C1_LP4_SI570_CLK";
+ };
+ };
+ i2c@4 { /* C2_LP4 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <4>;
+ si570_c2_lp4: clock-generator@5d { /* u10 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>; /* FIXME addr */
+ temperature-stability = <50>;
+ factory-fout = <30000000>;
+ clock-frequency = <30000000>;
+ clock-output-names = "C2_LP4_SI570_CLK";
+ };
+ };
+ i2c@5 { /* C3_LP4 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <5>;
+ si570_c3_lp4: clock-generator@5d { /* u15 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>; /* FIXME addr */
+ temperature-stability = <50>;
+ factory-fout = <30000000>;
+ clock-frequency = <30000000>;
+ clock-output-names = "C3_LP4_SI570_CLK";
+ };
+ };
+ i2c@6 { /* HSDP_SI570 */
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <6>;
+ si570_hsdp: clock-generator@5d { /* u19 */
+ #clock-cells = <0>;
+ compatible = "silabs,si570";
+ reg = <0x5d>; /* FIXME addr */
+ temperature-stability = <50>;
+ factory-fout = <156250000>; /* FIXME every chip can be different - 10MHZ_TO_810MHZ */
+ clock-frequency = <33333333>;
+ clock-output-names = "HSDP_SI570";
+ };
+ };
+ };
+};
+
+&usb0 {
+ status = "okay";
+ xlnx,usb-polarity = <0>;
+ xlnx,usb-reset-mode = <0>;
+};
+
+&dwc3_0 {
+ status = "okay";
+ dr_mode = "host";
+ /* dr_mode = "peripheral"; */
+ maximum-speed = "high-speed";
+};
+
+&usb1 {
+ status = "disabled"; /* not at mem board */
+ xlnx,usb-polarity = <0>;
+ xlnx,usb-reset-mode = <0>;
+};
+
+&dwc3_1 {
+ /delete-property/ phy-names ;
+ /delete-property/ phys ;
+ maximum-speed = "high-speed";
+ snps,dis_u2_susphy_quirk ;
+ snps,dis_u3_susphy_quirk ;
+ status = "disabled";
+};
diff --git a/board/xilinx/zynqmp/zynqmp-a2197-m-revA b/board/xilinx/zynqmp/zynqmp-a2197-m-revA
new file mode 120000
index 00000000000..a64c140b860
--- /dev/null
+++ b/board/xilinx/zynqmp/zynqmp-a2197-m-revA
@@ -0,0 +1 @@
+zynqmp-a2197-revA \ No newline at end of file
diff --git a/configs/xilinx_zynqmp_a2197_m_revA_defconfig b/configs/xilinx_zynqmp_a2197_m_revA_defconfig
new file mode 100644
index 00000000000..d9107d6bb86
--- /dev/null
+++ b/configs/xilinx_zynqmp_a2197_m_revA_defconfig
@@ -0,0 +1,116 @@
+CONFIG_ARM=y
+CONFIG_ARCH_ZYNQMP=y
+CONFIG_SYS_TEXT_BASE=0x8000000
+CONFIG_SYS_MALLOC_F_LEN=0x8000
+CONFIG_SPL=y
+CONFIG_DEBUG_UART_BASE=0xff000000
+CONFIG_DEBUG_UART_CLOCK=100000000
+CONFIG_IDENT_STRING=" Xilinx ZynqMP SC for Versal"
+CONFIG_SPL_SPI_FLASH_SUPPORT=y
+CONFIG_SPL_SPI_SUPPORT=y
+CONFIG_ZYNQMP_USB=y
+CONFIG_DEBUG_UART=y
+CONFIG_AHCI=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_SPL_LOAD_FIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_BOARD_EARLY_INIT_R=y
+CONFIG_SPL_OS_BOOT=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
+CONFIG_SPL_ATF=y
+CONFIG_SYS_PROMPT="ZynqMP> "
+CONFIG_CMD_THOR_DOWNLOAD=y
+CONFIG_CMD_MEMTEST=y
+CONFIG_SYS_ALT_MEMTEST=y
+CONFIG_CMD_CLK=y
+CONFIG_CMD_DFU=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_FPGA_LOADBP=y
+CONFIG_CMD_FPGA_LOADP=y
+CONFIG_CMD_FPGA_LOAD_SECURE=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SDRAM=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_TFTPPUT=y
+CONFIG_CMD_TIME=y
+CONFIG_CMD_TIMER=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_SPL_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="zynqmp-a2197-m-revA"
+CONFIG_ENV_IS_IN_FAT=y
+CONFIG_NET_RANDOM_ETHADDR=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SCSI_AHCI=y
+CONFIG_SATA_CEVA=y
+CONFIG_CLK_ZYNQMP=y
+CONFIG_DFU_RAM=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=0
+CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
+CONFIG_FPGA_XILINX=y
+CONFIG_FPGA_ZYNQMPPL=y
+CONFIG_DM_GPIO=y
+CONFIG_XILINX_GPIO=y
+CONFIG_DM_PCA953X=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_CADENCE=y
+CONFIG_I2C_MUX=y
+CONFIG_I2C_MUX_PCA954x=y
+CONFIG_LED=y
+CONFIG_LED_GPIO=y
+CONFIG_MISC=y
+CONFIG_I2C_EEPROM=y
+CONFIG_SYS_I2C_EEPROM_ADDR=0x0
+CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0x0
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ZYNQ=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_BAR=y
+CONFIG_SF_DUAL_FLASH=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+# CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
+CONFIG_PHY_MARVELL=y
+CONFIG_PHY_NATSEMI=y
+CONFIG_PHY_REALTEK=y
+CONFIG_PHY_TI=y
+CONFIG_PHY_VITESSE=y
+CONFIG_PHY_FIXED=y
+CONFIG_PHY_GIGE=y
+CONFIG_MII=y
+CONFIG_ZYNQ_GEM=y
+CONFIG_SCSI=y
+CONFIG_DM_SCSI=y
+CONFIG_DEBUG_UART_ZYNQ=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_ZYNQ_SERIAL=y
+CONFIG_SPI=y
+CONFIG_ZYNQMP_GQSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_ZYNQMP=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_GADGET=y
+CONFIG_USB_DWC3_GENERIC=y
+CONFIG_USB_ULPI_VIEWPORT=y
+CONFIG_USB_ULPI=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Xilinx"
+CONFIG_USB_GADGET_VENDOR_NUM=0x03FD
+CONFIG_USB_GADGET_PRODUCT_NUM=0x0300
+CONFIG_USB_FUNCTION_THOR=y
+CONFIG_SPL_GZIP=y
+CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
diff --git a/configs/xilinx_zynqmp_a2197_revA_defconfig b/configs/xilinx_zynqmp_a2197_revA_defconfig
index 2859ef553e3..ace01142324 100644
--- a/configs/xilinx_zynqmp_a2197_revA_defconfig
+++ b/configs/xilinx_zynqmp_a2197_revA_defconfig
@@ -44,7 +44,7 @@ CONFIG_CMD_TIMER=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_DEFAULT_DEVICE_TREE="zynqmp-a2197-revA"
-CONFIG_OF_LIST="zynqmp-a2197-revA zynqmp-a2197-g-revA zynqmp-a2197-p-revA"
+CONFIG_OF_LIST="zynqmp-a2197-revA zynqmp-a2197-g-revA zynqmp-a2197-p-revA zynqmp-a2197-m-revA"
CONFIG_ENV_IS_IN_FAT=y
CONFIG_NET_RANDOM_ETHADDR=y
CONFIG_SPL_DM=y
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-10 23:46:04 +0000