diff options
| -rw-r--r-- | drivers/ddr/marvell/axp/ddr3_axp.h | 3 | ||||
| -rw-r--r-- | drivers/ddr/marvell/axp/ddr3_axp_config.h | 5 | ||||
| -rw-r--r-- | include/configs/db-mv784mp-gp.h | 1 | ||||
| -rw-r--r-- | include/configs/maxbcm.h | 1 |
4 files changed, 10 insertions, 0 deletions
diff --git a/drivers/ddr/marvell/axp/ddr3_axp.h b/drivers/ddr/marvell/axp/ddr3_axp.h index d9e33f7c6e2..75d315a35e0 100644 --- a/drivers/ddr/marvell/axp/ddr3_axp.h +++ b/drivers/ddr/marvell/axp/ddr3_axp.h @@ -33,7 +33,10 @@ #define SAR1_CPU_CORE_MASK 0x00000018 #define SAR1_CPU_CORE_OFFSET 3 +/* Only enable ECC if the board selects it */ +#ifdef CONFIG_BOARD_ECC_SUPPORT #define ECC_SUPPORT +#endif #define NEW_FABRIC_TWSI_ADDR 0x4E #ifdef CONFIG_DB_784MP_GP #define BUS_WIDTH_ECC_TWSI_ADDR 0x4E diff --git a/drivers/ddr/marvell/axp/ddr3_axp_config.h b/drivers/ddr/marvell/axp/ddr3_axp_config.h index a6720442ffa..25c34fb0115 100644 --- a/drivers/ddr/marvell/axp/ddr3_axp_config.h +++ b/drivers/ddr/marvell/axp/ddr3_axp_config.h @@ -44,7 +44,12 @@ * DDR3_TRAINING_DEBUG - Debug prints of internal code */ #define DDR_TARGET_FABRIC 5 +/* Only enable ECC if the board selects it */ +#ifdef CONFIG_BOARD_ECC_SUPPORT #define DRAM_ECC 1 +#else +#define DRAM_ECC 0 +#endif #ifdef MV_DDR_32BIT #define BUS_WIDTH 32 diff --git a/include/configs/db-mv784mp-gp.h b/include/configs/db-mv784mp-gp.h index e988f020ab6..c354e6f0d82 100644 --- a/include/configs/db-mv784mp-gp.h +++ b/include/configs/db-mv784mp-gp.h @@ -146,5 +146,6 @@ /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ #define CONFIG_SYS_MVEBU_DDR_AXP #define CONFIG_SPD_EEPROM 0x4e +#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ #endif /* _CONFIG_DB_MV7846MP_GP_H */ diff --git a/include/configs/maxbcm.h b/include/configs/maxbcm.h index 49e83c0fc63..23e552646dc 100644 --- a/include/configs/maxbcm.h +++ b/include/configs/maxbcm.h @@ -108,5 +108,6 @@ /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ #define CONFIG_SYS_MVEBU_DDR_AXP #define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */ +#define CONFIG_BOARD_ECC_SUPPORT /* this board supports ECC */ #endif /* _CONFIG_DB_MV7846MP_GP_H */ |