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-rw-r--r--arch/powerpc/cpu/mpc8xxx/law.c20
-rw-r--r--arch/powerpc/cpu/mpc8xxx/srio.c72
-rw-r--r--board/freescale/common/p_corenet/tlb.c8
-rw-r--r--board/freescale/t208xqds/tlb.c8
-rw-r--r--board/freescale/t208xrdb/tlb.c8
-rw-r--r--include/configs/MPC8548CDS.h8
-rw-r--r--include/configs/P2041RDB.h46
-rw-r--r--include/configs/T102xRDB.h38
-rw-r--r--include/configs/T208xQDS.h42
-rw-r--r--include/configs/T208xRDB.h42
10 files changed, 146 insertions, 146 deletions
diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c
index dd274166c01..35409dc8824 100644
--- a/arch/powerpc/cpu/mpc8xxx/law.c
+++ b/arch/powerpc/cpu/mpc8xxx/law.c
@@ -309,42 +309,42 @@ void init_laws(void)
*/
switch ((bootloc & FSL_CORENET_RCWSR6_BOOT_LOC) >> 23) {
case 0x0: /* boot from PCIE1 */
- set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+ set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
LAW_SIZE_1M,
LAW_TRGT_IF_PCIE_1);
- set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+ set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
LAW_SIZE_1M,
LAW_TRGT_IF_PCIE_1);
break;
case 0x1: /* boot from PCIE2 */
- set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+ set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
LAW_SIZE_1M,
LAW_TRGT_IF_PCIE_2);
- set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+ set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
LAW_SIZE_1M,
LAW_TRGT_IF_PCIE_2);
break;
case 0x2: /* boot from PCIE3 */
- set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+ set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
LAW_SIZE_1M,
LAW_TRGT_IF_PCIE_3);
- set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+ set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
LAW_SIZE_1M,
LAW_TRGT_IF_PCIE_3);
break;
case 0x8: /* boot from SRIO1 */
- set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+ set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
LAW_SIZE_1M,
LAW_TRGT_IF_RIO_1);
- set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+ set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
LAW_SIZE_1M,
LAW_TRGT_IF_RIO_1);
break;
case 0x9: /* boot from SRIO2 */
- set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+ set_next_law(CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
LAW_SIZE_1M,
LAW_TRGT_IF_RIO_2);
- set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+ set_next_law(CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
LAW_SIZE_1M,
LAW_TRGT_IF_RIO_2);
break;
diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c
index c815d19384b..dc1bc0db423 100644
--- a/arch/powerpc/cpu/mpc8xxx/srio.c
+++ b/arch/powerpc/cpu/mpc8xxx/srio.c
@@ -240,8 +240,8 @@ void srio_init(void)
devdisr = &gur->devdisr;
#endif
if (is_serdes_configured(SRIO1)) {
- set_next_law(CONFIG_SYS_SRIO1_MEM_PHYS,
- law_size_bits(CONFIG_SYS_SRIO1_MEM_SIZE),
+ set_next_law(CFG_SYS_SRIO1_MEM_PHYS,
+ law_size_bits(CFG_SYS_SRIO1_MEM_SIZE),
LAW_TRGT_IF_RIO_1);
srio1_used = 1;
#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
@@ -256,8 +256,8 @@ void srio_init(void)
#ifdef CONFIG_SRIO2
if (is_serdes_configured(SRIO2)) {
- set_next_law(CONFIG_SYS_SRIO2_MEM_PHYS,
- law_size_bits(CONFIG_SYS_SRIO2_MEM_SIZE),
+ set_next_law(CFG_SYS_SRIO2_MEM_PHYS,
+ law_size_bits(CFG_SYS_SRIO2_MEM_SIZE),
LAW_TRGT_IF_RIO_2);
srio2_used = 1;
#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
@@ -301,44 +301,44 @@ void srio_boot_master(int port)
/* configure inbound window for slave's u-boot image */
debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
- (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
- (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
- CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
+ (u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
+ (u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1,
+ CFG_SRIO_PCIE_BOOT_IMAGE_SIZE);
out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwtar,
- CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
+ CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwbar,
- CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 >> 12);
+ CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 >> 12);
out_be32((void *)&srio->atmu.port[port - 1].inbw[0].riwar,
SRIO_IB_ATMU_AR
- | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE));
+ | atmu_size_mask(CFG_SRIO_PCIE_BOOT_IMAGE_SIZE));
/* configure inbound window for slave's u-boot image */
debug("SRIOBOOT - MASTER: Inbound window for slave's image; "
"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
- (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
- (u64)CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
- CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE);
+ (u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS,
+ (u64)CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2,
+ CFG_SRIO_PCIE_BOOT_IMAGE_SIZE);
out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwtar,
- CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
+ CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS >> 12);
out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwbar,
- CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 >> 12);
+ CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 >> 12);
out_be32((void *)&srio->atmu.port[port - 1].inbw[1].riwar,
SRIO_IB_ATMU_AR
- | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE));
+ | atmu_size_mask(CFG_SRIO_PCIE_BOOT_IMAGE_SIZE));
/* configure inbound window for slave's ucode and ENV */
debug("SRIOBOOT - MASTER: Inbound window for slave's ucode and ENV; "
"Local = 0x%llx, Srio = 0x%llx, Size = 0x%x\n",
- (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
- (u64)CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
- CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
+ (u64)CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS,
+ (u64)CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS,
+ CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE);
out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwtar,
- CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS >> 12);
+ CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS >> 12);
out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwbar,
- CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS >> 12);
+ CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS >> 12);
out_be32((void *)&srio->atmu.port[port - 1].inbw[2].riwar,
SRIO_IB_ATMU_AR
- | atmu_size_mask(CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE));
+ | atmu_size_mask(CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE));
}
void srio_boot_master_release_slave(int port)
@@ -368,11 +368,11 @@ void srio_boot_master_release_slave(int port)
if (port - 1)
out_be32((void *)&srio->atmu.port[port - 1]
.outbw[1].rowbar,
- CONFIG_SYS_SRIO2_MEM_PHYS >> 12);
+ CFG_SYS_SRIO2_MEM_PHYS >> 12);
else
out_be32((void *)&srio->atmu.port[port - 1]
.outbw[1].rowbar,
- CONFIG_SYS_SRIO1_MEM_PHYS >> 12);
+ CFG_SYS_SRIO1_MEM_PHYS >> 12);
out_be32((void *)&srio->atmu.port[port - 1]
.outbw[1].rowar,
SRIO_OB_ATMU_AR_MAINT
@@ -390,12 +390,12 @@ void srio_boot_master_release_slave(int port)
if (port - 1)
out_be32((void *)&srio->atmu.port[port - 1]
.outbw[2].rowbar,
- (CONFIG_SYS_SRIO2_MEM_PHYS
+ (CFG_SYS_SRIO2_MEM_PHYS
+ SRIO_MAINT_WIN_SIZE) >> 12);
else
out_be32((void *)&srio->atmu.port[port - 1]
.outbw[2].rowbar,
- (CONFIG_SYS_SRIO1_MEM_PHYS
+ (CFG_SYS_SRIO1_MEM_PHYS
+ SRIO_MAINT_WIN_SIZE) >> 12);
out_be32((void *)&srio->atmu.port[port - 1]
.outbw[2].rowar,
@@ -407,10 +407,10 @@ void srio_boot_master_release_slave(int port)
* by the maint-outbound window
*/
if (port - 1) {
- out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
+ out_be32((void *)CFG_SYS_SRIO2_MEM_VIRT
+ SRIO_LCSBA1CSR_OFFSET,
SRIO_LCSBA1CSR);
- while (in_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
+ while (in_be32((void *)CFG_SYS_SRIO2_MEM_VIRT
+ SRIO_LCSBA1CSR_OFFSET)
!= SRIO_LCSBA1CSR)
;
@@ -418,15 +418,15 @@ void srio_boot_master_release_slave(int port)
* And then set the BRR register
* to release slave core
*/
- out_be32((void *)CONFIG_SYS_SRIO2_MEM_VIRT
+ out_be32((void *)CFG_SYS_SRIO2_MEM_VIRT
+ SRIO_MAINT_WIN_SIZE
- + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET,
- CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
+ + CFG_SRIO_PCIE_BOOT_BRR_OFFSET,
+ CFG_SRIO_PCIE_BOOT_RELEASE_MASK);
} else {
- out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
+ out_be32((void *)CFG_SYS_SRIO1_MEM_VIRT
+ SRIO_LCSBA1CSR_OFFSET,
SRIO_LCSBA1CSR);
- while (in_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
+ while (in_be32((void *)CFG_SYS_SRIO1_MEM_VIRT
+ SRIO_LCSBA1CSR_OFFSET)
!= SRIO_LCSBA1CSR)
;
@@ -434,10 +434,10 @@ void srio_boot_master_release_slave(int port)
* And then set the BRR register
* to release slave core
*/
- out_be32((void *)CONFIG_SYS_SRIO1_MEM_VIRT
+ out_be32((void *)CFG_SYS_SRIO1_MEM_VIRT
+ SRIO_MAINT_WIN_SIZE
- + CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET,
- CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK);
+ + CFG_SRIO_PCIE_BOOT_BRR_OFFSET,
+ CFG_SRIO_PCIE_BOOT_RELEASE_MASK);
}
debug("SRIOBOOT - MASTER: "
"Release slave successfully! Now the slave should start up!\n");
diff --git a/board/freescale/common/p_corenet/tlb.c b/board/freescale/common/p_corenet/tlb.c
index 4cdef89bf0e..7302b760662 100644
--- a/board/freescale/common/p_corenet/tlb.c
+++ b/board/freescale/common/p_corenet/tlb.c
@@ -69,8 +69,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
* SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
* space is at 0xfff00000, it covered the 0xfffff000.
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
- CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+ CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
#else
@@ -150,8 +150,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
* SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
* fetching ucode and ENV from master
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
- CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+ CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
0, 17, BOOKE_PAGESZ_1M, 1),
#endif
diff --git a/board/freescale/t208xqds/tlb.c b/board/freescale/t208xqds/tlb.c
index 9160674b94f..f2448e86c0d 100644
--- a/board/freescale/t208xqds/tlb.c
+++ b/board/freescale/t208xqds/tlb.c
@@ -43,8 +43,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
* SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
* space is at 0xfff00000, it covered the 0xfffff000.
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
- CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+ CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
#else
@@ -136,8 +136,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
* SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
* fetching ucode and ENV from master
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
- CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+ CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
0, 18, BOOKE_PAGESZ_1M, 1),
#endif
diff --git a/board/freescale/t208xrdb/tlb.c b/board/freescale/t208xrdb/tlb.c
index 69e58e7e973..45c27c08120 100644
--- a/board/freescale/t208xrdb/tlb.c
+++ b/board/freescale/t208xrdb/tlb.c
@@ -43,8 +43,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
* SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
* space is at 0xfff00000, it covered the 0xfffff000.
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
- CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
+ CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
0, 0, BOOKE_PAGESZ_1M, 1),
#else
@@ -136,8 +136,8 @@ struct fsl_e_tlb_entry tlb_table[] = {
* SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
* fetching ucode and ENV from master
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
- CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
+ SET_TLB_ENTRY(1, CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
+ CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
0, 18, BOOKE_PAGESZ_1M, 1),
#endif
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index eb75f8b37d5..25b4fe0c7d4 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -282,13 +282,13 @@
/*
* RapidIO MMU
*/
-#define CONFIG_SYS_SRIO1_MEM_VIRT 0xc0000000
+#define CFG_SYS_SRIO1_MEM_VIRT 0xc0000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc40000000ull
+#define CFG_SYS_SRIO1_MEM_PHYS 0xc40000000ull
#else
-#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc0000000
+#define CFG_SYS_SRIO1_MEM_PHYS 0xc0000000
#endif
-#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
+#define CFG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */
#if defined(CONFIG_TSEC_ENET)
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index be8d09f6dd7..c3ef2163335 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -18,9 +18,9 @@
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/* Set 1M boot space */
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
+#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+ (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif
@@ -173,49 +173,49 @@
/*
* RapidIO
*/
-#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
+#define CFG_SYS_SRIO1_MEM_VIRT 0xa0000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
+#define CFG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
#else
-#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000
+#define CFG_SYS_SRIO1_MEM_PHYS 0xa0000000
#endif
-#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
+#define CFG_SYS_SRIO2_MEM_VIRT 0xb0000000
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
+#define CFG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
#else
-#define CONFIG_SYS_SRIO2_MEM_PHYS 0xb0000000
+#define CFG_SYS_SRIO2_MEM_PHYS 0xb0000000
#endif
-#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
/*
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
+#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
+#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
+#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
+#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
/* slave core release by master*/
-#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
-#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
/*
* SRIO_PCIE_BOOT - SLAVE
*/
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+ (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
#endif
/*
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h
index f9f9318448b..b567b63980e 100644
--- a/include/configs/T102xRDB.h
+++ b/include/configs/T102xRDB.h
@@ -53,40 +53,40 @@
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
+#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
+#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
#else
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
+#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xef200000
+#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0xfff00000
#endif
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
#ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
+#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
#else
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
+#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xef100000
+#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0xffe00000
#endif
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
+#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
/* slave core release by master*/
-#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
-#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
/* PCIe Boot - Slave */
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+ (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
/* Set 1M boot space for PCIe boot */
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
+#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+ (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif
diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h
index acaad1bfc82..798822e5031 100644
--- a/include/configs/T208xQDS.h
+++ b/include/configs/T208xQDS.h
@@ -49,9 +49,9 @@
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/* Set 1M boot space */
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
+#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+ (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif
@@ -295,39 +295,39 @@
/*
* RapidIO
*/
-#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
-#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
-#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
-#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_SYS_SRIO1_MEM_VIRT 0xa0000000
+#define CFG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
+#define CFG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_SYS_SRIO2_MEM_VIRT 0xb0000000
+#define CFG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
+#define CFG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
/*
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
+#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
+#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
+#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
+#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
/* slave core release by master*/
-#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
-#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
/*
* SRIO_PCIE_BOOT - SLAVE
*/
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+ (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
#endif
/*
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h
index 7315afa39f8..ea366b671c0 100644
--- a/include/configs/T208xRDB.h
+++ b/include/configs/T208xRDB.h
@@ -49,9 +49,9 @@
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
/* Set 1M boot space */
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
-#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
+#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000)
+#define CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
+ (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif
@@ -254,39 +254,39 @@
/*
* RapidIO
*/
-#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
-#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
-#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
-#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
-#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
-#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_SYS_SRIO1_MEM_VIRT 0xa0000000
+#define CFG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
+#define CFG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
+#define CFG_SYS_SRIO2_MEM_VIRT 0xb0000000
+#define CFG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
+#define CFG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
/*
* for slave u-boot IMAGE instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
-#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
+#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
+#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
+#define CFG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
+#define CFG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
/*
* for slave UCODE and ENV instored in master memory space,
* PHYS must be aligned based on the SIZE
*/
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
-#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
+#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
+#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
+#define CFG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
/* slave core release by master*/
-#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
-#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
+#define CFG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
+#define CFG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
/*
* SRIO_PCIE_BOOT - SLAVE
*/
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
-#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
- (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
+#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
+#define CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
+ (0x300000000ull | CFG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
#endif
/*
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-10 15:43:56 +0000