diff options
29 files changed, 598 insertions, 90 deletions
diff --git a/arch/arm/include/asm/boot0-linux-kernel-header.h b/arch/arm/include/asm/boot0-linux-kernel-header.h index c6cd76f32af..c930fea5fd4 100644 --- a/arch/arm/include/asm/boot0-linux-kernel-header.h +++ b/arch/arm/include/asm/boot0-linux-kernel-header.h @@ -31,8 +31,6 @@ .long \sym\()_hi32 .endm -.globl _start -_start: /* * DO NOT MODIFY. Image header expected by Linux boot-loaders. */ diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c index 026c4f9c02d..787fe922955 100644 --- a/arch/arm/mach-k3/am625_init.c +++ b/arch/arm/mach-k3/am625_init.c @@ -15,6 +15,15 @@ #include <dm/uclass-internal.h> #include <dm/pinctrl.h> +#define RTC_BASE_ADDRESS 0x2b1f0000 +#define REG_K3RTC_S_CNT_LSW (RTC_BASE_ADDRESS + 0x18) +#define REG_K3RTC_KICK0 (RTC_BASE_ADDRESS + 0x70) +#define REG_K3RTC_KICK1 (RTC_BASE_ADDRESS + 0x74) + +/* Magic values for lock/unlock */ +#define K3RTC_KICK0_UNLOCK_VALUE 0x83e70b13 +#define K3RTC_KICK1_UNLOCK_VALUE 0x95a4f1e0 + /* * This uninitialized global variable would normal end up in the .bss section, * but the .bss is cleared between writing and reading this variable, so move @@ -71,6 +80,42 @@ static __maybe_unused void enable_mcu_esm_reset(void) writel(stat, CTRLMMR_MCU_RST_CTRL); } +#if defined(CONFIG_CPU_V7R) + +/* + * RTC Erratum i2327 Workaround for Silicon Revision 1 + * + * Due to a bug in initial synchronization out of cold power on, + * IRQ status can get locked infinitely if we do not unlock RTC + * + * This workaround *must* be applied within 1 second of power on, + * So, this is closest point to be able to guarantee the max + * timing. + * + * https://www.ti.com/lit/er/sprz487c/sprz487c.pdf + */ +void rtc_erratumi2327_init(void) +{ + u32 counter; + + /* + * If counter has gone past 1, nothing we can do, leave + * system locked! This is the only way we know if RTC + * can be used for all practical purposes. + */ + counter = readl(REG_K3RTC_S_CNT_LSW); + if (counter > 1) + return; + /* + * Need to set this up at the very start + * MUST BE DONE under 1 second of boot. + */ + writel(K3RTC_KICK0_UNLOCK_VALUE, REG_K3RTC_KICK0); + writel(K3RTC_KICK1_UNLOCK_VALUE, REG_K3RTC_KICK1); + return; +} +#endif + void board_init_f(ulong dummy) { struct udevice *dev; @@ -78,6 +123,7 @@ void board_init_f(ulong dummy) #if defined(CONFIG_CPU_V7R) setup_k3_mpu_regions(); + rtc_erratumi2327_init(); #endif /* diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c index 88687c2d094..f8087d2421e 100644 --- a/arch/arm/mach-k3/arm64-mmu.c +++ b/arch/arm/mach-k3/arm64-mmu.c @@ -222,14 +222,13 @@ struct mm_region *mem_map = j721s2_mem_map; #endif /* CONFIG_SOC_K3_J721S2 */ -#if defined(CONFIG_SOC_K3_AM642) || defined(CONFIG_SOC_K3_AM625) || \ - defined(CONFIG_SOC_K3_AM62A7) +#if defined(CONFIG_SOC_K3_AM625) || defined(CONFIG_SOC_K3_AM62A7) /* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ -#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 3) +#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 4) /* ToDo: Add 64bit IO */ -struct mm_region am64_mem_map[NR_MMU_REGIONS] = { +struct mm_region am62_mem_map[NR_MMU_REGIONS] = { { .virt = 0x0UL, .phys = 0x0UL, @@ -240,10 +239,65 @@ struct mm_region am64_mem_map[NR_MMU_REGIONS] = { }, { .virt = 0x80000000UL, .phys = 0x80000000UL, + .size = 0x1E780000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xA0000000UL, + .phys = 0xA0000000UL, + .size = 0x60000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + + }, { + .virt = 0x880000000UL, + .phys = 0x880000000UL, .size = 0x80000000UL, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, { + .virt = 0x500000000UL, + .phys = 0x500000000UL, + .size = 0x400000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = am62_mem_map; +#endif /* CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */ + +#ifdef CONFIG_SOC_K3_AM642 + +/* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */ +#define NR_MMU_REGIONS (CONFIG_NR_DRAM_BANKS + 4) + +/* ToDo: Add 64bit IO */ +struct mm_region am64_mem_map[NR_MMU_REGIONS] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x1E800000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0xA0000000UL, + .phys = 0xA0000000UL, + .size = 0x60000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { .virt = 0x880000000UL, .phys = 0x880000000UL, .size = 0x80000000UL, @@ -263,4 +317,4 @@ struct mm_region am64_mem_map[NR_MMU_REGIONS] = { }; struct mm_region *mem_map = am64_mem_map; -#endif /* CONFIG_SOC_K3_AM642 || CONFIG_SOC_K3_AM625 || CONFIG_SOC_K3_AM62A7 */ +#endif /* CONFIG_SOC_K3_AM642 */ diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 3c85caee579..0e045919dd0 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -563,39 +563,51 @@ void disable_linefill_optimization(void) } #endif -void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size) +static void remove_fwl_regions(struct fwl_data fwl_data, size_t num_regions, + enum k3_firewall_region_type fwl_type) { - struct ti_sci_msg_fwl_region region; struct ti_sci_fwl_ops *fwl_ops; struct ti_sci_handle *ti_sci; - size_t i, j; + struct ti_sci_msg_fwl_region region; + size_t j; ti_sci = get_ti_sci_handle(); fwl_ops = &ti_sci->ops.fwl_ops; - for (i = 0; i < fwl_data_size; i++) { - for (j = 0; j < fwl_data[i].regions; j++) { - region.fwl_id = fwl_data[i].fwl_id; - region.region = j; - region.n_permission_regs = 3; - - fwl_ops->get_fwl_region(ti_sci, ®ion); - - /* Don't disable the background regions */ - if (region.control != 0 && - ((region.control & K3_BACKGROUND_FIREWALL_BIT) == - 0)) { - pr_debug("Attempting to disable firewall %5d (%25s)\n", - region.fwl_id, fwl_data[i].name); - region.control = 0; - - if (fwl_ops->set_fwl_region(ti_sci, ®ion)) - pr_err("Could not disable firewall %5d (%25s)\n", - region.fwl_id, fwl_data[i].name); - } + + for (j = 0; j < fwl_data.regions; j++) { + region.fwl_id = fwl_data.fwl_id; + region.region = j; + region.n_permission_regs = 3; + + fwl_ops->get_fwl_region(ti_sci, ®ion); + + /* Don't disable the background regions */ + if (region.control != 0 && + ((region.control & K3_FIREWALL_BACKGROUND_BIT) == + fwl_type)) { + pr_debug("Attempting to disable firewall %5d (%25s)\n", + region.fwl_id, fwl_data.name); + region.control = 0; + + if (fwl_ops->set_fwl_region(ti_sci, ®ion)) + pr_err("Could not disable firewall %5d (%25s)\n", + region.fwl_id, fwl_data.name); } } } +void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size) +{ + size_t i; + + for (i = 0; i < fwl_data_size; i++) { + remove_fwl_regions(fwl_data[i], fwl_data[i].regions, + K3_FIREWALL_REGION_FOREGROUND); + remove_fwl_regions(fwl_data[i], fwl_data[i].regions, + K3_FIREWALL_REGION_BACKGROUND); + } +} + void spl_enable_dcache(void) { #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) diff --git a/arch/arm/mach-k3/common.h b/arch/arm/mach-k3/common.h index e7e59f533b7..a994c3df3e0 100644 --- a/arch/arm/mach-k3/common.h +++ b/arch/arm/mach-k3/common.h @@ -9,9 +9,7 @@ #include <asm/armv7_mpu.h> #include <asm/hardware.h> -#define J721E 0xbb64 -#define J7200 0xbb6d -#define K3_BACKGROUND_FIREWALL_BIT BIT(8) +#define K3_FIREWALL_BACKGROUND_BIT BIT(8) struct fwl_data { const char *name; @@ -19,6 +17,11 @@ struct fwl_data { u16 regions; }; +enum k3_firewall_region_type { + K3_FIREWALL_REGION_FOREGROUND, + K3_FIREWALL_REGION_BACKGROUND +}; + enum k3_device_type { K3_DEVICE_TYPE_BAD, K3_DEVICE_TYPE_GP, diff --git a/arch/arm/mach-k3/j7200/clk-data.c b/arch/arm/mach-k3/j7200/clk-data.c index 0437e30abb4..9b45786a2d4 100644 --- a/arch/arm/mach-k3/j7200/clk-data.c +++ b/arch/arm/mach-k3/j7200/clk-data.c @@ -379,6 +379,7 @@ static const struct clk_data clk_list[] = { CLK_MUX("main_pll4_xref_sel_out0", main_pll4_xref_sel_out0_parents, 2, 0x43008090, 4, 1, 0), CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0), CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000), + CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out1", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c4, 0, 2, 0, 0, 48000000), CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0), CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfracf_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0, 0), CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0), @@ -534,6 +535,8 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(197, 2, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), DEV_CLK(202, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"), DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(278, 2, "usart_programmable_clock_divider_out1"), + DEV_CLK(278, 3, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(288, 3, "postdiv2_16fft_main_1_hsdivout7_clk"), DEV_CLK(288, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(288, 6, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), @@ -546,7 +549,7 @@ static const struct dev_clk soc_dev_clk_data[] = { const struct ti_k3_clk_platdata j7200_clk_platdata = { .clk_list = clk_list, - .clk_list_cnt = 108, + .clk_list_cnt = 109, .soc_dev_clk_data = soc_dev_clk_data, - .soc_dev_clk_data_cnt = 127, + .soc_dev_clk_data_cnt = 129, }; diff --git a/arch/arm/mach-k3/j7200/dev-data.c b/arch/arm/mach-k3/j7200/dev-data.c index d3194ae51a9..c1a4dab6941 100644 --- a/arch/arm/mach-k3/j7200/dev-data.c +++ b/arch/arm/mach-k3/j7200/dev-data.c @@ -53,6 +53,7 @@ static struct ti_dev soc_dev_list[] = { PSC_DEV(92, &soc_lpsc_list[5]), PSC_DEV(91, &soc_lpsc_list[6]), PSC_DEV(146, &soc_lpsc_list[7]), + PSC_DEV(278, &soc_lpsc_list[7]), PSC_DEV(4, &soc_lpsc_list[8]), PSC_DEV(4, &soc_lpsc_list[9]), PSC_DEV(202, &soc_lpsc_list[10]), @@ -77,5 +78,5 @@ const struct ti_k3_pd_platdata j7200_pd_platdata = { .num_psc = 2, .num_pd = 6, .num_lpsc = 17, - .num_devs = 22, + .num_devs = 23, }; diff --git a/arch/arm/mach-k3/j721e/clk-data.c b/arch/arm/mach-k3/j721e/clk-data.c index 5ab795139e1..e4511092c86 100644 --- a/arch/arm/mach-k3/j721e/clk-data.c +++ b/arch/arm/mach-k3/j721e/clk-data.c @@ -553,6 +553,7 @@ static const struct clk_data clk_list[] = { CLK_MUX("main_pll4_xref_sel_out0", main_pll4_xref_sel_out0_parents, 2, 0x43008090, 4, 1, 0), CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0), CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000), + CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out2", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c8, 0, 2, 0, 0, 48000000), CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0), CLK_DIV("hsdiv0_16fft_main_6_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_6_foutvcop_clk", 0x686080, 0, 7, 0, 0), CLK_DIV("hsdiv0_16fft_main_7_hsdivout0_clk", "pllfrac2_ssmod_16fft_main_7_foutvcop_clk", 0x687080, 0, 7, 0, 0), @@ -760,6 +761,8 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(197, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), DEV_CLK(202, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"), DEV_CLK(203, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"), + DEV_CLK(279, 0, "usart_programmable_clock_divider_out2"), + DEV_CLK(279, 1, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(288, 3, "postdiv3_16fft_main_1_hsdivout7_clk"), DEV_CLK(288, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(288, 5, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), @@ -780,7 +783,7 @@ static const struct dev_clk soc_dev_clk_data[] = { const struct ti_k3_clk_platdata j721e_clk_platdata = { .clk_list = clk_list, - .clk_list_cnt = 156, + .clk_list_cnt = 157, .soc_dev_clk_data = soc_dev_clk_data, - .soc_dev_clk_data_cnt = 171, + .soc_dev_clk_data_cnt = 173, }; diff --git a/arch/arm/mach-k3/j721e/dev-data.c b/arch/arm/mach-k3/j721e/dev-data.c index 300d998c626..f0afa3552b7 100644 --- a/arch/arm/mach-k3/j721e/dev-data.c +++ b/arch/arm/mach-k3/j721e/dev-data.c @@ -46,6 +46,7 @@ static struct ti_dev soc_dev_list[] = { PSC_DEV(30, &soc_lpsc_list[0]), PSC_DEV(61, &soc_lpsc_list[0]), PSC_DEV(146, &soc_lpsc_list[1]), + PSC_DEV(279, &soc_lpsc_list[1]), PSC_DEV(90, &soc_lpsc_list[2]), PSC_DEV(47, &soc_lpsc_list[3]), PSC_DEV(288, &soc_lpsc_list[4]), @@ -75,5 +76,5 @@ const struct ti_k3_pd_platdata j721e_pd_platdata = { .num_psc = 2, .num_pd = 5, .num_lpsc = 16, - .num_devs = 22, + .num_devs = 23, }; diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c index 0c5d41a77e6..b6164575b7b 100644 --- a/arch/arm/mach-k3/j721e_init.c +++ b/arch/arm/mach-k3/j721e_init.c @@ -294,7 +294,7 @@ u32 spl_mmc_boot_mode(struct mmc *mmc, const u32 boot_device) { switch (boot_device) { case BOOT_DEVICE_MMC1: - return MMCSD_MODE_EMMCBOOT; + return (spl_mmc_emmc_boot_partition(mmc) ? MMCSD_MODE_EMMCBOOT : MMCSD_MODE_FS); case BOOT_DEVICE_MMC2: return MMCSD_MODE_FS; default: diff --git a/arch/arm/mach-k3/j721s2/clk-data.c b/arch/arm/mach-k3/j721s2/clk-data.c index ad6bd991b70..0c5c321c1eb 100644 --- a/arch/arm/mach-k3/j721s2/clk-data.c +++ b/arch/arm/mach-k3/j721s2/clk-data.c @@ -247,6 +247,7 @@ static const struct clk_data clk_list[] = { CLK_MUX("emmcsd1_lb_clksel_out0", emmcsd1_lb_clksel_out0_parents, 2, 0x1080b4, 16, 1, 0), CLK_MUX("mcu_clkout_mux_out0", mcu_clkout_mux_out0_parents, 2, 0x40f08010, 0, 1, 0), CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081c0, 0, 2, 0, 0, 48000000), + CLK_DIV("usart_programmable_clock_divider_out5", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081d4, 0, 2, 0, 0), CLK_DIV("usart_programmable_clock_divider_out8", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x1081e0, 0, 2, 0, 0), CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0), CLK_DIV("hsdiv0_16fft_main_26_hsdivout0_clk", "pllfracf2_ssmod_16fft_main_26_foutvcop_clk", 0x69a080, 0, 7, 0, 0), @@ -383,6 +384,8 @@ static const struct dev_clk soc_dev_clk_data[] = { DEV_CLK(223, 3, "gluelogic_hfosc0_clkout"), DEV_CLK(223, 4, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"), DEV_CLK(223, 5, "board_0_wkup_i2c0_scl_out"), + DEV_CLK(354, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), + DEV_CLK(354, 3, "usart_programmable_clock_divider_out5"), DEV_CLK(357, 2, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), DEV_CLK(357, 3, "usart_programmable_clock_divider_out8"), DEV_CLK(360, 4, "k3_pll_ctrl_wrap_main_0_chip_div1_clk_clk"), @@ -397,7 +400,7 @@ static const struct dev_clk soc_dev_clk_data[] = { const struct ti_k3_clk_platdata j721s2_clk_platdata = { .clk_list = clk_list, - .clk_list_cnt = 104, + .clk_list_cnt = 105, .soc_dev_clk_data = soc_dev_clk_data, - .soc_dev_clk_data_cnt = 122, + .soc_dev_clk_data_cnt = 124, }; diff --git a/arch/arm/mach-k3/j721s2/dev-data.c b/arch/arm/mach-k3/j721s2/dev-data.c index e36f1edb786..35e8b17eb1e 100644 --- a/arch/arm/mach-k3/j721s2/dev-data.c +++ b/arch/arm/mach-k3/j721s2/dev-data.c @@ -67,6 +67,7 @@ static struct ti_dev soc_dev_list[] = { PSC_DEV(99, &soc_lpsc_list[12]), PSC_DEV(98, &soc_lpsc_list[13]), PSC_DEV(146, &soc_lpsc_list[14]), + PSC_DEV(354, &soc_lpsc_list[15]), PSC_DEV(357, &soc_lpsc_list[15]), PSC_DEV(4, &soc_lpsc_list[16]), PSC_DEV(202, &soc_lpsc_list[17]), @@ -81,5 +82,5 @@ const struct ti_k3_pd_platdata j721s2_pd_platdata = { .num_psc = 2, .num_pd = 6, .num_lpsc = 19, - .num_devs = 24, + .num_devs = 25, }; diff --git a/arch/sandbox/include/asm/axi.h b/arch/sandbox/include/asm/axi.h index d483f7b65a0..5b94beda0ab 100644 --- a/arch/sandbox/include/asm/axi.h +++ b/arch/sandbox/include/asm/axi.h @@ -14,8 +14,8 @@ * @bus: The AXI bus from which to retrieve a emulation device * @address: The address of a transfer that should be handled by a emulation * device - * @length: The data width of a transfer that should be handled by a emulation - * device + * @size: A constant indicating the data width of the transfer that + * should be handled by an emulation device * @emulp: Pointer to a buffer receiving the emulation device that handles * the transfer specified by the address and length parameters * @@ -45,8 +45,8 @@ * Return: 0 of OK, -ENODEV if no device capable of handling the specified * transfer exists or the device could not be retrieved */ -int axi_sandbox_get_emul(struct udevice *bus, ulong address, uint length, - struct udevice **emulp); +int axi_sandbox_get_emul(struct udevice *bus, ulong address, + const enum axi_size_t size, struct udevice **emulp); /** * axi_get_store() - Get address of internal storage of a emulated AXI device * @dev: Emulated AXI device to get the pointer of the internal storage diff --git a/board/vscom/baltos/board.c b/board/vscom/baltos/board.c index f335d5b4f4a..8f23cda8e4f 100644 --- a/board/vscom/baltos/board.c +++ b/board/vscom/baltos/board.c @@ -76,17 +76,23 @@ static int baltos_set_console(void) static int read_eeprom(BSP_VS_HWPARAM *header) { - i2c_set_bus_num(1); + int rc; + struct udevice *dev; + struct udevice *bus; + + rc = uclass_get_device_by_seq(UCLASS_I2C, 1, &bus); + if (rc) + return rc; /* Check if baseboard eeprom is available */ - if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) { + if (dm_i2c_probe(bus, CONFIG_SYS_I2C_EEPROM_ADDR, 0, &dev)) { puts("Could not probe the EEPROM; something fundamentally " "wrong on the I2C bus.\n"); return -ENODEV; } /* read the eeprom using i2c */ - if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header, + if (dm_i2c_read(dev, 0, (uchar *)header, sizeof(BSP_VS_HWPARAM))) { puts("Could not read the EEPROM; something fundamentally" " wrong on the I2C bus.\n"); @@ -173,34 +179,28 @@ const struct dpll_params dpll_ddr_baltos = { void am33xx_spl_board_init(void) { - int mpu_vdd; - int sil_rev; + int sil_rev, mpu_vdd; + int freq; + + enable_i2c1_pin_mux(); + i2c_set_bus_num(1); - /* Get the frequency */ - dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev); + freq = am335x_get_efuse_mpu_max_freq(cdev); /* - * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all + * The GP EVM, IDK and EVM SK use a TPS65910 PMIC. For all * MPU frequencies we support we use a CORE voltage of - * 1.1375V. For MPU voltage we need to switch based on + * 1.1375V. For MPU voltage we need to switch based on * the frequency we are running at. */ - i2c_set_bus_num(1); - - printf("I2C speed: %d Hz\n", CONFIG_SYS_I2C_SPEED); - - if (i2c_probe(TPS65910_CTRL_I2C_ADDR)) { - puts("i2c: cannot access TPS65910\n"); + if (power_tps65910_init(1)) return; - } - /* * Depending on MPU clock and PG we will need a different * VDD to drive at that speed. */ sil_rev = readl(&cdev->deviceid) >> 28; - mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, - dpll_mpu_opp100.m); + mpu_vdd = am335x_get_tps65910_mpu_vdd(sil_rev, freq); /* Tell the TPS65910 to use i2c */ tps65910_set_i2c_control(); @@ -213,12 +213,6 @@ void am33xx_spl_board_init(void) if (tps65910_voltage_update(CORE, TPS65910_OP_REG_SEL_1_1_3)) return; - /* Set CORE Frequencies to OPP100 */ - do_setup_dpll(&dpll_core_regs, &dpll_core_opp100); - - /* Set MPU Frequency to what we detected now that voltages are set */ - do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); - writel(0x000010ff, PRM_DEVICE_INST + 4); } diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig index 090b902be30..6ef3c78390a 100644 --- a/configs/am335x_baltos_defconfig +++ b/configs/am335x_baltos_defconfig @@ -18,7 +18,6 @@ CONFIG_OF_BOARD_SETUP=y CONFIG_DISTRO_DEFAULTS=y CONFIG_BOOTCOMMAND="run findfdt; run usbboot;run mmcboot;setenv mmcdev 1; setenv bootpart 1:2; run mmcboot;run nandboot;" CONFIG_SYS_CONSOLE_INFO_QUIET=y -CONFIG_ARCH_MISC_INIT=y CONFIG_SYS_SPL_MALLOC=y CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SPL_FS_EXT4=y @@ -57,10 +56,10 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y CONFIG_VERSION_VARIABLE=y CONFIG_NET_RETRY_COUNT=10 CONFIG_BOOTP_SEND_HOSTNAME=y +# CONFIG_TI_SYSC is not set CONFIG_BOOTCOUNT_LIMIT=y -CONFIG_SYS_I2C_LEGACY=y +CONFIG_DM_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y -CONFIG_SYS_I2C_SPEED=1000 CONFIG_SYS_I2C_EEPROM_ADDR=0x50 CONFIG_MMC_OMAP_HS=y CONFIG_MMC_OMAP_HS_ADMA=y @@ -79,6 +78,8 @@ CONFIG_PHY_SMSC=y CONFIG_DM_MDIO=y CONFIG_MII=y CONFIG_DRIVER_TI_CPSW=y +CONFIG_DM_PMIC=y +# CONFIG_PMIC_CHILDREN is not set CONFIG_SPL_POWER_TPS65910=y CONFIG_SPI=y CONFIG_DM_SPI=y @@ -94,5 +95,4 @@ CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00 CONFIG_USB_GADGET_DOWNLOAD=y CONFIG_USB_FUNCTION_MASS_STORAGE=y CONFIG_USB_ETHER=y -CONFIG_USBNET_HOST_ADDR="de:ad:be:af:00:00" CONFIG_WDT=y diff --git a/configs/am62ax_evm_a53_defconfig b/configs/am62ax_evm_a53_defconfig index 41fa6f38aa7..76ec5ed4046 100644 --- a/configs/am62ax_evm_a53_defconfig +++ b/configs/am62ax_evm_a53_defconfig @@ -35,6 +35,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_POWER_DOMAIN=y +CONFIG_SPL_YMODEM_SUPPORT=y CONFIG_CMD_MMC=y CONFIG_OF_CONTROL=y CONFIG_SPL_OF_CONTROL=y diff --git a/configs/j7200_evm_a72_defconfig b/configs/j7200_evm_a72_defconfig index 713238b180d..cc68a212179 100644 --- a/configs/j7200_evm_a72_defconfig +++ b/configs/j7200_evm_a72_defconfig @@ -47,7 +47,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SYS_SPL_MALLOC=y CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1800 CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig index e149ccb9a41..c4dd33627bd 100644 --- a/configs/j7200_evm_r5_defconfig +++ b/configs/j7200_evm_r5_defconfig @@ -43,7 +43,7 @@ CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000 CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 CONFIG_SPL_EARLY_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_EXT4=y diff --git a/configs/j721e_hs_evm_a72_defconfig b/configs/j721e_hs_evm_a72_defconfig index f6e2a3d5a87..db642d52e50 100644 --- a/configs/j721e_hs_evm_a72_defconfig +++ b/configs/j721e_hs_evm_a72_defconfig @@ -45,7 +45,7 @@ CONFIG_SPL_STACK_R=y CONFIG_SYS_SPL_MALLOC=y CONFIG_SYS_SPL_MALLOC_SIZE=0x800000 CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1800 CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" diff --git a/configs/j721e_hs_evm_r5_defconfig b/configs/j721e_hs_evm_r5_defconfig index d06ccf944a8..c32f1cbf639 100644 --- a/configs/j721e_hs_evm_r5_defconfig +++ b/configs/j721e_hs_evm_r5_defconfig @@ -44,7 +44,7 @@ CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000 CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000 CONFIG_SPL_EARLY_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y -CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800 CONFIG_SPL_DMA=y CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_EXT4=y diff --git a/doc/board/ti/j7200_evm.rst b/doc/board/ti/j7200_evm.rst new file mode 100644 index 00000000000..0d3a526516c --- /dev/null +++ b/doc/board/ti/j7200_evm.rst @@ -0,0 +1,332 @@ +.. SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +.. sectionauthor:: Udit Kumar <u-kumar1@ti.com> + +J7200 Platforms +=============== + +Introduction: +------------- +The J7200 family of SoCs are part of K3 Multicore SoC architecture platform +targeting automotive applications. They are designed as a low power, high +performance and highly integrated device architecture, adding significant +enhancement on processing power, graphics capability, video and imaging +processing, virtualization and coherent memory support. + +The device is partitioned into three functional domains, each containing +specific processing cores and peripherals: + +1. Wake-up (WKUP) domain: + * Device Management and Security Controller (DMSC) + +2. Microcontroller (MCU) domain: + * Dual Core ARM Cortex-R5F processor + +3. MAIN domain: + * Dual core 64-bit ARM Cortex-A72 + +More info can be found in TRM: https://www.ti.com/lit/pdf/spruiu1 + +Boot Flow: +---------- +Below is the pictorial representation of boot flow: + +.. code-block:: text + + +------------------------------------------------------------------------+-----------------------+ + | DMSC | MCU R5 | A72 | MAIN R5/C7x | + +------------------------------------------------------------------------+-----------------------+ + | +--------+ | | | | + | | Reset | | | | | + | +--------+ | | | | + | : | | | | + | +--------+ | +-----------+ | | | + | | *ROM* |----------|-->| Reset rls | | | | + | +--------+ | +-----------+ | | | + | | | | : | | | + | | ROM | | : | | | + | |services| | : | | | + | | | | +-------------+ | | | + | | | | | *R5 ROM* | | | | + | | | | +-------------+ | | | + | | |<---------|---|Load and auth| | | | + | | | | | tiboot3.bin | | | | + | | Start | | +-------------+ | | | + | | TIFS |<---------|---| Start | | | | + | | | | | TIFS | | | | + | +--------+ | +-------------+ | | | + | : | | | | | | + | +---------+ | | Load | | | | + | | *TIFS* | | | system | | | | + | +---------+ | | Config data | | | | + | | |<--------|---| | | | | + | | | | +-------------+ | | | + | | | | : | | | + | | | | : | | | + | | | | : | | | + | | | | +-------------+ | | | + | | | | | *R5 SPL* | | | | + | | | | +-------------+ | | | + | | | | | DDR | | | | + | | | | | config | | | | + | | | | +-------------+ | | | + | | | | | Load | | | | + | | | | | tispl.bin | | | | + | | | | +-------------+ | | | + | | | | | Load R5 | | | | + | | | | | firmware | | | | + | | | | +-------------+ | | | + | | |<--------|---| Start A72 | | | | + | | | | | and jump to | | | | + | | | | | DM fw image | | | | + | | | | +-------------+ | | | + | | | | | +-----------+ | | + | | |---------|-----------------------|---->| Reset rls | | | + | | | | | +-----------+ | | + | | TIFS | | | : | | + | |Services | | | +-----------+ | | + | | |<--------|-----------------------|---->|*ATF/OPTEE*| | | + | | | | | +-----------+ | | + | | | | | : | | + | | | | | +-----------+ | | + | | |<--------|-----------------------|---->| *A72 SPL* | | | + | | | | | +-----------+ | | + | | | | | | Load | | | + | | | | | | u-boot.img| | | + | | | | | +-----------+ | | + | | | | | : | | + | | | | | +-----------+ | | + | | |<--------|-----------------------|---->| *U-Boot* | | | + | | | | | +-----------+ | | + | | | | | | prompt | | | + | | | | | +-----------+ | | + | | | | | | Load R5 | | | + | | | | | | Firmware | | | + | | | | | +-----------+ | | + | | |<--------|-----------------------|-----| Start R5 | | +-----------+ | + | | |---------|-----------------------|-----+-----------+-----|----->| R5 starts | | + | | | | | | Load C7 | | +-----------+ | + | | | | | | Firmware | | | + | | | | | +-----------+ | | + | | |<--------|-----------------------|-----| Start C7 | | +-----------+ | + | | |---------|-----------------------|-----+-----------+-----|----->| C7 starts | | + | | | | | | +-----------+ | + | | | | | | | + | +---------+ | | | | + | | | | | + +------------------------------------------------------------------------+-----------------------+ + +- Here DMSC acts as master and provides all the critical services. R5/A72 + requests DMSC to get these services done as shown in the above diagram. + +Sources: +-------- +1. SYSFW: + Tree: git://git.ti.com/k3-image-gen/k3-image-gen.git + Branch: master + +2. ATF: + Tree: https://github.com/ARM-software/arm-trusted-firmware.git + Branch: master + +3. OPTEE: + Tree: https://github.com/OP-TEE/optee_os.git + Branch: master + +4. DM Firmware: + Tree: git://git.ti.com/processor-firmware/ti-linux-firmware.git + Branch: ti-linux-firmware + +5. U-Boot: + Tree: https://source.denx.de/u-boot/u-boot + Branch: master + +Build procedure: +---------------- +1. SYSFW: + +.. code-block:: bash + + make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabihf- SOC=j7200 SBL=u-boot-spl.bin SYSFW_PATH=<path to sysfw>/ti-fs-firmware-j7200-gp.bin + u-boot-spl.bin is generated at step 4. + +2. ATF: + +.. code-block:: bash + + make CROSS_COMPILE=aarch64-linux-gnu- ARCH=aarch64 PLAT=k3 TARGET_BOARD=generic SPD=opteed + +3. OPTEE: + +.. code-block:: bash + + make PLATFORM=k3-j7200 CFG_ARM64_core=y + +4. U-Boot: + +* 4.1 R5: + +.. code-block:: bash + + make CROSS_COMPILE=arm-linux-gnueabihf- j7200_evm_r5_defconfig O=build/r5 + make CROSS_COMPILE=arm-linux-gnueabihf- O=build/r5 + +* 4.2 A72: + +.. code-block:: bash + + make CROSS_COMPILE=aarch64-linux-gnu- j7200_evm_a72_defconfig O=build/a72 + make CROSS_COMPILE=aarch64-linux-gnu- ATF=<ATF dir>/build/k3/generic/release/bl31.bin TEE=<OPTEE OS dir>/out/arm-plat-k3/core/tee-pager_v2.bin DM=<DM firmware>/ti-dm/j7200/ipc_echo_testb_mcu1_0_release_strip.xer5f O=build/a72 + +Target Images +-------------- +Copy the below images to an SD card and boot: + - tiboot3.bin from step 1 + - tispl.bin, u-boot.img from 4.2 + +Image formats: +-------------- + +- tiboot3.bin: + +.. code-block:: console + + +-----------------------+ + | X.509 | + | Certificate | + | +-------------------+ | + | | | | + | | R5 | | + | | u-boot-spl.bin | | + | | | | + | +-------------------+ | + | | | | + | | FIT header | | + | | +---------------+ | | + | | | | | | + | | | DTB 1...N | | | + | | +---------------+ | | + | +-------------------+ | + | | | | + | | FIT HEADER | | + | | +---------------+ | | + | | | | | | + | | | sysfw.bin | | | + | | +---------------+ | | + | | | | | | + | | | board config | | | + | | +---------------+ | | + | | | | | | + | | | PM config | | | + | | +---------------+ | | + | | | | | | + | | | RM config | | | + | | +---------------+ | | + | | | | | | + | | | Secure config | | | + | | +---------------+ | | + | +-------------------+ | + +-----------------------+ + +- tispl.bin + +.. code-block:: console + + +-----------------------+ + | | + | FIT HEADER | + | +-------------------+ | + | | | | + | | A72 ATF | | + | +-------------------+ | + | | | | + | | A72 OPTEE | | + | +-------------------+ | + | | | | + | | R5 DM FW | | + | +-------------------+ | + | | | | + | | A72 SPL | | + | +-------------------+ | + | | | | + | | SPL DTB 1...N | | + | +-------------------+ | + +-----------------------+ + + +Switch Setting for Boot Mode +---------------------------- + +Boot Mode pins provide means to select the boot mode and options before the +device is powered up. After every POR, they are the main source to populate +the Boot Parameter Tables. + +The following table shows some common boot modes used on J7200 platform. More +details can be found in the Technical Reference Manual: +https://www.ti.com/lit/pdf/spruiu1 under the `Boot Mode Pins` section. + + +*Boot Modes* + +============ ============= ============= +Switch Label SW9: 12345678 SW8: 12345678 +============ ============= ============= +SD 00000000 10000010 +EMMC 01000000 10000000 +OSPI 01000000 00000110 +UART 01110000 00000000 +USB DFU 00100000 10000000 +============ ============= ============= + +For SW8 and SW9, the switch state in the "ON" position = 1. + +eMMC: +----- +ROM supports booting from eMMC raw read or UDA FS mode. + +Below is memory layout in case of booting from +boot 0/1 partition in raw mode. + +Current allocated size for tiboot3 size is 1MB, tispl is 2MB. + +Size of u-boot.img is taken 4MB for refernece, +But this is subject to change depending upon atf, optee size + +.. code-block:: console + + boot0/1 partition (8 MB) user partition + 0x0+----------------------------------+ 0x0+------------------------+ + | tiboot3.bin (1 MB) | | | + 0x800+----------------------------------+ | | + | tispl.bin (2 MB) | | | + 0x1800+----------------------------------+ | | + | u-boot.img (4MB) | | | + 0x3800+----------------------------------+ | | + | | | | + 0x3900+ environment | | | + | | | | + 0x3A00+----------------------------------+ +-------------------------+ + +In case of UDA FS mode booting, following is layout. + +All boot images tiboot3.bin, tispl and u-boot should be written to +fat formatted UDA FS as file. + +.. code-block:: console + + boot0/1 partition (8 MB) user partition + 0x0+---------------------------------+ 0x0+-------------------------+ + | | | tiboot3.bin* | + 0x800+----------------------------------+ | | + | | | tispl.bin | + 0x1800+----------------------------------+ | | + | | | u-boot.img | + 0x3800+----------------------------------+ | | + | | | | + 0x3900+ | | environment | + | | | | + 0x3A00+----------------------------------+ +-------------------------+ + + + +In case of booting from eMMC, write above images into raw or UDA FS. +and set mmc partconf accordingly. diff --git a/doc/board/ti/k3.rst b/doc/board/ti/k3.rst index b49a60caf13..2b2f4bb8bbb 100644 --- a/doc/board/ti/k3.rst +++ b/doc/board/ti/k3.rst @@ -31,6 +31,7 @@ K3 Based SoCs :maxdepth: 1 j721e_evm + j7200_evm am62x_sk Boot Flow Overview diff --git a/doc/build/clang.rst b/doc/build/clang.rst index 1d35616eb5e..cc265506c2f 100644 --- a/doc/build/clang.rst +++ b/doc/build/clang.rst @@ -74,3 +74,39 @@ simplified with a simple wrapper script - saved as #!/bin/sh exec clang -target arm-freebsd-eabi --sysroot /usr/arm-freebsd "$@" + + +Known Issues +------------ + +When build U-boot for `xenguest_arm64_defconfig` target, it reports linkage +error: + +.. code-block:: bash + + aarch64-linux-gnu-ld.bfd: drivers/xen/hypervisor.o: in function `do_hypervisor_callback': + /home/leoy/Dev2/u-boot/drivers/xen/hypervisor.c:188: undefined reference to `__aarch64_swp8_acq_rel' + aarch64-linux-gnu-ld.bfd: drivers/xen/hypervisor.o: in function `synch_test_and_set_bit': + /home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:40: undefined reference to `__aarch64_ldset1_acq_rel' + aarch64-linux-gnu-ld.bfd: drivers/xen/hypervisor.o: in function `synch_test_and_clear_bit': + /home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:28: undefined reference to `__aarch64_ldclr1_acq_rel' + aarch64-linux-gnu-ld.bfd: drivers/xen/hypervisor.o: in function `synch_test_and_set_bit': + /home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:40: undefined reference to `__aarch64_ldset1_acq_rel' + aarch64-linux-gnu-ld.bfd: drivers/xen/hypervisor.o: in function `synch_test_and_clear_bit': + /home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:28: undefined reference to `__aarch64_ldclr1_acq_rel' + aarch64-linux-gnu-ld.bfd: drivers/xen/events.o: in function `synch_test_and_clear_bit': + /home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:28: undefined reference to `__aarch64_ldclr1_acq_rel' + aarch64-linux-gnu-ld.bfd: drivers/xen/events.o: in function `synch_test_and_set_bit': + /home/leoy/Dev2/u-boot/./arch/arm/include/asm/xen/system.h:40: undefined reference to `__aarch64_ldset1_acq_rel' + aarch64-linux-gnu-ld.bfd: drivers/xen/gnttab.o: in function `gnttab_end_access': + /home/leoy/Dev2/u-boot/drivers/xen/gnttab.c:109: undefined reference to `__aarch64_cas2_acq_rel' + Segmentation fault + +To fix the failure, we need to append option `-mno-outline-atomics` in Clang +command to not generate local calls to out-of-line atomic operations: + +.. code-block:: bash + + make HOSTCC=clang xenguest_arm64_defconfig + make HOSTCC=clang CROSS_COMPILE=aarch64-linux-gnu- \ + CC="clang -target aarch64-linux-gnueabi -mno-outline-atomics" -j8 diff --git a/drivers/axi/axi-emul-uclass.c b/drivers/axi/axi-emul-uclass.c index 793336d8c47..e6f3ef07200 100644 --- a/drivers/axi/axi-emul-uclass.c +++ b/drivers/axi/axi-emul-uclass.c @@ -14,7 +14,7 @@ #include <asm/axi.h> int axi_sandbox_get_emul(struct udevice *bus, ulong address, - enum axi_size_t size, struct udevice **emulp) + const enum axi_size_t size, struct udevice **emulp) { struct udevice *dev; u32 reg[2]; diff --git a/drivers/firmware/ti_sci.c b/drivers/firmware/ti_sci.c index bd7379ae555..72f572d8248 100644 --- a/drivers/firmware/ti_sci.c +++ b/drivers/firmware/ti_sci.c @@ -265,7 +265,7 @@ static int ti_sci_do_xfer(struct ti_sci_info *info, if (xfer->rx_len) { ret = ti_sci_get_response(info, xfer, &info->chan_rx); if (!ti_sci_is_response_ack(xfer->tx_message.buf)) { - dev_err(info->dev, "Message not acknowledged"); + dev_err(info->dev, "Message not acknowledged\n"); ret = -ENODEV; } } diff --git a/drivers/gpio/npcm_gpio.c b/drivers/gpio/npcm_gpio.c index 8afd57fa8e5..98e5dc79c1c 100644 --- a/drivers/gpio/npcm_gpio.c +++ b/drivers/gpio/npcm_gpio.c @@ -37,14 +37,14 @@ static int npcm_gpio_direction_output(struct udevice *dev, unsigned int offset, { struct npcm_gpio_priv *priv = dev_get_priv(dev); - clrbits_le32(priv->base + GPIO_IEM, BIT(offset)); - writel(BIT(offset), priv->base + GPIO_OES); - if (value) setbits_le32(priv->base + GPIO_DOUT, BIT(offset)); else clrbits_le32(priv->base + GPIO_DOUT, BIT(offset)); + clrbits_le32(priv->base + GPIO_IEM, BIT(offset)); + writel(BIT(offset), priv->base + GPIO_OES); + return 0; } diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c index 23397175d34..34314d0bd1e 100644 --- a/drivers/phy/ti/phy-j721e-wiz.c +++ b/drivers/phy/ti/phy-j721e-wiz.c @@ -256,6 +256,7 @@ enum wiz_type { J721E_WIZ_10G, AM64_WIZ_10G, J784S4_WIZ_10G, + J721S2_WIZ_10G, }; struct wiz_data { @@ -307,6 +308,15 @@ static struct wiz_data j784s4_wiz_10g = { .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, }; +static struct wiz_data j721s2_10g_data = { + .type = J721S2_WIZ_10G, + .pll0_refclk_mux_sel = &pll0_refclk_mux_sel, + .pll1_refclk_mux_sel = &pll1_refclk_mux_sel, + .refclk_dig_sel = &refclk_dig_sel_10g, + .clk_mux_sel = clk_mux_sel_10g, + .clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G, +}; + #define WIZ_TYPEC_DIR_DEBOUNCE_MIN 100 /* ms */ #define WIZ_TYPEC_DIR_DEBOUNCE_MAX 1000 @@ -1037,8 +1047,14 @@ static int j721e_wiz_bind_of_clocks(struct wiz *wiz) ofnode node; int i, rc; - if (type == AM64_WIZ_10G || type == J784S4_WIZ_10G) + switch (type) { + case AM64_WIZ_10G: + case J784S4_WIZ_10G: + case J721S2_WIZ_10G: return j721e_wiz_bind_clocks(wiz); + default: + break; + }; div_clk_drv = lists_driver_lookup_name("wiz_div_clk"); if (!div_clk_drv) { @@ -1282,6 +1298,9 @@ static const struct udevice_id j721e_wiz_ids[] = { { .compatible = "ti,j784s4-wiz-10g", .data = (ulong)&j784s4_wiz_10g, }, + { + .compatible = "ti,j721s2-wiz-10g", .data = (ulong)&j721s2_10g_data, + }, {} }; diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c index 1ad8bfbd880..92513822e70 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c @@ -1552,12 +1552,12 @@ static int npcm7xx_pinconf_set(struct udevice *dev, unsigned int pin, setbits_le32(base + NPCM7XX_GP_N_OES, BIT(gpio)); case PIN_CONFIG_OUTPUT: dev_dbg(dev, "set pin %d output %d\n", pin, arg); - clrbits_le32(base + NPCM7XX_GP_N_IEM, BIT(gpio)); - setbits_le32(base + NPCM7XX_GP_N_OES, BIT(gpio)); if (arg) setbits_le32(base + NPCM7XX_GP_N_DOUT, BIT(gpio)); else clrbits_le32(base + NPCM7XX_GP_N_DOUT, BIT(gpio)); + clrbits_le32(base + NPCM7XX_GP_N_IEM, BIT(gpio)); + setbits_le32(base + NPCM7XX_GP_N_OES, BIT(gpio)); break; case PIN_CONFIG_DRIVE_PUSH_PULL: dev_dbg(dev, "set pin %d push pull\n", pin); diff --git a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c index 0ec47e9577e..f18be08518e 100644 --- a/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c +++ b/drivers/pinctrl/nuvoton/pinctrl-npcm8xx.c @@ -900,12 +900,12 @@ static int npcm8xx_pinconf_set(struct udevice *dev, unsigned int selector, setbits_le32(base + GPIO_OES, BIT(gpio)); case PIN_CONFIG_OUTPUT: dev_dbg(dev, "set pin %d output %d\n", pin, arg); - clrbits_le32(base + GPIO_IEM, BIT(gpio)); - setbits_le32(base + GPIO_OES, BIT(gpio)); if (arg) setbits_le32(base + GPIO_DOUT, BIT(gpio)); else clrbits_le32(base + GPIO_DOUT, BIT(gpio)); + clrbits_le32(base + GPIO_IEM, BIT(gpio)); + setbits_le32(base + GPIO_OES, BIT(gpio)); break; case PIN_CONFIG_DRIVE_PUSH_PULL: dev_dbg(dev, "set pin %d push pull\n", pin); |