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-rw-r--r--arch/arm/dts/ast2500-u-boot.dtsi20
-rw-r--r--drivers/clk/aspeed/clk_ast2500.c38
-rw-r--r--include/dt-bindings/clock/aspeed-clock.h68
3 files changed, 68 insertions, 58 deletions
diff --git a/arch/arm/dts/ast2500-u-boot.dtsi b/arch/arm/dts/ast2500-u-boot.dtsi
index 3b119e4ace6..29b08f16ac6 100644
--- a/arch/arm/dts/ast2500-u-boot.dtsi
+++ b/arch/arm/dts/ast2500-u-boot.dtsi
@@ -25,7 +25,7 @@
reg = <0x1e6e0000 0x174
0x1e6e0200 0x1d4 >;
#reset-cells = <1>;
- clocks = <&scu PLL_MPLL>;
+ clocks = <&scu ASPEED_CLK_MPLL>;
resets = <&rst AST_RESET_SDRAM>;
};
@@ -39,7 +39,7 @@
compatible = "aspeed,ast2500-sdhci";
reg = <0x1e740100>;
#reset-cells = <1>;
- clocks = <&scu BCLK_SDCLK>;
+ clocks = <&scu ASPEED_CLK_SDIO>;
resets = <&rst AST_RESET_SDIO>;
};
@@ -47,7 +47,7 @@
compatible = "aspeed,ast2500-sdhci";
reg = <0x1e740200>;
#reset-cells = <1>;
- clocks = <&scu BCLK_SDCLK>;
+ clocks = <&scu ASPEED_CLK_SDIO>;
resets = <&rst AST_RESET_SDIO>;
};
};
@@ -56,23 +56,23 @@
};
&uart1 {
- clocks = <&scu PCLK_UART1>;
+ clocks = <&scu ASPEED_CLK_GATE_UART1CLK>;
};
&uart2 {
- clocks = <&scu PCLK_UART2>;
+ clocks = <&scu ASPEED_CLK_GATE_UART2CLK>;
};
&uart3 {
- clocks = <&scu PCLK_UART3>;
+ clocks = <&scu ASPEED_CLK_GATE_UART3CLK>;
};
&uart4 {
- clocks = <&scu PCLK_UART4>;
+ clocks = <&scu ASPEED_CLK_GATE_UART4CLK>;
};
&uart5 {
- clocks = <&scu PCLK_UART5>;
+ clocks = <&scu ASPEED_CLK_GATE_UART5CLK>;
};
&timer {
@@ -80,9 +80,9 @@
};
&mac0 {
- clocks = <&scu PCLK_MAC1>, <&scu PLL_D2PLL>;
+ clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>;
};
&mac1 {
- clocks = <&scu PCLK_MAC2>, <&scu PLL_D2PLL>;
+ clocks = <&scu ASPEED_CLK_GATE_MAC1CLK>, <&scu ASPEED_CLK_D2PLL>;
};
diff --git a/drivers/clk/aspeed/clk_ast2500.c b/drivers/clk/aspeed/clk_ast2500.c
index 392fe76b27a..aab7d14deb7 100644
--- a/drivers/clk/aspeed/clk_ast2500.c
+++ b/drivers/clk/aspeed/clk_ast2500.c
@@ -122,8 +122,7 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
ulong rate;
switch (clk->id) {
- case PLL_HPLL:
- case ARMCLK:
+ case ASPEED_CLK_HPLL:
/*
* This ignores dynamic/static slowdown of ARMCLK and may
* be inaccurate.
@@ -131,11 +130,11 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
rate = ast2500_get_hpll_rate(clkin,
readl(&priv->scu->h_pll_param));
break;
- case MCLK_DDR:
+ case ASPEED_CLK_MPLL:
rate = ast2500_get_mpll_rate(clkin,
readl(&priv->scu->m_pll_param));
break;
- case BCLK_PCLK:
+ case ASPEED_CLK_APB:
{
ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
& SCU_PCLK_DIV_MASK)
@@ -146,7 +145,7 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
rate = rate / apb_div;
}
break;
- case BCLK_SDCLK:
+ case ASPEED_CLK_SDIO:
{
ulong apb_div = 4 + 4 * ((readl(&priv->scu->clk_sel1)
& SCU_SDCLK_DIV_MASK)
@@ -157,19 +156,19 @@ static ulong ast2500_clk_get_rate(struct clk *clk)
rate = rate / apb_div;
}
break;
- case PCLK_UART1:
+ case ASPEED_CLK_GATE_UART1CLK:
rate = ast2500_get_uart_clk_rate(priv->scu, 1);
break;
- case PCLK_UART2:
+ case ASPEED_CLK_GATE_UART2CLK:
rate = ast2500_get_uart_clk_rate(priv->scu, 2);
break;
- case PCLK_UART3:
+ case ASPEED_CLK_GATE_UART3CLK:
rate = ast2500_get_uart_clk_rate(priv->scu, 3);
break;
- case PCLK_UART4:
+ case ASPEED_CLK_GATE_UART4CLK:
rate = ast2500_get_uart_clk_rate(priv->scu, 4);
break;
- case PCLK_UART5:
+ case ASPEED_CLK_GATE_UART5CLK:
rate = ast2500_get_uart_clk_rate(priv->scu, 5);
break;
default:
@@ -431,11 +430,10 @@ static ulong ast2500_clk_set_rate(struct clk *clk, ulong rate)
ulong new_rate;
switch (clk->id) {
- case PLL_MPLL:
- case MCLK_DDR:
+ case ASPEED_CLK_MPLL:
new_rate = ast2500_configure_ddr(priv->scu, rate);
break;
- case PLL_D2PLL:
+ case ASPEED_CLK_D2PLL:
new_rate = ast2500_configure_d2pll(priv->scu, rate);
break;
default:
@@ -450,7 +448,7 @@ static int ast2500_clk_enable(struct clk *clk)
struct ast2500_clk_priv *priv = dev_get_priv(clk->dev);
switch (clk->id) {
- case BCLK_SDCLK:
+ case ASPEED_CLK_SDIO:
if (readl(&priv->scu->clk_stop_ctrl1) & SCU_CLKSTOP_SDCLK) {
ast_scu_unlock(priv->scu);
@@ -471,13 +469,13 @@ static int ast2500_clk_enable(struct clk *clk)
* configured based on whether RGMII or RMII mode has been selected
* through hardware strapping.
*/
- case PCLK_MAC1:
+ case ASPEED_CLK_GATE_MAC1CLK:
ast2500_configure_mac(priv->scu, 1);
break;
- case PCLK_MAC2:
+ case ASPEED_CLK_GATE_MAC2CLK:
ast2500_configure_mac(priv->scu, 2);
break;
- case PLL_D2PLL:
+ case ASPEED_CLK_D2PLL:
ast2500_configure_d2pll(priv->scu, D2PLL_DEFAULT_RATE);
break;
default:
@@ -497,9 +495,9 @@ static int ast2500_clk_ofdata_to_platdata(struct udevice *dev)
{
struct ast2500_clk_priv *priv = dev_get_priv(dev);
- priv->scu = dev_read_addr_ptr(dev);
- if (!priv->scu)
- return -EINVAL;
+ priv->scu = devfdt_get_addr_ptr(dev);
+ if (IS_ERR(priv->scu))
+ return PTR_ERR(priv->scu);
return 0;
}
diff --git a/include/dt-bindings/clock/aspeed-clock.h b/include/dt-bindings/clock/aspeed-clock.h
index 4803abe9f62..e6599deeb9f 100644
--- a/include/dt-bindings/clock/aspeed-clock.h
+++ b/include/dt-bindings/clock/aspeed-clock.h
@@ -1,30 +1,42 @@
/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright 2016 Google Inc.
- */
-/* Core Clocks */
-#define PLL_HPLL 1
-#define PLL_DPLL 2
-#define PLL_D2PLL 3
-#define PLL_MPLL 4
-#define ARMCLK 5
-
-
-/* Bus Clocks, derived from core clocks */
-#define BCLK_PCLK 101
-#define BCLK_LHCLK 102
-#define BCLK_MACCLK 103
-#define BCLK_SDCLK 104
-#define BCLK_ARMCLK 105
-
-#define MCLK_DDR 201
-
-/* Special clocks */
-#define PCLK_UART1 501
-#define PCLK_UART2 502
-#define PCLK_UART3 503
-#define PCLK_UART4 504
-#define PCLK_UART5 505
-#define PCLK_MAC1 506
-#define PCLK_MAC2 507
+#define ASPEED_CLK_GATE_ECLK 0
+#define ASPEED_CLK_GATE_GCLK 1
+#define ASPEED_CLK_GATE_MCLK 2
+#define ASPEED_CLK_GATE_VCLK 3
+#define ASPEED_CLK_GATE_BCLK 4
+#define ASPEED_CLK_GATE_DCLK 5
+#define ASPEED_CLK_GATE_REFCLK 6
+#define ASPEED_CLK_GATE_USBPORT2CLK 7
+#define ASPEED_CLK_GATE_LCLK 8
+#define ASPEED_CLK_GATE_USBUHCICLK 9
+#define ASPEED_CLK_GATE_D1CLK 10
+#define ASPEED_CLK_GATE_YCLK 11
+#define ASPEED_CLK_GATE_USBPORT1CLK 12
+#define ASPEED_CLK_GATE_UART1CLK 13
+#define ASPEED_CLK_GATE_UART2CLK 14
+#define ASPEED_CLK_GATE_UART5CLK 15
+#define ASPEED_CLK_GATE_ESPICLK 16
+#define ASPEED_CLK_GATE_MAC1CLK 17
+#define ASPEED_CLK_GATE_MAC2CLK 18
+#define ASPEED_CLK_GATE_RSACLK 19
+#define ASPEED_CLK_GATE_UART3CLK 20
+#define ASPEED_CLK_GATE_UART4CLK 21
+#define ASPEED_CLK_GATE_SDCLK 22
+#define ASPEED_CLK_GATE_LHCCLK 23
+#define ASPEED_CLK_HPLL 24
+#define ASPEED_CLK_AHB 25
+#define ASPEED_CLK_APB 26
+#define ASPEED_CLK_UART 27
+#define ASPEED_CLK_SDIO 28
+#define ASPEED_CLK_ECLK 29
+#define ASPEED_CLK_ECLK_MUX 30
+#define ASPEED_CLK_LHCLK 31
+#define ASPEED_CLK_MAC 32
+#define ASPEED_CLK_BCLK 33
+#define ASPEED_CLK_MPLL 34
+#define ASPEED_CLK_24M 35
+#define ASPEED_CLK_MAC1RCLK 36
+#define ASPEED_CLK_MAC2RCLK 37
+#define ASPEED_CLK_DPLL 38
+#define ASPEED_CLK_D2PLL 39
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-21 04:42:27 +0000