diff options
| -rw-r--r-- | arch/arm/Kconfig | 14 | ||||
| -rw-r--r-- | arch/arm/dts/hi3798cv200-u-boot.dtsi | 29 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-hi3798cv200/dwmmc.h | 13 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h | 50 | ||||
| -rw-r--r-- | board/hisilicon/poplar/Kconfig | 15 | ||||
| -rw-r--r-- | board/hisilicon/poplar/MAINTAINERS | 6 | ||||
| -rw-r--r-- | board/hisilicon/poplar/Makefile | 7 | ||||
| -rw-r--r-- | board/hisilicon/poplar/README | 288 | ||||
| -rw-r--r-- | board/hisilicon/poplar/poplar.c | 174 | ||||
| -rw-r--r-- | configs/poplar_defconfig | 26 | ||||
| -rw-r--r-- | include/configs/poplar.h | 86 |
11 files changed, 708 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 3c3f5f7d05d..5f2048bd203 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -837,6 +837,19 @@ config TARGET_HIKEY Support for HiKey 96boards platform. It features a HI6220 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM. +config TARGET_POPLAR + bool "Support Poplar 96boards Enterprise Edition Platform" + select ARM64 + select DM + select OF_CONTROL + select DM_SERIAL + select DM_USB + help + Support for Poplar 96boards EE platform. It features a HI3798cv200 + SoC, with 4xA53 CPU, 1GB RAM and the high performance Mali T720 GPU + making it capable of running any commercial set-top solution based on + Linux or Android. + config TARGET_LS1012AQDS bool "Support ls1012aqds" select ARCH_LS1012A @@ -1165,6 +1178,7 @@ source "board/grinn/chiliboard/Kconfig" source "board/gumstix/pepper/Kconfig" source "board/h2200/Kconfig" source "board/hisilicon/hikey/Kconfig" +source "board/hisilicon/poplar/Kconfig" source "board/imx31_phycore/Kconfig" source "board/isee/igep003x/Kconfig" source "board/olimex/mx23_olinuxino/Kconfig" diff --git a/arch/arm/dts/hi3798cv200-u-boot.dtsi b/arch/arm/dts/hi3798cv200-u-boot.dtsi new file mode 100644 index 00000000000..2b3713b8fa0 --- /dev/null +++ b/arch/arm/dts/hi3798cv200-u-boot.dtsi @@ -0,0 +1,29 @@ +/* + * U-Boot addition to: + * 1) use platform data for the console + * 2) provide support for the generic-ehci USB driver currently not available + * in the linux kernel (8/May/2017). + * + * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +&soc { + usb2: ehci@9890000 { + compatible = "generic-ehci"; + reg = <0x9890000 0x100>; + status = "okay"; + }; +}; + +&uart0 { + status = "disabled"; +}; + +/{ + chosen { + stdout-path = ""; + }; +}; + diff --git a/arch/arm/include/asm/arch-hi3798cv200/dwmmc.h b/arch/arm/include/asm/arch-hi3798cv200/dwmmc.h new file mode 100644 index 00000000000..1060d94c91d --- /dev/null +++ b/arch/arm/include/asm/arch-hi3798cv200/dwmmc.h @@ -0,0 +1,13 @@ +/* + * (C) Copyright 2017 Linaro + * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _HI3798cv200_DWMMC_H_ +#define _HI3798cv200_DWMMC_H_ + +int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width); + +#endif /* _HI3798cv200_DWMMC_H_ */ diff --git a/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h new file mode 100644 index 00000000000..d30e0b4ca10 --- /dev/null +++ b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h @@ -0,0 +1,50 @@ +/* + * (C) Copyright 2017 Linaro + * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __HI3798cv200_H__ +#define __HI3798cv200_H__ + +#define REG_BASE_PERI_CTRL 0xF8A20000 +#define REG_BASE_CRG 0xF8A22000 + +/* DEVICES */ +#define REG_BASE_MCI 0xF9830000 +#define REG_BASE_UART0 0xF8B00000 + +/* PERI control registers (4KB) */ + /* USB2 PHY01 configuration register */ +#define PERI_CTRL_USB0 (REG_BASE_PERI_CTRL + 0x120) + +/* PERI CRG registers (4KB) */ + /* USB2 CTRL0 clock and soft reset */ +#define PERI_CRG46 (REG_BASE_CRG + 0xb8) +#define USB2_BUS_CKEN (1<<0) +#define USB2_OHCI48M_CKEN (1<<1) +#define USB2_OHCI12M_CKEN (1<<2) +#define USB2_OTG_UTMI_CKEN (1<<3) +#define USB2_HST_PHY_CKEN (1<<4) +#define USB2_UTMI0_CKEN (1<<5) +#define USB2_BUS_SRST_REQ (1<<12) +#define USB2_UTMI0_SRST_REQ (1<<13) +#define USB2_HST_PHY_SYST_REQ (1<<16) +#define USB2_OTG_PHY_SYST_REQ (1<<17) +#define USB2_CLK48_SEL (1<<20) + + /* USB2 PHY clock and soft reset */ +#define PERI_CRG47 (REG_BASE_CRG + 0xbc) +#define USB2_PHY01_REF_CKEN (1 << 0) +#define USB2_PHY2_REF_CKEN (1 << 2) +#define USB2_PHY01_SRST_REQ (1 << 4) +#define USB2_PHY2_SRST_REQ (1 << 6) +#define USB2_PHY01_SRST_TREQ0 (1 << 8) +#define USB2_PHY01_SRST_TREQ1 (1 << 9) +#define USB2_PHY2_SRST_TREQ (1 << 10) +#define USB2_PHY01_REFCLK_SEL (1 << 12) +#define USB2_PHY2_REFCLK_SEL (1 << 14) + + +#endif diff --git a/board/hisilicon/poplar/Kconfig b/board/hisilicon/poplar/Kconfig new file mode 100644 index 00000000000..339729544e1 --- /dev/null +++ b/board/hisilicon/poplar/Kconfig @@ -0,0 +1,15 @@ +if TARGET_POPLAR + +config SYS_BOARD + default "poplar" + +config SYS_VENDOR + default "hisilicon" + +config SYS_SOC + default "hi3798cv200" + +config SYS_CONFIG_NAME + default "poplar" + +endif diff --git a/board/hisilicon/poplar/MAINTAINERS b/board/hisilicon/poplar/MAINTAINERS new file mode 100644 index 00000000000..0cc01c8321e --- /dev/null +++ b/board/hisilicon/poplar/MAINTAINERS @@ -0,0 +1,6 @@ +Poplar BOARD +M: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> +S: Maintained +F: board/hisilicon/poplar +F: include/configs/poplar.h +F: configs/poplar_defconfig diff --git a/board/hisilicon/poplar/Makefile b/board/hisilicon/poplar/Makefile new file mode 100644 index 00000000000..101545d2122 --- /dev/null +++ b/board/hisilicon/poplar/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2017 Linaro +# Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> +# +# SPDX-License-Identifier: GPL-2.0+ +# +obj-y := poplar.o diff --git a/board/hisilicon/poplar/README b/board/hisilicon/poplar/README new file mode 100644 index 00000000000..99ed6ce295e --- /dev/null +++ b/board/hisilicon/poplar/README @@ -0,0 +1,288 @@ +================================================================================ + Board Information +================================================================================ + +Developed by HiSilicon, the board features the Hi3798C V200 with an +integrated quad-core 64-bit ARM Cortex A53 processor and high +performance Mali T720 GPU, making it capable of running any commercial +set-top solution based on Linux or Android. Its high performance +specification also supports a premium user experience with up to H.265 +HEVC decoding of 4K video at 60 frames per second. + +SOC Hisilicon Hi3798CV200 +CPU Quad-core ARM Cortex-A53 64 bit +DRAM DDR3/3L/4 SDRAM interface, maximum 32-bit data width 2 GB +USB Two USB 2.0 ports One USB 3.0 ports +CONSOLE USB-micro port for console support +ETHERNET 1 GBe Ethernet +PCIE One PCIe 2.0 interfaces +JTAG 8-Pin JTAG +EXPANSION INTERFACE Linaro 96Boards Low Speed Expansion slot +DIMENSION Standard 160×120 mm 96Boards Enterprice Edition form factor +WIFI 802.11AC 2*2 with Bluetooth +CONNECTORS One connector for Smart Card One connector for TSI + + +================================================================================ + BUILD INSTRUCTIONS +================================================================================ + +Note of warning: +================ + +U-boot has a *strong* dependency with the l-loader and the arm trusted firmware +repositories. + +The boot sequence is: + l-loader --> arm_trusted_firmware --> u-boot + +U-Boot needs to be aware of the BL31 runtime location and size to avoid writing +over it. Currently, BL31 is being placed below the kernel text offset (check +poplar.c) but this could change in the future. + +The current version of u-boot has been tested with: + - https://github.com/Linaro/poplar-l-loader.git + + commit f0988698dcc5c08bd0a8f50aa0457e138a5f438c + Author: Alex Elder <elder@linaro.org> + Date: Fri Jun 16 08:57:59 2017 -0500 + + l-loader: use external memory region definitions + + The ARM Trusted Firmware code now has a header file that collects + all the definitions for the memory regions used for its boot stages. + Include that file where needed, and use the definitions found therein + + Signed-off-by: Alex Elder <elder@linaro.org> + + + - https://github.com/Linaro/poplar-arm-trusted-firmware.git + + commit 6ac42dd3be13c99aa8ce29a15073e2f19d935f68 + Author: Alex Elder <elder@linaro.org> + Date: Fri Jun 16 09:24:50 2017 -0500 + + poplar: define memory regions in a separate file + + Separate the definitions for memory regions used for the BL stage + images and FIP into a new file. The "l-loader" image uses knowledge + of the sizes and locations of these memory regions, and it can now + include this (external) header to get these definitions, rather than + having to make coordinated changes to both code bases. + + The new file has a complete set of definitions (more than may be + required by one or the other user). It also includes a summary of + how the boot process works, and how it uses these regions. + + It should now be relatively easy to adjust the sizes and locations + of these memory regions, or to add to them (e.g. for TEE). + + Signed-off-by: Alex Elder <elder@linaro.org> + + +Compile from source: +==================== + +Get all the sources + + > mkdir -p ~/poplar/src ~/poplar/bin + > cd ~/poplar/src + > git clone https://github.com/Linaro/poplar-l-loader.git l-loader + > git clone https://github.com/Linaro/poplar-arm-trusted-firmware.git atf + > git clone https://github.com/Linaro/poplar-u-boot.git u-boot + +Make sure you are using the correct branch on each one of these repositories. +The definition of "correct" might change over time (at this moment in time this +would be the "latest" branch). + +Compile U-Boot: +=============== + + Prerequisite: + # sudo apt-get install device-tree-compiler + + > cd ~/poplar/src/u-boot + > make CROSS_COMPILE=aarch64-linux-gnu- poplar_defconfig + > make CROSS_COMPILE=aarch64-linux-gnu- + > cp u-boot.bin ~/poplar/bin + +Compile ARM Trusted Firmware (ATF): +=================================== + + > cd ~/poplar/src/atf + > make CROSS_COMPILE=aarch64-linux-gnu- all fip \ + SPD=none BL33=~/poplar/bin/u-boot.bin DEBUG=1 PLAT=poplar + +Copy resulting binaries + > cp build/hi3798cv200/debug/bl1.bin ~/poplar/src/l-loader/atf/ + > cp build/hi3798cv200/debug/fip.bin ~/poplar/src/l-loader/atf/ + +Compile l-loader: +================= + + > cd ~/poplar/src/l-loader + > make clean + > make CROSS_COMPILE=arm-linux-gnueabi- + + Due to BootROM requiremets, rename l-loader.bin to fastboot.bin: + > cp l-loader.bin ~/poplar/bin/fastboot.bin + + +================================================================================ + FLASH INSTRUCTIONS +================================================================================ + +Two methods: + +Using USB debrick support: + Copy fastboot.bin to a FAT partition on the USB drive and reboot the + poplar board while pressing S3(usb_boot). + + The system will execute the new u-boot and boot into a shell which you + can then use to write to eMMC. + +Using U-BOOT from shell: + 1) using AXIS usb ethernet dongle and tftp + 2) using FAT formated USB drive + + +1. TFTP (USB ethernet dongle) +============================= + +Plug a USB AXIS ethernet dongle on any of the USB2 ports on the Poplar board. +Copy fastboot.bin to your tftp server. +In u-boot make sure your network is properly setup. + +Then + +=> tftp 0x30000000 fastboot.bin +starting USB... +USB0: USB EHCI 1.00 +scanning bus 0 for devices... 1 USB Device(s) found +USB1: USB EHCI 1.00 +scanning bus 1 for devices... 3 USB Device(s) found + scanning usb for storage devices... 0 Storage Device(s) found + scanning usb for ethernet devices... 1 Ethernet Device(s) found +Waiting for Ethernet connection... done. +Using asx0 device +TFTP from server 192.168.1.4; our IP address is 192.168.1.10 +Filename 'poplar/fastboot.bin'. +Load address: 0x30000000 +Loading: ################################################################# + ################################################################# + ############################################################### + 2 MiB/s +done +Bytes transferred = 983040 (f0000 hex) + +=> mmc write 0x30000000 0 0x780 + +MMC write: dev # 0, block # 0, count 1920 ... 1920 blocks written: OK +=> reset + + +2. USING USB FAT DRIVE +======================= + +Copy fastboot.bin to any partition on a FAT32 formated usb flash drive. +Enter the uboot prompt + +=> fatls usb 0:2 + 983040 fastboot.bin + +1 file(s), 0 dir(s) + +=> fatload usb 0:2 0x30000000 fastboot.bin +reading fastboot.bin +983040 bytes read in 44 ms (21.3 MiB/s) + +=> mmc write 0x30000000 0 0x780 + +MMC write: dev # 0, block # 0, count 1920 ... 1920 blocks written: OK + + +================================================================================ + BOOT TRACE +================================================================================ + +Bootrom start +Boot Media: eMMC +Decrypt auxiliary code ...OK + +lsadc voltage min: 000000FE, max: 000000FF, aver: 000000FE, index: 00000000 + +Entry boot auxiliary code + +Auxiliary code - v1.00 +DDR code - V1.1.2 20160205 +Build: Mar 24 2016 - 17:09:44 +Reg Version: v134 +Reg Time: 2016/03/18 09:44:55 +Reg Name: hi3798cv2dmb_hi3798cv200_ddr3_2gbyte_8bitx4_4layers.reg + +Boot auxiliary code success +Bootrom success + +LOADER: Switched to aarch64 mode +LOADER: Entering ARM TRUSTED FIRMWARE +LOADER: CPU0 executes at 0x000ce000 + +INFO: BL1: 0xe1000 - 0xe7000 [size = 24576] +NOTICE: Booting Trusted Firmware +NOTICE: BL1: v1.3(debug):v1.3-372-g1ba9c60 +NOTICE: BL1: Built : 17:51:33, Apr 30 2017 +INFO: BL1: RAM 0xe1000 - 0xe7000 +INFO: BL1: Loading BL2 +INFO: Loading image id=1 at address 0xe9000 +INFO: Image id=1 loaded at address 0xe9000, size = 0x5008 +NOTICE: BL1: Booting BL2 +INFO: Entry point address = 0xe9000 +INFO: SPSR = 0x3c5 +NOTICE: BL2: v1.3(debug):v1.3-372-g1ba9c60 +NOTICE: BL2: Built : 17:51:33, Apr 30 2017 +INFO: BL2: Loading BL31 +INFO: Loading image id=3 at address 0x129000 +INFO: Image id=3 loaded at address 0x129000, size = 0x8038 +INFO: BL2: Loading BL33 +INFO: Loading image id=5 at address 0x37000000 +INFO: Image id=5 loaded at address 0x37000000, size = 0x58f17 +NOTICE: BL1: Booting BL31 +INFO: Entry point address = 0x129000 +INFO: SPSR = 0x3cd +INFO: Boot bl33 from 0x37000000 for 364311 Bytes +NOTICE: BL31: v1.3(debug):v1.3-372-g1ba9c60 +NOTICE: BL31: Built : 17:51:33, Apr 30 2017 +INFO: BL31: Initializing runtime services +INFO: BL31: Preparing for EL3 exit to normal world +INFO: Entry point address = 0x37000000 +INFO: SPSR = 0x3c9 + + +U-Boot 2017.05-rc2-00130-gd2255b0 (Apr 30 2017 - 17:51:28 +0200)poplar + +Model: HiSilicon Poplar Development Board +BOARD: Hisilicon HI3798cv200 Poplar +DRAM: 1 GiB +MMC: Hisilicon DWMMC: 0 +In: serial@f8b00000 +Out: serial@f8b00000 +Err: serial@f8b00000 +Net: Net Initialization Skipped +No ethernet found. + +Hit any key to stop autoboot: 0 +starting USB... +USB0: USB EHCI 1.00 +scanning bus 0 for devices... 1 USB Device(s) found +USB1: USB EHCI 1.00 +scanning bus 1 for devices... 4 USB Device(s) found + scanning usb for storage devices... 1 Storage Device(s) found + scanning usb for ethernet devices... 1 Ethernet Device(s) found + +USB device 0: + Device 0: Vendor: SanDisk Rev: 1.00 Prod: Cruzer Blade + Type: Removable Hard Disk + Capacity: 7632.0 MB = 7.4 GB (15630336 x 512) +... is now current device +Scanning usb 0:1... +=> diff --git a/board/hisilicon/poplar/poplar.c b/board/hisilicon/poplar/poplar.c new file mode 100644 index 00000000000..d542f6857b1 --- /dev/null +++ b/board/hisilicon/poplar/poplar.c @@ -0,0 +1,174 @@ +/* + * (C) Copyright 2017 Linaro + * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <dm.h> +#include <common.h> +#include <asm/io.h> +#include <dm/platform_data/serial_pl01x.h> +#include <asm/arch/hi3798cv200.h> +#include <asm/arch/dwmmc.h> +#include <asm/armv8/mmu.h> + +DECLARE_GLOBAL_DATA_PTR; + +static struct mm_region poplar_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + 0, + } +}; + +struct mm_region *mem_map = poplar_mem_map; + +static const struct pl01x_serial_platdata serial_platdata = { + .base = REG_BASE_UART0, + .type = TYPE_PL010, + .clock = 75000000, +}; + +U_BOOT_DEVICE(poplar_serial) = { + .name = "serial_pl01x", + .platdata = &serial_platdata, +}; + +int checkboard(void) +{ + puts("BOARD: Hisilicon HI3798cv200 Poplar\n"); + + return 0; +} + +void reset_cpu(ulong addr) +{ + psci_system_reset(); +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size(NULL, 0x80000000); + + return 0; +} + +/* + * Some linux kernel versions don't use memory before its load address, so to + * be generic we just pretend it isn't there. In previous uboot versions we + * carved the space used by BL31 (runs in DDR on this platfomr) so the PSCI code + * could persist in memory and be left alone by the kernel. + * + * That led to a problem when mapping memory in older kernels. That PSCI code + * now lies in memory below the kernel load offset; it therefore won't be + * touched by the kernel, and by not specially reserving it we avoid the mapping + * problem as well. + * + */ +#define KERNEL_TEXT_OFFSET 0x00080000 + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = KERNEL_TEXT_OFFSET; + gd->bd->bi_dram[0].size = gd->ram_size - gd->bd->bi_dram[0].start; + + return 0; +} + +static void usb2_phy_config(void) +{ + const u32 config[] = { + /* close EOP pre-emphasis. open data pre-emphasis */ + 0xa1001c, + /* Rcomp = 150mW, increase DC level */ + 0xa00607, + /* keep Rcomp working */ + 0xa10700, + /* Icomp = 212mW, increase current drive */ + 0xa00aab, + /* EMI fix: rx_active not stay 1 when error packets received */ + 0xa11140, + /* Comp mode select */ + 0xa11041, + /* adjust eye diagram */ + 0xa0098c, + /* adjust eye diagram */ + 0xa10a0a, + }; + int i; + + for (i = 0; i < ARRAY_SIZE(config); i++) { + writel(config[i], PERI_CTRL_USB0); + clrsetbits_le32(PERI_CTRL_USB0, BIT(21), BIT(20) | BIT(22)); + udelay(20); + } +} + +static void usb2_phy_init(void) +{ + /* reset usb2 controller bus/utmi/roothub */ + setbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ | + USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ); + udelay(200); + + /* reset usb2 phy por/utmi */ + setbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ | USB2_PHY01_SRST_TREQ1); + udelay(200); + + /* open usb2 ref clk */ + setbits_le32(PERI_CRG47, USB2_PHY01_REF_CKEN); + udelay(300); + + /* cancel usb2 power on reset */ + clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_REQ); + udelay(500); + + usb2_phy_config(); + + /* cancel usb2 port reset, wait comp circuit stable */ + clrbits_le32(PERI_CRG47, USB2_PHY01_SRST_TREQ1); + mdelay(10); + + /* open usb2 controller clk */ + setbits_le32(PERI_CRG46, USB2_BUS_CKEN | USB2_OHCI48M_CKEN | + USB2_OHCI12M_CKEN | USB2_OTG_UTMI_CKEN | + USB2_HST_PHY_CKEN | USB2_UTMI0_CKEN); + udelay(200); + + /* cancel usb2 control reset */ + clrbits_le32(PERI_CRG46, USB2_BUS_SRST_REQ | USB2_UTMI0_SRST_REQ | + USB2_HST_PHY_SYST_REQ | USB2_OTG_PHY_SYST_REQ); + udelay(200); +} + +int board_mmc_init(bd_t *bis) +{ + int ret; + + ret = hi6220_dwmci_add_port(0, REG_BASE_MCI, 8); + if (ret) + printf("mmc init error (%d)\n", ret); + + return ret; +} + +int board_init(void) +{ + usb2_phy_init(); + + return 0; +} + diff --git a/configs/poplar_defconfig b/configs/poplar_defconfig new file mode 100644 index 00000000000..8f9f40f64d9 --- /dev/null +++ b/configs/poplar_defconfig @@ -0,0 +1,26 @@ +CONFIG_ARM=y +CONFIG_TARGET_POPLAR=y +CONFIG_IDENT_STRING="poplar" +CONFIG_DEFAULT_DEVICE_TREE="hi3798cv200-poplar" +CONFIG_SYS_PROMPT="poplar# " +CONFIG_DISTRO_DEFAULTS=y +CONFIG_DISPLAY_CPUINFO=n +CONFIG_DISPLAY_BOARDINFO=y +CONFIG_ISO_PARTITION=n +CONFIG_MMC_DW=y +CONFIG_MMC_DW_K3=y +CONFIG_PL011_SERIAL=y +CONFIG_PSCI_RESET=y +CONFIG_USB=y +CONFIG_USB_EHCI=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_GENERIC=y +CONFIG_USB_STORAGE=y +CONFIG_NET=y +# CONFIG_CMD_IMLS is not set +# CONFIG_DM_GPIO is not set +CONFIG_LIB_RAND=y +CONFIG_CMD_UNZIP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y + diff --git a/include/configs/poplar.h b/include/configs/poplar.h new file mode 100644 index 00000000000..55e05d6ca56 --- /dev/null +++ b/include/configs/poplar.h @@ -0,0 +1,86 @@ +/* + * (C) Copyright 2017 Linaro + * + * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> + * + * Configuration for Poplar 96boards CE. Parts were derived from other ARM + * configurations. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _POPLAR_H_ +#define _POPLAR_H_ + +#include <linux/sizes.h> + +/* DRAM banks */ +#define CONFIG_NR_DRAM_BANKS 2 + +/* SYS */ +#define CONFIG_SYS_BOOTM_LEN 0x1400000 +#define CONFIG_SYS_INIT_SP_ADDR 0x200000 +#define CONFIG_SYS_LOAD_ADDR 0x800000 +#define CONFIG_SYS_MALLOC_LEN SZ_32M + +/* ATF bl33.bin load address (must match) */ +#define CONFIG_SYS_TEXT_BASE 0x37000000 + +/* PL010/PL011 */ +#define CONFIG_PL01X_SERIAL + +/* USB configuration */ +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_SYS_USB_EVENT_POLL +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* SD/MMC */ +#define CONFIG_BOUNCE_BUFFER + +/***************************************************************************** + * Initial environment variables + *****************************************************************************/ + +#define BOOT_TARGET_DEVICES(func) \ + func(USB, usb, 0) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) +#ifndef CONFIG_SPL_BUILD +#include <config_distro_defaults.h> +#include <config_distro_bootcmd.h> +#endif + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loader_mmc_blknum=0x0\0" \ + "loader_mmc_nblks=0x780\0" \ + "env_mmc_blknum=0x780\0" \ + "env_mmc_nblks=0x80\0" \ + "kernel_addr_r=0x30000000\0" \ + "pxefile_addr_r=0x32000000\0" \ + "scriptaddr=0x32000000\0" \ + "fdt_addr_r=0x32200000\0" \ + "fdtfile=hisilicon/hi3798cv200-poplar.dtb\0" \ + "ramdisk_addr_r=0x32400000\0" \ + BOOTENV + + +/* Command line configuration */ +#define CONFIG_ENV_IS_IN_MMC 1 +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_OFFSET (0x780 * 512) /* env_mmc_blknum */ +#define CONFIG_ENV_SIZE 0x10000 /* env_mmc_nblks bytes */ +#define CONFIG_FAT_WRITE +#define CONFIG_ENV_VARS_UBOOT_CONFIG + +/* Monitor Command Prompt */ +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#endif /* _POPLAR_H_ */ |