diff options
| -rw-r--r-- | arch/x86/cpu/baytrail/cpu.c | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c index b1faf8ca326..2837709d6d1 100644 --- a/arch/x86/cpu/baytrail/cpu.c +++ b/arch/x86/cpu/baytrail/cpu.c @@ -9,12 +9,60 @@ #include <common.h> #include <cpu.h> #include <dm.h> +#include <pci.h> #include <asm/cpu.h> #include <asm/cpu_x86.h> +#include <asm/io.h> #include <asm/lapic.h> #include <asm/msr.h> #include <asm/turbo.h> +#define BYT_PRV_CLK 0x800 +#define BYT_PRV_CLK_EN (1 << 0) +#define BYT_PRV_CLK_M_VAL_SHIFT 1 +#define BYT_PRV_CLK_N_VAL_SHIFT 16 +#define BYT_PRV_CLK_UPDATE (1 << 31) + +static void hsuart_clock_set(void *base) +{ + u32 m, n, reg; + + /* + * Configure the BayTrail UART clock for the internal HS UARTs + * (PCI devices) to 58982400 Hz + */ + m = 0x2400; + n = 0x3d09; + reg = (m << BYT_PRV_CLK_M_VAL_SHIFT) | (n << BYT_PRV_CLK_N_VAL_SHIFT); + writel(reg, base + BYT_PRV_CLK); + reg |= BYT_PRV_CLK_EN | BYT_PRV_CLK_UPDATE; + writel(reg, base + BYT_PRV_CLK); +} + +/* + * Configure the internal clock of both SIO HS-UARTs, if they are enabled + * via FSP + */ +int arch_cpu_init_dm(void) +{ + struct udevice *dev; + void *base; + int ret; + int i; + + /* Loop over the 2 HS-UARTs */ + for (i = 0; i < 2; i++) { + ret = dm_pci_bus_find_bdf(PCI_BDF(0, 0x1e, 3 + i), &dev); + if (!ret) { + base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, + PCI_REGION_MEM); + hsuart_clock_set(base); + } + } + + return 0; +} + static void set_max_freq(void) { msr_t perf_ctl; |