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-rw-r--r--arch/powerpc/cpu/ppc4xx/Kconfig4
-rw-r--r--board/esd/hub405/Kconfig12
-rw-r--r--board/esd/hub405/MAINTAINERS6
-rw-r--r--board/esd/hub405/Makefile10
-rw-r--r--board/esd/hub405/flash.c85
-rw-r--r--board/esd/hub405/hub405.c208
-rw-r--r--configs/HUB405_defconfig3
-rw-r--r--doc/README.scrapyard1
-rw-r--r--include/configs/HUB405.h351
9 files changed, 1 insertions, 679 deletions
diff --git a/arch/powerpc/cpu/ppc4xx/Kconfig b/arch/powerpc/cpu/ppc4xx/Kconfig
index 8ce66d67df5..cab8f25f9be 100644
--- a/arch/powerpc/cpu/ppc4xx/Kconfig
+++ b/arch/powerpc/cpu/ppc4xx/Kconfig
@@ -125,9 +125,6 @@ config TARGET_CPCI405AB
config TARGET_CPCI405DT
bool "Support CPCI405DT"
-config TARGET_HUB405
- bool "Support HUB405"
-
config TARGET_OCRTC
bool "Support OCRTC"
@@ -232,7 +229,6 @@ source "board/csb472/Kconfig"
source "board/dave/PPChameleonEVB/Kconfig"
source "board/esd/cpci2dp/Kconfig"
source "board/esd/cpci405/Kconfig"
-source "board/esd/hub405/Kconfig"
source "board/esd/ocrtc/Kconfig"
source "board/esd/pci405/Kconfig"
source "board/esd/plu405/Kconfig"
diff --git a/board/esd/hub405/Kconfig b/board/esd/hub405/Kconfig
deleted file mode 100644
index 2b9556a195e..00000000000
--- a/board/esd/hub405/Kconfig
+++ /dev/null
@@ -1,12 +0,0 @@
-if TARGET_HUB405
-
-config SYS_BOARD
- default "hub405"
-
-config SYS_VENDOR
- default "esd"
-
-config SYS_CONFIG_NAME
- default "HUB405"
-
-endif
diff --git a/board/esd/hub405/MAINTAINERS b/board/esd/hub405/MAINTAINERS
deleted file mode 100644
index e84a1d95f25..00000000000
--- a/board/esd/hub405/MAINTAINERS
+++ /dev/null
@@ -1,6 +0,0 @@
-HUB405 BOARD
-M: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
-S: Maintained
-F: board/esd/hub405/
-F: include/configs/HUB405.h
-F: configs/HUB405_defconfig
diff --git a/board/esd/hub405/Makefile b/board/esd/hub405/Makefile
deleted file mode 100644
index 99e18b567fd..00000000000
--- a/board/esd/hub405/Makefile
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier: GPL-2.0+
-#
-
-obj-y = hub405.o flash.o \
- ../common/misc.o \
- ../common/esd405ep_nand.o \
diff --git a/board/esd/hub405/flash.c b/board/esd/hub405/flash.c
deleted file mode 100644
index 23e81642e02..00000000000
--- a/board/esd/hub405/flash.c
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * (C) Copyright 2001
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/ppc4xx.h>
-#include <asm/processor.h>
-
-/*
- * include common flash code (for esd boards)
- */
-#include "../common/flash.c"
-
-/*-----------------------------------------------------------------------
- * Functions
- */
-static ulong flash_get_size (vu_long * addr, flash_info_t * info);
-static void flash_get_offsets (ulong base, flash_info_t * info);
-
-/*-----------------------------------------------------------------------
- */
-
-unsigned long flash_init (void)
-{
- unsigned long size_b0;
- int i;
- uint pbcr;
- unsigned long base_b0;
- int size_val = 0;
-
- /* Init: no FLASHes known */
- for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
- flash_info[i].flash_id = FLASH_UNKNOWN;
- }
-
- /* Static FLASH Bank configuration here - FIXME XXX */
-
- size_b0 = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
-
- if (flash_info[0].flash_id == FLASH_UNKNOWN) {
- printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
- size_b0, size_b0<<20);
- }
-
- /* Setup offsets */
- flash_get_offsets (-size_b0, &flash_info[0]);
-
- /* Re-do sizing to get full correct info */
- mtdcr(EBC0_CFGADDR, PB0CR);
- pbcr = mfdcr(EBC0_CFGDATA);
- mtdcr(EBC0_CFGADDR, PB0CR);
- base_b0 = -size_b0;
- switch (size_b0) {
- case 1 << 20:
- size_val = 0;
- break;
- case 2 << 20:
- size_val = 1;
- break;
- case 4 << 20:
- size_val = 2;
- break;
- case 8 << 20:
- size_val = 3;
- break;
- case 16 << 20:
- size_val = 4;
- break;
- }
- pbcr = (pbcr & 0x0001ffff) | base_b0 | (size_val << 17);
- mtdcr(EBC0_CFGDATA, pbcr);
-
- /* Monitor protection ON by default */
- (void)flash_protect(FLAG_PROTECT_SET,
- -CONFIG_SYS_MONITOR_LEN,
- 0xffffffff,
- &flash_info[0]);
-
- flash_info[0].size = size_b0;
-
- return (size_b0);
-}
diff --git a/board/esd/hub405/hub405.c b/board/esd/hub405/hub405.c
deleted file mode 100644
index 14237443fa5..00000000000
--- a/board/esd/hub405/hub405.c
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <asm/processor.h>
-#include <asm/io.h>
-#include <command.h>
-#include <malloc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-extern void lxt971_no_sleep(void);
-
-int board_revision(void)
-{
- unsigned long osrl_reg;
- unsigned long isr1l_reg;
- unsigned long tcr_reg;
- unsigned long value;
-
- /*
- * Get version of HUB405 board from GPIO's
- */
-
- /*
- * Setup GPIO pin(s) (IRQ6/GPIO23)
- */
- osrl_reg = in_be32((void *)GPIO0_OSRH);
- isr1l_reg = in_be32((void *)GPIO0_ISR1H);
- tcr_reg = in_be32((void *)GPIO0_TCR);
- out_be32((void *)GPIO0_OSRH, osrl_reg & ~0x00030000); /* output select */
- out_be32((void *)GPIO0_ISR1H, isr1l_reg | 0x00030000); /* input select */
- out_be32((void *)GPIO0_TCR, tcr_reg & ~0x00000100); /* select input */
-
- udelay(1000); /* wait some time before reading input */
- value = in_be32((void *)GPIO0_IR) & 0x00000100; /* get config bits */
-
- /*
- * Restore GPIO settings
- */
- out_be32((void *)GPIO0_OSRH, osrl_reg); /* output select */
- out_be32((void *)GPIO0_ISR1H, isr1l_reg); /* input select */
- out_be32((void *)GPIO0_TCR, tcr_reg); /* enable output driver for outputs */
-
- if (value & 0x00000100) {
- /* Revision 1.1 or 1.2 detected */
- return 1;
- }
-
- /* Revision 1.0 */
- return 0;
-}
-
-
-int board_early_init_f (void)
-{
- /*
- * IRQ 0-15 405GP internally generated; active high; level sensitive
- * IRQ 16 405GP internally generated; active low; level sensitive
- * IRQ 17-24 RESERVED
- * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
- * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
- * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
- * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
- * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
- * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
- * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
- */
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
- mtdcr(UIC0ER, 0x00000000); /* disable all ints */
- mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
- mtdcr(UIC0PR, 0xFFFFFF9F); /* set int polarities */
- mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
- mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
- mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
-
- /*
- * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
- */
- mtebc (EBC0_CFG, 0xa8400000); /* ebc always driven */
-
- return 0;
-}
-
-#define LED_REG (DUART0_BA + 0x20)
-int misc_init_r (void)
-{
- unsigned long val;
- int delay, flashcnt;
- char *str;
- char hw_rev[4];
-
- /*
- * Enable interrupts in exar duart mcr[3]
- */
- out_8((void *)(DUART0_BA + 4), 0x08);
- out_8((void *)(DUART1_BA + 4), 0x08);
- out_8((void *)(DUART2_BA + 4), 0x08);
- out_8((void *)(DUART3_BA + 4), 0x08);
-
- /*
- * Set RS232/RS422 control (RS232 = high on GPIO)
- */
- val = in_be32((void *)GPIO0_OR);
- val &= ~(CONFIG_SYS_UART2_RS232 | CONFIG_SYS_UART3_RS232 |
- CONFIG_SYS_UART4_RS232 | CONFIG_SYS_UART5_RS232);
-
- str = getenv("phys0");
- if (!str || (str && (str[0] == '0')))
- val |= CONFIG_SYS_UART2_RS232;
-
- str = getenv("phys1");
- if (!str || (str && (str[0] == '0')))
- val |= CONFIG_SYS_UART3_RS232;
-
- str = getenv("phys2");
- if (!str || (str && (str[0] == '0')))
- val |= CONFIG_SYS_UART4_RS232;
-
- str = getenv("phys3");
- if (!str || (str && (str[0] == '0')))
- val |= CONFIG_SYS_UART5_RS232;
-
- out_be32((void *)GPIO0_OR, val);
-
- /*
- * check board type and setup AP power
- */
- str = getenv("bd_type"); /* this is only set on non prototype hardware */
- if (str != NULL) {
- if ((strcmp(str, "swch405") == 0) || ((!strcmp(str, "hub405") && (gd->board_type >= 1)))) {
- unsigned char led_reg_default = 0;
- str = getenv("ap_pwr");
- if (!str || (str && (str[0] == '1')))
- led_reg_default = 0x04 | 0x02 ; /* U2_LED | AP_PWR */
-
- /*
- * Flash LEDs
- */
- for (flashcnt = 0; flashcnt < 3; flashcnt++) {
- /* LED_A..D off */
- out_8((void *)LED_REG, led_reg_default);
- for (delay = 0; delay < 100; delay++)
- udelay(1000);
- /* LED_A..D on */
- out_8((void *)LED_REG, led_reg_default | 0xf0);
- for (delay = 0; delay < 50; delay++)
- udelay(1000);
- }
- out_8((void *)LED_REG, led_reg_default);
- }
- }
-
- /*
- * Reset external DUARTs
- */
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */
- udelay(10); /* wait 10us */
- out_be32((void *)GPIO0_OR,
- in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */
- udelay(1000); /* wait 1ms */
-
- /*
- * Store hardware revision in environment for further processing
- */
- sprintf(hw_rev, "1.%ld", gd->board_type);
- setenv("hw_rev", hw_rev);
- return (0);
-}
-
-
-/*
- * Check Board Identity:
- */
-int checkboard (void)
-{
- char str[64];
- int i = getenv_f("serial#", str, sizeof(str));
-
- puts ("Board: ");
-
- if (i == -1) {
- puts ("### No HW ID - assuming HUB405");
- } else {
- puts(str);
- }
-
- if (getenv_f("bd_type", str, sizeof(str)) != -1) {
- printf(" (%s", str);
- } else {
- puts(" (Missing bd_type!");
- }
-
- gd->board_type = board_revision();
- printf(", Rev 1.%ld)\n", gd->board_type);
-
- /*
- * Disable sleep mode in LXT971
- */
- lxt971_no_sleep();
-
- return 0;
-}
diff --git a/configs/HUB405_defconfig b/configs/HUB405_defconfig
deleted file mode 100644
index a39712e26f2..00000000000
--- a/configs/HUB405_defconfig
+++ /dev/null
@@ -1,3 +0,0 @@
-CONFIG_PPC=y
-CONFIG_4xx=y
-CONFIG_TARGET_HUB405=y
diff --git a/doc/README.scrapyard b/doc/README.scrapyard
index 1775987f55f..d8bb3aae607 100644
--- a/doc/README.scrapyard
+++ b/doc/README.scrapyard
@@ -12,6 +12,7 @@ The list should be sorted in reverse chronological order.
Board Arch CPU Commit Removed Last known maintainer/contact
=================================================================================================
+HUB405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs@esd.eu>
HH405 ppc4xx 405ep - - Matthias Fuchs <matthias.fuchs@esd.eu>
DU440 ppc4xx 440epx - - Matthias Fuchs <matthias.fuchs@esd.eu>
DU405 ppc4xx 405gpr - - Matthias Fuchs <matthias.fuchs@esd.eu>
diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h
deleted file mode 100644
index 1783b9ff15e..00000000000
--- a/include/configs/HUB405.h
+++ /dev/null
@@ -1,351 +0,0 @@
-/*
- * (C) Copyright 2001-2003
- * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-/*
- * board/config.h - configuration options, board specific
- */
-
-#ifndef __CONFIG_H
-#define __CONFIG_H
-
-/*
- * High Level Configuration Options
- * (easy to change)
- */
-
-#define CONFIG_405EP 1 /* This is a PPC405 CPU */
-#define CONFIG_HUB405 1 /* ...on a HUB405 board */
-
-#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
-
-#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
-#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
-
-#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
-
-#define CONFIG_BOARD_TYPES 1 /* support board types */
-
-#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
-
-#undef CONFIG_BOOTARGS
-#undef CONFIG_BOOTCOMMAND
-
-#define CONFIG_PREBOOT /* enable preboot variable */
-
-#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
-
-#define CONFIG_PPC4xx_EMAC
-#define CONFIG_MII 1 /* MII PHY management */
-#define CONFIG_PHY_ADDR 0 /* PHY address */
-#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
-
-#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
-
-
-/*
- * BOOTP options
- */
-#define CONFIG_BOOTP_BOOTFILESIZE
-#define CONFIG_BOOTP_BOOTPATH
-#define CONFIG_BOOTP_GATEWAY
-#define CONFIG_BOOTP_HOSTNAME
-
-
-/*
- * Command line configuration.
- */
-#include <config_cmd_default.h>
-
-#define CONFIG_CMD_DHCP
-#define CONFIG_CMD_IRQ
-#define CONFIG_CMD_ELF
-#define CONFIG_CMD_NAND
-#define CONFIG_CMD_I2C
-#define CONFIG_CMD_MII
-#define CONFIG_CMD_PING
-#define CONFIG_CMD_EEPROM
-
-
-#undef CONFIG_WATCHDOG /* watchdog disabled */
-
-#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
-
-/*
- * Miscellaneous configurable options
- */
-#define CONFIG_SYS_LONGHELP /* undef to save memory */
-
-#undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
-
-#if defined(CONFIG_CMD_KGDB)
-#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
-#else
-#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
-#endif
-#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
-#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
-
-#define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
-
-#define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
-
-#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
-#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
-
-#define CONFIG_CONS_INDEX 1 /* Use UART0 */
-#define CONFIG_SYS_NS16550
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE 1
-#define CONFIG_SYS_NS16550_CLK get_serial_clock()
-
-#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */
-#define CONFIG_SYS_BASE_BAUD 691200
-
-/* The following table includes the supported baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE \
- { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
- 57600, 115200, 230400, 460800, 921600 }
-
-#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
-#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
-
-#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
-
-#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
-
-#define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
-
-/* Ethernet stuff */
-#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
-#define CONFIG_ETHADDR 00:50:C2:1E:AF:FE
-#define CONFIG_HAS_ETH1
-#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD
-
-/*-----------------------------------------------------------------------
- * NAND-FLASH stuff
- *-----------------------------------------------------------------------
- */
-#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
-#define NAND_BIG_DELAY_US 25
-
-#define CONFIG_SYS_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
-#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
-#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
-#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
-
-#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
-#define CONFIG_SYS_NAND_QUIET 1
-
-/*-----------------------------------------------------------------------
- * PCI stuff
- *-----------------------------------------------------------------------
- */
-#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
-#define PCI_HOST_FORCE 1 /* configure as pci host */
-#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
-
-#undef CONFIG_PCI /* include pci support */
-#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
-#undef CONFIG_PCI_PNP /* do pci plug-and-play */
- /* resource configuration */
-
-#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
-
-#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
-#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
-#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
-#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
-#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
-#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
-#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */
-#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
-#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
-
-/*-----------------------------------------------------------------------
- * Start addresses for the final memory configuration
- * (Set up by the startup code)
- * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
- */
-#define CONFIG_SYS_SDRAM_BASE 0x00000000
-#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
-#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
-
-/*
- * For booting Linux, the board info and command line data
- * have to be in the first 8 MB of memory, since this is
- * the maximum mapped by the Linux kernel during initialization.
- */
-#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
-/*-----------------------------------------------------------------------
- * FLASH organization
- */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
-#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
-
-#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
-
-#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
-#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
-#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
-/*
- * The following defines are added for buggy IOP480 byte interface.
- * All other boards should use the standard values (CPCI405 etc.)
- */
-#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
-#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
-#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
-
-#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
-
-#if 0 /* test-only */
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
-#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
-#endif
-
-/*-----------------------------------------------------------------------
- * Environment Variable setup
- */
-#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
-#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
-#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
- /* total size of a CAT24WC16 is 2048 bytes */
-
-#define CONFIG_SYS_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
-#define CONFIG_SYS_NVRAM_SIZE 242 /* NVRAM size */
-
-/*-----------------------------------------------------------------------
- * I2C EEPROM (CAT24WC16) for environment
- */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_PPC4XX
-#define CONFIG_SYS_I2C_PPC4XX_CH0
-#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
-#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
-
-#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
-/* mask of address bits that overflow into the "EEPROM chip address" */
-#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
- /* 16 byte page write mode using*/
- /* last 4 bits of the address */
-#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
-
-/*
- * Init Memory Controller:
- *
- * BR0/1 and OR0/1 (FLASH)
- */
-
-#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
-
-/*-----------------------------------------------------------------------
- * External Bus Controller (EBC) Setup
- */
-
-/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB0AP 0x92015480
-/*#define CONFIG_SYS_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
-#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
-
-/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
-#define CONFIG_SYS_EBC_PB1AP 0x92015480
-#define CONFIG_SYS_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
-
-/* Memory Bank 2 (8 Bit Peripheral: UART) initialization */
-#if 0
-#define CONFIG_SYS_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
-#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-#else
-#define CONFIG_SYS_EBC_PB2AP 0x92015480
-#define CONFIG_SYS_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
-#endif
-
-#define DUART0_BA 0xF0000000 /* DUART Base Address */
-#define DUART1_BA 0xF0000008 /* DUART Base Address */
-#define DUART2_BA 0xF0000010 /* DUART Base Address */
-#define DUART3_BA 0xF0000018 /* DUART Base Address */
-#define CONFIG_SYS_NAND_BASE 0xF4000000
-
-/*-----------------------------------------------------------------------
- * FPGA stuff
- */
-#define CONFIG_SYS_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
-#define CONFIG_SYS_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
-
-/* FPGA program pin configuration */
-#define CONFIG_SYS_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
-#define CONFIG_SYS_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
-#define CONFIG_SYS_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
-#define CONFIG_SYS_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
-#define CONFIG_SYS_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
-
-/*-----------------------------------------------------------------------
- * Definitions for initial stack pointer and data area (in data cache)
- */
-/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
-#define CONFIG_SYS_TEMP_STACK_OCM 1
-
-/* On Chip Memory location */
-#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
-#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
-#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
-
-#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
-
-/*-----------------------------------------------------------------------
- * Definitions for GPIO setup (PPC405EP specific)
- *
- * GPIO0[0] - External Bus Controller BLAST output
- * GPIO0[1-9] - Instruction trace outputs -> GPIO
- * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
- * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
- * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
- * GPIO0[24-27] - UART0 control signal inputs/outputs
- * GPIO0[28-29] - UART1 data signal input/output
- * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
- */
-#define CONFIG_SYS_GPIO0_OSRL 0x40000550
-#define CONFIG_SYS_GPIO0_OSRH 0x00000110
-#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
-#define CONFIG_SYS_GPIO0_ISR1H 0x15555445
-#define CONFIG_SYS_GPIO0_TSRL 0x00000000
-#define CONFIG_SYS_GPIO0_TSRH 0x00000000
-#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014
-
-#define CONFIG_SYS_DUART_RST (0x80000000 >> 14)
-#define CONFIG_SYS_UART2_RS232 (0x80000000 >> 5)
-#define CONFIG_SYS_UART3_RS232 (0x80000000 >> 6)
-#define CONFIG_SYS_UART4_RS232 (0x80000000 >> 7)
-#define CONFIG_SYS_UART5_RS232 (0x80000000 >> 8)
-
-/*
- * Default speed selection (cpu_plb_opb_ebc) in mhz.
- * This value will be set if iic boot eprom is disabled.
- */
-#if 0
-#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
-#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
-#endif
-#if 0
-#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
-#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
-#endif
-#if 1
-#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
-#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
-#endif
-
-#endif /* __CONFIG_H */
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-10 15:59:35 +0000