diff options
| -rw-r--r-- | arch/arm/cpu/armv7m/mpu.c | 11 | ||||
| -rw-r--r-- | arch/arm/mach-stm32/soc.c | 36 |
2 files changed, 17 insertions, 30 deletions
diff --git a/arch/arm/cpu/armv7m/mpu.c b/arch/arm/cpu/armv7m/mpu.c index 8e92a33fd4d..e4d090e5de4 100644 --- a/arch/arm/cpu/armv7m/mpu.c +++ b/arch/arm/cpu/armv7m/mpu.c @@ -10,12 +10,13 @@ #include <asm/armv7m_mpu.h> #include <asm/io.h> -#define V7M_MPU_CTRL_ENABLE (1 << 0) +#define V7M_MPU_CTRL_ENABLE BIT(0) #define V7M_MPU_CTRL_DISABLE (0 << 0) -#define V7M_MPU_CTRL_HFNMIENA (1 << 1) -#define VALID_REGION (1 << 4) +#define V7M_MPU_CTRL_HFNMIENA BIT(1) +#define V7M_MPU_CTRL_PRIVDEFENA BIT(2) +#define VALID_REGION BIT(4) -#define ENABLE_REGION (1 << 0) +#define ENABLE_REGION BIT(0) #define AP_SHIFT 24 #define XN_SHIFT 28 @@ -36,7 +37,7 @@ void disable_mpu(void) void enable_mpu(void) { - writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_HFNMIENA, &V7M_MPU->ctrl); + writel(V7M_MPU_CTRL_ENABLE | V7M_MPU_CTRL_PRIVDEFENA, &V7M_MPU->ctrl); /* Make sure new mpu config is effective for next memory access */ dsb(); diff --git a/arch/arm/mach-stm32/soc.c b/arch/arm/mach-stm32/soc.c index df20d547c50..f6fd0b2e23c 100644 --- a/arch/arm/mach-stm32/soc.c +++ b/arch/arm/mach-stm32/soc.c @@ -15,35 +15,21 @@ int arch_cpu_init(void) struct mpu_region_config stm32_region_config[] = { /* - * Make all 4GB cacheable & executable. We are overriding it - * with next region for any requirement. e.g. below region1, - * 2 etc. - * In other words, the area not coming in following - * regions configuration is the one configured here in region_0 - * (cacheable & executable). + * Make SDRAM area cacheable & executable. */ +#if defined(CONFIG_STM32F4) { 0x00000000, REGION_0, XN_DIS, PRIV_RW_USR_RW, - O_I_WB_RD_WR_ALLOC, REGION_4GB }, - - /* armv7m code area */ - { 0x00000000, REGION_1, XN_DIS, PRIV_RW_USR_RW, - STRONG_ORDER, REGION_512MB }, - - /* Device area : Not executable */ - { 0x40000000, REGION_2, XN_EN, PRIV_RW_USR_RW, - DEVICE_NON_SHARED, REGION_512MB }, + O_I_WB_RD_WR_ALLOC, REGION_16MB }, +#endif - /* - * Armv7m fixed configuration: strongly ordered & not - * executable, not cacheable - */ - { 0xE0000000, REGION_3, XN_EN, PRIV_RW_USR_RW, - STRONG_ORDER, REGION_512MB }, +#if defined(CONFIG_STM32F7) + { 0xC0000000, REGION_0, XN_DIS, PRIV_RW_USR_RW, + O_I_WB_RD_WR_ALLOC, REGION_16MB }, +#endif -#if !defined(CONFIG_STM32H7) - /* Device area : Not executable */ - { 0xA0000000, REGION_4, XN_EN, PRIV_RW_USR_RW, - DEVICE_NON_SHARED, REGION_512MB }, +#if defined(CONFIG_STM32H7) + { 0xD0000000, REGION_0, XN_DIS, PRIV_RW_USR_RW, + O_I_WB_RD_WR_ALLOC, REGION_32MB }, #endif }; |