diff options
Diffstat (limited to 'arch/arm/cpu/armv8/fsl-layerscape/cpu.c')
| -rw-r--r-- | arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 46 |
1 files changed, 23 insertions, 23 deletions
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index c11341a1d38..ef71e2cf2bc 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -257,26 +257,26 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, - { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, - CONFIG_SYS_PCIE1_PHYS_SIZE, + { CFG_SYS_PCIE1_PHYS_ADDR, CFG_SYS_PCIE1_PHYS_ADDR, + CFG_SYS_PCIE1_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, - { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, - CONFIG_SYS_PCIE2_PHYS_SIZE, + { CFG_SYS_PCIE2_PHYS_ADDR, CFG_SYS_PCIE2_PHYS_ADDR, + CFG_SYS_PCIE2_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, -#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR - { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, - CONFIG_SYS_PCIE3_PHYS_SIZE, +#ifdef CFG_SYS_PCIE3_PHYS_ADDR + { CFG_SYS_PCIE3_PHYS_ADDR, CFG_SYS_PCIE3_PHYS_ADDR, + CFG_SYS_PCIE3_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, #endif -#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR - { CONFIG_SYS_PCIE4_PHYS_ADDR, CONFIG_SYS_PCIE4_PHYS_ADDR, - CONFIG_SYS_PCIE4_PHYS_SIZE, +#ifdef CFG_SYS_PCIE4_PHYS_ADDR + { CFG_SYS_PCIE4_PHYS_ADDR, CFG_SYS_PCIE4_PHYS_ADDR, + CFG_SYS_PCIE4_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, @@ -368,19 +368,19 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, - { CONFIG_SYS_PCIE1_PHYS_ADDR, CONFIG_SYS_PCIE1_PHYS_ADDR, - CONFIG_SYS_PCIE1_PHYS_SIZE, + { CFG_SYS_PCIE1_PHYS_ADDR, CFG_SYS_PCIE1_PHYS_ADDR, + CFG_SYS_PCIE1_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, - { CONFIG_SYS_PCIE2_PHYS_ADDR, CONFIG_SYS_PCIE2_PHYS_ADDR, - CONFIG_SYS_PCIE2_PHYS_SIZE, + { CFG_SYS_PCIE2_PHYS_ADDR, CFG_SYS_PCIE2_PHYS_ADDR, + CFG_SYS_PCIE2_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, -#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR - { CONFIG_SYS_PCIE3_PHYS_ADDR, CONFIG_SYS_PCIE3_PHYS_ADDR, - CONFIG_SYS_PCIE3_PHYS_SIZE, +#ifdef CFG_SYS_PCIE3_PHYS_ADDR + { CFG_SYS_PCIE3_PHYS_ADDR, CFG_SYS_PCIE3_PHYS_ADDR, + CFG_SYS_PCIE3_PHYS_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, @@ -477,25 +477,25 @@ static void fix_pcie_mmu_map(void) (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) { for (i = 0; i < ARRAY_SIZE(final_map); i++) { switch (final_map[i].phys) { - case CONFIG_SYS_PCIE1_PHYS_ADDR: + case CFG_SYS_PCIE1_PHYS_ADDR: final_map[i].phys = 0x2000000000ULL; final_map[i].virt = 0x2000000000ULL; final_map[i].size = 0x800000000ULL; break; - case CONFIG_SYS_PCIE2_PHYS_ADDR: + case CFG_SYS_PCIE2_PHYS_ADDR: final_map[i].phys = 0x2800000000ULL; final_map[i].virt = 0x2800000000ULL; final_map[i].size = 0x800000000ULL; break; -#ifdef CONFIG_SYS_PCIE3_PHYS_ADDR - case CONFIG_SYS_PCIE3_PHYS_ADDR: +#ifdef CFG_SYS_PCIE3_PHYS_ADDR + case CFG_SYS_PCIE3_PHYS_ADDR: final_map[i].phys = 0x3000000000ULL; final_map[i].virt = 0x3000000000ULL; final_map[i].size = 0x800000000ULL; break; #endif -#ifdef CONFIG_SYS_PCIE4_PHYS_ADDR - case CONFIG_SYS_PCIE4_PHYS_ADDR: +#ifdef CFG_SYS_PCIE4_PHYS_ADDR + case CFG_SYS_PCIE4_PHYS_ADDR: final_map[i].phys = 0x3800000000ULL; final_map[i].virt = 0x3800000000ULL; final_map[i].size = 0x800000000ULL; |