diff options
Diffstat (limited to 'arch/arm/dts/rk3288.dtsi')
| -rw-r--r-- | arch/arm/dts/rk3288.dtsi | 110 |
1 files changed, 55 insertions, 55 deletions
diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi index 5e40e7419e3..12566a033f4 100644 --- a/arch/arm/dts/rk3288.dtsi +++ b/arch/arm/dts/rk3288.dtsi @@ -709,54 +709,29 @@ status = "disabled"; }; - edp: edp@ff970000 { - compatible = "rockchip,rk3288-edp"; - reg = <0xff970000 0x4000>; - interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>; - rockchip,grf = <&grf>; - clock-names = "clk_edp", "clk_edp_24m", "pclk_edp"; - resets = <&cru 111>; - reset-names = "edp"; - power-domains = <&power RK3288_PD_VIO>; - status = "disabled"; - ports { - edp_in: port { - #address-cells = <1>; - #size-cells = <0>; - edp_in_vopb: endpoint@0 { - reg = <0>; - remote-endpoint = <&vopb_out_edp>; - }; - edp_in_vopl: endpoint@1 { - reg = <1>; - remote-endpoint = <&vopl_out_edp>; - }; - }; - }; - }; - - hdmi: hdmi@ff980000 { - compatible = "rockchip,rk3288-dw-hdmi"; - reg = <0xff980000 0x20000>; - reg-io-width = <4>; - ddc-i2c-bus = <&i2c5>; + mipi_dsi: mipi@ff960000 { + compatible = "rockchip,rk3288_mipi_dsi"; + reg = <0xff960000 0x4000>; + clocks = <&cru PCLK_MIPI_DSI0>; + clock-names = "pclk_mipi"; + /*pinctrl-names = "default"; + pinctrl-0 = <&lcdc0_ctl>;*/ rockchip,grf = <&grf>; - interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; - clock-names = "iahb", "isfr"; + #address-cells = <1>; + #size-cells = <0>; status = "disabled"; ports { - hdmi_in: port { + reg = <1>; + mipi_in: port { #address-cells = <1>; #size-cells = <0>; - hdmi_in_vopb: endpoint@0 { + mipi_in_vopb: endpoint@0 { reg = <0>; - remote-endpoint = <&vopb_out_hdmi>; + remote-endpoint = <&vopb_out_mipi>; }; - hdmi_in_vopl: endpoint@1 { + mipi_in_vopl: endpoint@1 { reg = <1>; - remote-endpoint = <&vopl_out_hdmi>; + remote-endpoint = <&vopl_out_mipi>; }; }; }; @@ -790,29 +765,54 @@ }; }; - mipi_dsi0: mipi@ff960000 { - compatible = "rockchip,rk3288_mipi_dsi"; - reg = <0xff960000 0x4000>; - clocks = <&cru PCLK_MIPI_DSI0>; - clock-names = "pclk_mipi"; - /*pinctrl-names = "default"; - pinctrl-0 = <&lcdc0_ctl>;*/ + edp: dp@ff970000 { + compatible = "rockchip,rk3288-edp"; + reg = <0xff970000 0x4000>; + interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru SCLK_EDP>, <&cru SCLK_EDP_24M>, <&cru PCLK_EDP_CTRL>; rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; + clock-names = "clk_edp", "clk_edp_24m", "pclk_edp"; + resets = <&cru 111>; + reset-names = "edp"; + power-domains = <&power RK3288_PD_VIO>; status = "disabled"; ports { - reg = <1>; - mipi_in: port { + edp_in: port { #address-cells = <1>; #size-cells = <0>; - mipi_in_vopb: endpoint@0 { + edp_in_vopb: endpoint@0 { reg = <0>; - remote-endpoint = <&vopb_out_mipi>; + remote-endpoint = <&vopb_out_edp>; }; - mipi_in_vopl: endpoint@1 { + edp_in_vopl: endpoint@1 { reg = <1>; - remote-endpoint = <&vopl_out_mipi>; + remote-endpoint = <&vopl_out_edp>; + }; + }; + }; + }; + + hdmi: hdmi@ff980000 { + compatible = "rockchip,rk3288-dw-hdmi"; + reg = <0xff980000 0x20000>; + reg-io-width = <4>; + ddc-i2c-bus = <&i2c5>; + rockchip,grf = <&grf>; + interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru PCLK_HDMI_CTRL>, <&cru SCLK_HDMI_HDCP>; + clock-names = "iahb", "isfr"; + status = "disabled"; + ports { + hdmi_in: port { + #address-cells = <1>; + #size-cells = <0>; + hdmi_in_vopb: endpoint@0 { + reg = <0>; + remote-endpoint = <&vopb_out_hdmi>; + }; + hdmi_in_vopl: endpoint@1 { + reg = <1>; + remote-endpoint = <&vopl_out_hdmi>; }; }; }; |