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-rw-r--r--arch/arm/include/asm/arch-imx8m/clock.h491
-rw-r--r--arch/arm/include/asm/arch-imx8m/clock_imx8mm.h387
-rw-r--r--arch/arm/include/asm/arch-imx8m/clock_imx8mq.h424
-rw-r--r--arch/arm/include/asm/arch-imx8m/imx-regs.h291
-rw-r--r--arch/arm/include/asm/arch-imx8m/imx8mm_pins.h691
-rw-r--r--arch/arm/include/asm/arch-imx8m/power-domain.h15
6 files changed, 1626 insertions, 673 deletions
diff --git a/arch/arm/include/asm/arch-imx8m/clock.h b/arch/arm/include/asm/arch-imx8m/clock.h
index e7c1670f6b9..dded6e07977 100644
--- a/arch/arm/include/asm/arch-imx8m/clock.h
+++ b/arch/arm/include/asm/arch-imx8m/clock.h
@@ -2,27 +2,32 @@
/*
* Copyright 2017 NXP
*
- * Peng Fan <peng.fan@nxp.com>
+ * Peng Fan <peng.fan at nxp.com>
*/
-#ifndef _ASM_ARCH_IMX8M_CLOCK_H
-#define _ASM_ARCH_IMX8M_CLOCK_H
-
#include <linux/bitops.h>
+#ifdef CONFIG_IMX8MQ
+#include <asm/arch/clock_imx8mq.h>
+#elif defined(CONFIG_IMX8MM)
+#include <asm/arch/clock_imx8mm.h>
+#else
+#error "Error no clock.h"
+#endif
+
#define MHZ(X) ((X) * 1000000UL)
-enum pll_clocks {
- ANATOP_ARM_PLL,
- ANATOP_GPU_PLL,
- ANATOP_SYSTEM_PLL1,
- ANATOP_SYSTEM_PLL2,
- ANATOP_SYSTEM_PLL3,
- ANATOP_AUDIO_PLL1,
- ANATOP_AUDIO_PLL2,
- ANATOP_VIDEO_PLL1,
- ANATOP_VIDEO_PLL2,
- ANATOP_DRAM_PLL,
+/* Mainly for compatible to imx common code. */
+enum mxc_clock {
+ MXC_ARM_CLK = 0,
+ MXC_IPG_CLK,
+ MXC_CSPI_CLK,
+ MXC_ESDHC_CLK,
+ MXC_ESDHC2_CLK,
+ MXC_ESDHC3_CLK,
+ MXC_I2C_CLK,
+ MXC_UART_CLK,
+ MXC_QSPI_CLK,
};
enum clk_slice_type {
@@ -35,297 +40,6 @@ enum clk_slice_type {
DRAM_SEL_CLOCK_SLICE,
};
-enum clk_root_index {
- MXC_ARM_CLK = 0,
- ARM_A53_CLK_ROOT = 0,
- ARM_M4_CLK_ROOT = 1,
- VPU_A53_CLK_ROOT = 2,
- GPU_CORE_CLK_ROOT = 3,
- GPU_SHADER_CLK_ROOT = 4,
- MAIN_AXI_CLK_ROOT = 16,
- ENET_AXI_CLK_ROOT = 17,
- NAND_USDHC_BUS_CLK_ROOT = 18,
- VPU_BUS_CLK_ROOT = 19,
- DISPLAY_AXI_CLK_ROOT = 20,
- DISPLAY_APB_CLK_ROOT = 21,
- DISPLAY_RTRM_CLK_ROOT = 22,
- USB_BUS_CLK_ROOT = 23,
- GPU_AXI_CLK_ROOT = 24,
- GPU_AHB_CLK_ROOT = 25,
- NOC_CLK_ROOT = 26,
- NOC_APB_CLK_ROOT = 27,
- AHB_CLK_ROOT = 32,
- IPG_CLK_ROOT = 33,
- MXC_IPG_CLK = 33,
- AUDIO_AHB_CLK_ROOT = 34,
- MIPI_DSI_ESC_RX_CLK_ROOT = 36,
- DRAM_SEL_CFG = 48,
- CORE_SEL_CFG = 49,
- DRAM_ALT_CLK_ROOT = 64,
- DRAM_APB_CLK_ROOT = 65,
- VPU_G1_CLK_ROOT = 66,
- VPU_G2_CLK_ROOT = 67,
- DISPLAY_DTRC_CLK_ROOT = 68,
- DISPLAY_DC8000_CLK_ROOT = 69,
- PCIE1_CTRL_CLK_ROOT = 70,
- PCIE1_PHY_CLK_ROOT = 71,
- PCIE1_AUX_CLK_ROOT = 72,
- DC_PIXEL_CLK_ROOT = 73,
- LCDIF_PIXEL_CLK_ROOT = 74,
- SAI1_CLK_ROOT = 75,
- SAI2_CLK_ROOT = 76,
- SAI3_CLK_ROOT = 77,
- SAI4_CLK_ROOT = 78,
- SAI5_CLK_ROOT = 79,
- SAI6_CLK_ROOT = 80,
- SPDIF1_CLK_ROOT = 81,
- SPDIF2_CLK_ROOT = 82,
- ENET_REF_CLK_ROOT = 83,
- ENET_TIMER_CLK_ROOT = 84,
- ENET_PHY_REF_CLK_ROOT = 85,
- NAND_CLK_ROOT = 86,
- QSPI_CLK_ROOT = 87,
- MXC_ESDHC_CLK = 88,
- USDHC1_CLK_ROOT = 88,
- MXC_ESDHC2_CLK = 89,
- USDHC2_CLK_ROOT = 89,
- I2C1_CLK_ROOT = 90,
- MXC_I2C_CLK = 90,
- I2C2_CLK_ROOT = 91,
- I2C3_CLK_ROOT = 92,
- I2C4_CLK_ROOT = 93,
- UART1_CLK_ROOT = 94,
- UART2_CLK_ROOT = 95,
- UART3_CLK_ROOT = 96,
- UART4_CLK_ROOT = 97,
- USB_CORE_REF_CLK_ROOT = 98,
- USB_PHY_REF_CLK_ROOT = 99,
- GIC_CLK_ROOT = 100,
- ECSPI1_CLK_ROOT = 101,
- ECSPI2_CLK_ROOT = 102,
- PWM1_CLK_ROOT = 103,
- PWM2_CLK_ROOT = 104,
- PWM3_CLK_ROOT = 105,
- PWM4_CLK_ROOT = 106,
- GPT1_CLK_ROOT = 107,
- GPT2_CLK_ROOT = 108,
- GPT3_CLK_ROOT = 109,
- GPT4_CLK_ROOT = 110,
- GPT5_CLK_ROOT = 111,
- GPT6_CLK_ROOT = 112,
- TRACE_CLK_ROOT = 113,
- WDOG_CLK_ROOT = 114,
- WRCLK_CLK_ROOT = 115,
- IPP_DO_CLKO1 = 116,
- IPP_DO_CLKO2 = 117,
- MIPI_DSI_CORE_CLK_ROOT = 118,
- MIPI_DSI_PHY_REF_CLK_ROOT = 119,
- MIPI_DSI_DBI_CLK_ROOT = 120,
- OLD_MIPI_DSI_ESC_CLK_ROOT = 121,
- MIPI_CSI1_CORE_CLK_ROOT = 122,
- MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
- MIPI_CSI1_ESC_CLK_ROOT = 124,
- MIPI_CSI2_CORE_CLK_ROOT = 125,
- MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
- MIPI_CSI2_ESC_CLK_ROOT = 127,
- PCIE2_CTRL_CLK_ROOT = 128,
- PCIE2_PHY_CLK_ROOT = 129,
- PCIE2_AUX_CLK_ROOT = 130,
- ECSPI3_CLK_ROOT = 131,
- OLD_MIPI_DSI_ESC_RX_ROOT = 132,
- DISPLAY_HDMI_CLK_ROOT = 133,
- CLK_ROOT_MAX,
-};
-
-enum clk_root_src {
- OSC_25M_CLK,
- ARM_PLL_CLK,
- DRAM_PLL1_CLK,
- VIDEO_PLL2_CLK,
- VPU_PLL_CLK,
- GPU_PLL_CLK,
- SYSTEM_PLL1_800M_CLK,
- SYSTEM_PLL1_400M_CLK,
- SYSTEM_PLL1_266M_CLK,
- SYSTEM_PLL1_200M_CLK,
- SYSTEM_PLL1_160M_CLK,
- SYSTEM_PLL1_133M_CLK,
- SYSTEM_PLL1_100M_CLK,
- SYSTEM_PLL1_80M_CLK,
- SYSTEM_PLL1_40M_CLK,
- SYSTEM_PLL2_1000M_CLK,
- SYSTEM_PLL2_500M_CLK,
- SYSTEM_PLL2_333M_CLK,
- SYSTEM_PLL2_250M_CLK,
- SYSTEM_PLL2_200M_CLK,
- SYSTEM_PLL2_166M_CLK,
- SYSTEM_PLL2_125M_CLK,
- SYSTEM_PLL2_100M_CLK,
- SYSTEM_PLL2_50M_CLK,
- SYSTEM_PLL3_CLK,
- AUDIO_PLL1_CLK,
- AUDIO_PLL2_CLK,
- VIDEO_PLL_CLK,
- OSC_32K_CLK,
- EXT_CLK_1,
- EXT_CLK_2,
- EXT_CLK_3,
- EXT_CLK_4,
- OSC_27M_CLK,
-};
-
-/* CCGR index */
-enum clk_ccgr_index {
- CCGR_DVFS = 0,
- CCGR_ANAMIX = 1,
- CCGR_CPU = 2,
- CCGR_CSU = 4,
- CCGR_DRAM1 = 5,
- CCGR_DRAM2_OBSOLETE = 6,
- CCGR_ECSPI1 = 7,
- CCGR_ECSPI2 = 8,
- CCGR_ECSPI3 = 9,
- CCGR_ENET1 = 10,
- CCGR_GPIO1 = 11,
- CCGR_GPIO2 = 12,
- CCGR_GPIO3 = 13,
- CCGR_GPIO4 = 14,
- CCGR_GPIO5 = 15,
- CCGR_GPT1 = 16,
- CCGR_GPT2 = 17,
- CCGR_GPT3 = 18,
- CCGR_GPT4 = 19,
- CCGR_GPT5 = 20,
- CCGR_GPT6 = 21,
- CCGR_HS = 22,
- CCGR_I2C1 = 23,
- CCGR_I2C2 = 24,
- CCGR_I2C3 = 25,
- CCGR_I2C4 = 26,
- CCGR_IOMUX = 27,
- CCGR_IOMUX1 = 28,
- CCGR_IOMUX2 = 29,
- CCGR_IOMUX3 = 30,
- CCGR_IOMUX4 = 31,
- CCGR_M4 = 32,
- CCGR_MU = 33,
- CCGR_OCOTP = 34,
- CCGR_OCRAM = 35,
- CCGR_OCRAM_S = 36,
- CCGR_PCIE = 37,
- CCGR_PERFMON1 = 38,
- CCGR_PERFMON2 = 39,
- CCGR_PWM1 = 40,
- CCGR_PWM2 = 41,
- CCGR_PWM3 = 42,
- CCGR_PWM4 = 43,
- CCGR_QOS = 44,
- CCGR_DISMIX = 45,
- CCGR_MEGAMIX = 46,
- CCGR_QSPI = 47,
- CCGR_RAWNAND = 48,
- CCGR_RDC = 49,
- CCGR_ROM = 50,
- CCGR_SAI1 = 51,
- CCGR_SAI2 = 52,
- CCGR_SAI3 = 53,
- CCGR_SAI4 = 54,
- CCGR_SAI5 = 55,
- CCGR_SAI6 = 56,
- CCGR_SCTR = 57,
- CCGR_SDMA1 = 58,
- CCGR_SDMA2 = 59,
- CCGR_SEC_DEBUG = 60,
- CCGR_SEMA1 = 61,
- CCGR_SEMA2 = 62,
- CCGR_SIM_DISPLAY = 63,
- CCGR_SIM_ENET = 64,
- CCGR_SIM_M = 65,
- CCGR_SIM_MAIN = 66,
- CCGR_SIM_S = 67,
- CCGR_SIM_WAKEUP = 68,
- CCGR_SIM_USB = 69,
- CCGR_SIM_VPU = 70,
- CCGR_SNVS = 71,
- CCGR_TRACE = 72,
- CCGR_UART1 = 73,
- CCGR_UART2 = 74,
- CCGR_UART3 = 75,
- CCGR_UART4 = 76,
- CCGR_USB_CTRL1 = 77,
- CCGR_USB_CTRL2 = 78,
- CCGR_USB_PHY1 = 79,
- CCGR_USB_PHY2 = 80,
- CCGR_USDHC1 = 81,
- CCGR_USDHC2 = 82,
- CCGR_WDOG1 = 83,
- CCGR_WDOG2 = 84,
- CCGR_WDOG3 = 85,
- CCGR_VA53 = 86,
- CCGR_GPU = 87,
- CCGR_HEVC = 88,
- CCGR_AVC = 89,
- CCGR_VP9 = 90,
- CCGR_HEVC_INTER = 91,
- CCGR_GIC = 92,
- CCGR_DISPLAY = 93,
- CCGR_HDMI = 94,
- CCGR_HDMI_PHY = 95,
- CCGR_XTAL = 96,
- CCGR_PLL = 97,
- CCGR_TSENSOR = 98,
- CCGR_VPU_DEC = 99,
- CCGR_PCIE2 = 100,
- CCGR_MIPI_CSI1 = 101,
- CCGR_MIPI_CSI2 = 102,
- CCGR_MAX,
-};
-
-/* src index */
-enum clk_src_index {
- CLK_SRC_CKIL_SYNC_REQ = 0,
- CLK_SRC_ARM_PLL_EN = 1,
- CLK_SRC_GPU_PLL_EN = 2,
- CLK_SRC_VPU_PLL_EN = 3,
- CLK_SRC_DRAM_PLL_EN = 4,
- CLK_SRC_SYSTEM_PLL1_EN = 5,
- CLK_SRC_SYSTEM_PLL2_EN = 6,
- CLK_SRC_SYSTEM_PLL3_EN = 7,
- CLK_SRC_AUDIO_PLL1_EN = 8,
- CLK_SRC_AUDIO_PLL2_EN = 9,
- CLK_SRC_VIDEO_PLL1_EN = 10,
- CLK_SRC_VIDEO_PLL2_EN = 11,
- CLK_SRC_ARM_PLL = 12,
- CLK_SRC_GPU_PLL = 13,
- CLK_SRC_VPU_PLL = 14,
- CLK_SRC_DRAM_PLL = 15,
- CLK_SRC_SYSTEM_PLL1_800M = 16,
- CLK_SRC_SYSTEM_PLL1_400M = 17,
- CLK_SRC_SYSTEM_PLL1_266M = 18,
- CLK_SRC_SYSTEM_PLL1_200M = 19,
- CLK_SRC_SYSTEM_PLL1_160M = 20,
- CLK_SRC_SYSTEM_PLL1_133M = 21,
- CLK_SRC_SYSTEM_PLL1_100M = 22,
- CLK_SRC_SYSTEM_PLL1_80M = 23,
- CLK_SRC_SYSTEM_PLL1_40M = 24,
- CLK_SRC_SYSTEM_PLL2_1000M = 25,
- CLK_SRC_SYSTEM_PLL2_500M = 26,
- CLK_SRC_SYSTEM_PLL2_333M = 27,
- CLK_SRC_SYSTEM_PLL2_250M = 28,
- CLK_SRC_SYSTEM_PLL2_200M = 29,
- CLK_SRC_SYSTEM_PLL2_166M = 30,
- CLK_SRC_SYSTEM_PLL2_125M = 31,
- CLK_SRC_SYSTEM_PLL2_100M = 32,
- CLK_SRC_SYSTEM_PLL2_50M = 33,
- CLK_SRC_SYSTEM_PLL3 = 34,
- CLK_SRC_AUDIO_PLL1 = 35,
- CLK_SRC_AUDIO_PLL2 = 36,
- CLK_SRC_VIDEO_PLL1 = 37,
- CLK_SRC_VIDEO_PLL2 = 38,
- CLK_SRC_OSC_25M = 39,
- CLK_SRC_OSC_27M = 40,
-};
-
enum root_pre_div {
CLK_ROOT_PRE_DIV1 = 0,
CLK_ROOT_PRE_DIV2,
@@ -466,6 +180,29 @@ struct ccm_reg {
struct ccm_root ip_root[78];
};
+enum enet_freq {
+ ENET_25MHZ = 0,
+ ENET_50MHZ,
+ ENET_125MHZ,
+};
+
+#define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k) \
+ { \
+ .clk = (_rate), \
+ .alt_root_sel = (_m), \
+ .alt_pre_div = (_p), \
+ .apb_root_sel = (_s), \
+ .apb_pre_div = (_k), \
+ }
+
+struct dram_bypass_clk_setting {
+ ulong clk;
+ int alt_root_sel;
+ enum root_pre_div alt_pre_div;
+ int apb_root_sel;
+ enum root_pre_div apb_pre_div;
+};
+
#define CCGR_CLK_ON_MASK 0x03
#define CLK_SRC_ON_MASK 0x03
@@ -503,117 +240,6 @@ struct ccm_reg {
#define CLK_ROOT_IPG_POST_DIV_MASK 0x3
#define CLK_ROOT_POST_DIV_SHIFT 0
#define CLK_ROOT_POST_DIV(n) ((n) & 0x3f)
-
-/* AUDIO PLL1/2 VIDEO PLL1 GPU PLL VPU PLL ARM PLL*/
-#define FRAC_PLL_LOCK_MASK BIT(31)
-#define FRAC_PLL_CLKE_MASK BIT(21)
-#define FRAC_PLL_PD_MASK BIT(19)
-#define FRAC_PLL_REFCLK_SEL_MASK BIT(16)
-#define FRAC_PLL_LOCK_SEL_MASK BIT(15)
-#define FRAC_PLL_BYPASS_MASK BIT(14)
-#define FRAC_PLL_COUNTCLK_SEL_MASK BIT(13)
-#define FRAC_PLL_NEWDIV_VAL_MASK BIT(12)
-#define FRAC_PLL_NEWDIV_ACK_MASK BIT(11)
-#define FRAC_PLL_REFCLK_DIV_VAL(n) (((n) << 5) & (0x3f << 5))
-#define FRAC_PLL_REFCLK_DIV_VAL_MASK (0x3f << 5)
-#define FRAC_PLL_REFCLK_DIV_VAL_SHIFT 5
-#define FRAC_PLL_OUTPUT_DIV_VAL_MASK 0x1f
-#define FRAC_PLL_OUTPUT_DIV_VAL(n) ((n) & 0x1f)
-
-#define FRAC_PLL_REFCLK_SEL_OSC_25M (0 << 16)
-#define FRAC_PLL_REFCLK_SEL_OSC_27M BIT(16)
-#define FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
-#define FRAC_PLL_REFCLK_SEL_CLK_PN (3 << 16)
-
-#define FRAC_PLL_FRAC_DIV_CTL_MASK (0x1ffffff << 7)
-#define FRAC_PLL_FRAC_DIV_CTL_SHIFT 7
-#define FRAC_PLL_INT_DIV_CTL_MASK 0x7f
-#define FRAC_PLL_INT_DIV_CTL_VAL(n) ((n) & 0x7f)
-
-/* SYS PLL1/2/3 VIDEO PLL2 DRAM PLL */
-#define SSCG_PLL_LOCK_MASK BIT(31)
-#define SSCG_PLL_CLKE_MASK BIT(25)
-#define SSCG_PLL_DIV2_CLKE_MASK BIT(23)
-#define SSCG_PLL_DIV3_CLKE_MASK BIT(21)
-#define SSCG_PLL_DIV4_CLKE_MASK BIT(19)
-#define SSCG_PLL_DIV5_CLKE_MASK BIT(17)
-#define SSCG_PLL_DIV6_CLKE_MASK BIT(15)
-#define SSCG_PLL_DIV8_CLKE_MASK BIT(13)
-#define SSCG_PLL_DIV10_CLKE_MASK BIT(11)
-#define SSCG_PLL_DIV20_CLKE_MASK BIT(9)
-#define SSCG_PLL_VIDEO_PLL2_CLKE_MASK BIT(9)
-#define SSCG_PLL_DRAM_PLL_CLKE_MASK BIT(9)
-#define SSCG_PLL_PLL3_CLKE_MASK BIT(9)
-#define SSCG_PLL_PD_MASK BIT(7)
-#define SSCG_PLL_BYPASS1_MASK BIT(5)
-#define SSCG_PLL_BYPASS2_MASK BIT(4)
-#define SSCG_PLL_LOCK_SEL_MASK BIT(3)
-#define SSCG_PLL_COUNTCLK_SEL_MASK BIT(2)
-#define SSCG_PLL_REFCLK_SEL_MASK 0x3
-#define SSCG_PLL_REFCLK_SEL_OSC_25M (0 << 16)
-#define SSCG_PLL_REFCLK_SEL_OSC_27M BIT(16)
-#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
-#define SSCG_PLL_REFCLK_SEL_CLK_PN (3 << 16)
-
-#define SSCG_PLL_SSDS_MASK BIT(8)
-#define SSCG_PLL_SSMD_MASK (0x7 << 5)
-#define SSCG_PLL_SSMF_MASK (0xf << 1)
-#define SSCG_PLL_SSE_MASK 0x1
-
-#define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25)
-#define SSCG_PLL_REF_DIVR1_SHIFT 25
-#define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
-#define SSCG_PLL_REF_DIVR2_MASK (0x3f << 19)
-#define SSCG_PLL_REF_DIVR2_SHIFT 19
-#define SSCG_PLL_REF_DIVR2_VAL(n) (((n) << 19) & SSCG_PLL_REF_DIVR2_MASK)
-#define SSCG_PLL_FEEDBACK_DIV_F1_MASK (0x3f << 13)
-#define SSCG_PLL_FEEDBACK_DIV_F1_SHIFT 13
-#define SSCG_PLL_FEEDBACK_DIV_F1_VAL(n) (((n) << 13) & \
- SSCG_PLL_FEEDBACK_DIV_F1_MASK)
-#define SSCG_PLL_FEEDBACK_DIV_F2_MASK (0x3f << 7)
-#define SSCG_PLL_FEEDBACK_DIV_F2_SHIFT 7
-#define SSCG_PLL_FEEDBACK_DIV_F2_VAL(n) (((n) << 7) & \
- SSCG_PLL_FEEDBACK_DIV_F2_MASK)
-#define SSCG_PLL_OUTPUT_DIV_VAL_MASK (0x3f << 1)
-#define SSCG_PLL_OUTPUT_DIV_VAL_SHIFT 1
-#define SSCG_PLL_OUTPUT_DIV_VAL(n) (((n) << 1) & \
- SSCG_PLL_OUTPUT_DIV_VAL_MASK)
-#define SSCG_PLL_FILTER_RANGE_MASK 0x1
-
-#define HW_DIGPROG_MAJOR_UPPER_MASK (0xff << 16)
-#define HW_DIGPROG_MAJOR_LOWER_MASK (0xff << 8)
-#define HW_DIGPROG_MINOR_MASK 0xff
-
-#define HW_OSC_27M_CLKE_MASK BIT(4)
-#define HW_OSC_25M_CLKE_MASK BIT(2)
-#define HW_OSC_32K_SEL_MASK 0x1
-#define HW_OSC_32K_SEL_RTC 0x1
-#define HW_OSC_32K_SEL_25M_DIV800 0x0
-
-#define HW_FRAC_ARM_PLL_DIV_MASK (0x7 << 20)
-#define HW_FRAC_ARM_PLL_DIV_SHIFT 20
-#define HW_FRAC_VPU_PLL_DIV_MASK (0x7 << 16)
-#define HW_FRAC_VPU_PLL_DIV_SHIFT 16
-#define HW_FRAC_GPU_PLL_DIV_MASK (0x7 << 12)
-#define HW_FRAC_GPU_PLL_DIV_SHIFT 12
-#define HW_FRAC_VIDEO_PLL1_DIV_MASK (0x7 << 10)
-#define HW_FRAC_VIDEO_PLL1_DIV_SHIFT 10
-#define HW_FRAC_AUDIO_PLL2_DIV_MASK (0x7 << 4)
-#define HW_FRAC_AUDIO_PLL2_DIV_SHIFT 4
-#define HW_FRAC_AUDIO_PLL1_DIV_MASK 0x7
-#define HW_FRAC_AUDIO_PLL1_DIV_SHIFT 0
-
-#define HW_SSCG_VIDEO_PLL2_DIV_MASK (0x7 << 16)
-#define HW_SSCG_VIDEO_PLL2_DIV_SHIFT 16
-#define HW_SSCG_DRAM_PLL_DIV_MASK (0x7 << 14)
-#define HW_SSCG_DRAM_PLL_DIV_SHIFT 14
-#define HW_SSCG_SYSTEM_PLL3_DIV_MASK (0x7 << 8)
-#define HW_SSCG_SYSTEM_PLL3_DIV_SHIFT 8
-#define HW_SSCG_SYSTEM_PLL2_DIV_MASK (0x7 << 4)
-#define HW_SSCG_SYSTEM_PLL2_DIV_SHIFT 4
-#define HW_SSCG_SYSTEM_PLL1_DIV_MASK 0x7
-#define HW_SSCG_SYSTEM_PLL1_DIV_SHIFT 0
-
#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_125M_CLK 0x01000000
#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_50M_CLK 0x02000000
#define ENET1_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x03000000
@@ -622,34 +248,6 @@ struct ccm_reg {
#define ENET1_TIME_CLK_ROOT_FROM_PLL_ENET_MAIN_100M_CLK 0x01000000
#define ENET_PHY_REF_CLK_ROOT_FROM_PLL_ENET_MAIN_25M_CLK 0x01000000
-enum enet_freq {
- ENET_25MHZ = 0,
- ENET_50MHZ,
- ENET_125MHZ,
-};
-
-enum frac_pll_out_val {
- FRAC_PLL_OUT_1000M,
- FRAC_PLL_OUT_1600M,
-};
-
-#define DRAM_BYPASS_ROOT_CONFIG(_rate, _m, _p, _s, _k) \
- { \
- .clk = (_rate), \
- .alt_root_sel = (_m), \
- .alt_pre_div = (_p), \
- .apb_root_sel = (_s), \
- .apb_pre_div = (_k), \
- }
-
-struct dram_bypass_clk_setting {
- ulong clk;
- int alt_root_sel;
- enum root_pre_div alt_pre_div;
- int apb_root_sel;
- enum root_pre_div apb_pre_div;
-};
-
void dram_pll_init(ulong pll_val);
void dram_enable_bypass(ulong clk_val);
void dram_disable_bypass(void);
@@ -659,7 +257,7 @@ int clock_init(void);
void init_clk_usdhc(u32 index);
void init_uart_clk(u32 index);
void init_wdog_clk(void);
-unsigned int mxc_get_clock(enum clk_root_index clk);
+unsigned int mxc_get_clock(enum mxc_clock clk);
int clock_enable(enum clk_ccgr_index index, bool enable);
int clock_root_enabled(enum clk_root_index clock_id);
int clock_root_cfg(enum clk_root_index clock_id, enum root_pre_div pre_div,
@@ -675,4 +273,3 @@ int set_clk_qspi(void);
void enable_ocotp_clk(unsigned char enable);
int enable_i2c_clk(unsigned char enable, unsigned int i2c_num);
int set_clk_enet(enum enet_freq type);
-#endif
diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
new file mode 100644
index 00000000000..305514a4ecc
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mm.h
@@ -0,0 +1,387 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018-2019 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#ifndef _ASM_ARCH_IMX8MM_CLOCK_H
+#define _ASM_ARCH_IMX8MM_CLOCK_H
+
+#define PLL_1443X_RATE(_rate, _m, _p, _s, _k) \
+ { \
+ .rate = (_rate), \
+ .mdiv = (_m), \
+ .pdiv = (_p), \
+ .sdiv = (_s), \
+ .kdiv = (_k), \
+ }
+
+#define LOCK_STATUS BIT(31)
+#define LOCK_SEL_MASK BIT(29)
+#define CLKE_MASK BIT(11)
+#define RST_MASK BIT(9)
+#define BYPASS_MASK BIT(4)
+#define MDIV_SHIFT 12
+#define MDIV_MASK GENMASK(21, 12)
+#define PDIV_SHIFT 4
+#define PDIV_MASK GENMASK(9, 4)
+#define SDIV_SHIFT 0
+#define SDIV_MASK GENMASK(2, 0)
+#define KDIV_SHIFT 0
+#define KDIV_MASK GENMASK(15, 0)
+
+struct imx_int_pll_rate_table {
+ u32 rate;
+ int mdiv;
+ int pdiv;
+ int sdiv;
+ int kdiv;
+};
+
+enum pll_clocks {
+ ANATOP_ARM_PLL,
+ ANATOP_VPU_PLL,
+ ANATOP_GPU_PLL,
+ ANATOP_SYSTEM_PLL1,
+ ANATOP_SYSTEM_PLL2,
+ ANATOP_SYSTEM_PLL3,
+ ANATOP_AUDIO_PLL1,
+ ANATOP_AUDIO_PLL2,
+ ANATOP_VIDEO_PLL,
+ ANATOP_DRAM_PLL,
+};
+
+enum clk_root_index {
+ ARM_A53_CLK_ROOT = 0,
+ ARM_M4_CLK_ROOT = 1,
+ VPU_A53_CLK_ROOT = 2,
+ GPU3D_CLK_ROOT = 3,
+ GPU2D_CLK_ROOT = 4,
+ MAIN_AXI_CLK_ROOT = 16,
+ ENET_AXI_CLK_ROOT = 17,
+ NAND_USDHC_BUS_CLK_ROOT = 18,
+ VPU_BUS_CLK_ROOT = 19,
+ DISPLAY_AXI_CLK_ROOT = 20,
+ DISPLAY_APB_CLK_ROOT = 21,
+ DISPLAY_RTRM_CLK_ROOT = 22,
+ USB_BUS_CLK_ROOT = 23,
+ GPU_AXI_CLK_ROOT = 24,
+ GPU_AHB_CLK_ROOT = 25,
+ NOC_CLK_ROOT = 26,
+ NOC_APB_CLK_ROOT = 27,
+ AHB_CLK_ROOT = 32,
+ IPG_CLK_ROOT = 33,
+ AUDIO_AHB_CLK_ROOT = 34,
+ MIPI_DSI_ESC_RX_CLK_ROOT = 36,
+ DRAM_SEL_CFG = 48,
+ CORE_SEL_CFG = 49,
+ DRAM_ALT_CLK_ROOT = 64,
+ DRAM_APB_CLK_ROOT = 65,
+ VPU_G1_CLK_ROOT = 66,
+ VPU_G2_CLK_ROOT = 67,
+ DISPLAY_DTRC_CLK_ROOT = 68,
+ DISPLAY_DC8000_CLK_ROOT = 69,
+ PCIE_CTRL_CLK_ROOT = 70,
+ PCIE_PHY_CLK_ROOT = 71,
+ PCIE_AUX_CLK_ROOT = 72,
+ DC_PIXEL_CLK_ROOT = 73,
+ LCDIF_PIXEL_CLK_ROOT = 74,
+ SAI1_CLK_ROOT = 75,
+ SAI2_CLK_ROOT = 76,
+ SAI3_CLK_ROOT = 77,
+ SAI4_CLK_ROOT = 78,
+ SAI5_CLK_ROOT = 79,
+ SAI6_CLK_ROOT = 80,
+ SPDIF1_CLK_ROOT = 81,
+ SPDIF2_CLK_ROOT = 82,
+ ENET_REF_CLK_ROOT = 83,
+ ENET_TIMER_CLK_ROOT = 84,
+ ENET_PHY_REF_CLK_ROOT = 85,
+ NAND_CLK_ROOT = 86,
+ QSPI_CLK_ROOT = 87,
+ USDHC1_CLK_ROOT = 88,
+ USDHC2_CLK_ROOT = 89,
+ I2C1_CLK_ROOT = 90,
+ I2C2_CLK_ROOT = 91,
+ I2C3_CLK_ROOT = 92,
+ I2C4_CLK_ROOT = 93,
+ UART1_CLK_ROOT = 94,
+ UART2_CLK_ROOT = 95,
+ UART3_CLK_ROOT = 96,
+ UART4_CLK_ROOT = 97,
+ USB_CORE_REF_CLK_ROOT = 98,
+ USB_PHY_REF_CLK_ROOT = 99,
+ GIC_CLK_ROOT = 100,
+ ECSPI1_CLK_ROOT = 101,
+ ECSPI2_CLK_ROOT = 102,
+ PWM1_CLK_ROOT = 103,
+ PWM2_CLK_ROOT = 104,
+ PWM3_CLK_ROOT = 105,
+ PWM4_CLK_ROOT = 106,
+ GPT1_CLK_ROOT = 107,
+ GPT2_CLK_ROOT = 108,
+ GPT3_CLK_ROOT = 109,
+ GPT4_CLK_ROOT = 110,
+ GPT5_CLK_ROOT = 111,
+ GPT6_CLK_ROOT = 112,
+ TRACE_CLK_ROOT = 113,
+ WDOG_CLK_ROOT = 114,
+ WRCLK_CLK_ROOT = 115,
+ IPP_DO_CLKO1 = 116,
+ IPP_DO_CLKO2 = 117,
+ MIPI_DSI_CORE_CLK_ROOT = 118,
+ MIPI_DSI_PHY_REF_CLK_ROOT = 119,
+ MIPI_DSI_DBI_CLK_ROOT = 120,
+ USDHC3_CLK_ROOT = 121,
+ MIPI_CSI1_CORE_CLK_ROOT = 122,
+ MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
+ MIPI_CSI1_ESC_CLK_ROOT = 124,
+ MIPI_CSI2_CORE_CLK_ROOT = 125,
+ MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
+ MIPI_CSI2_ESC_CLK_ROOT = 127,
+ PCIE2_CTRL_CLK_ROOT = 128,
+ PCIE2_PHY_CLK_ROOT = 129,
+ PCIE2_AUX_CLK_ROOT = 130,
+ ECSPI3_CLK_ROOT = 131,
+ PDM_CLK_ROOT = 132,
+ VPU_H1_CLK_ROOT = 133,
+ CLK_ROOT_MAX,
+};
+
+enum clk_root_src {
+ OSC_24M_CLK,
+ ARM_PLL_CLK,
+ DRAM_PLL1_CLK,
+ VIDEO_PLL2_CLK,
+ VPU_PLL_CLK,
+ GPU_PLL_CLK,
+ SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL1_266M_CLK,
+ SYSTEM_PLL1_200M_CLK,
+ SYSTEM_PLL1_160M_CLK,
+ SYSTEM_PLL1_133M_CLK,
+ SYSTEM_PLL1_100M_CLK,
+ SYSTEM_PLL1_80M_CLK,
+ SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL2_500M_CLK,
+ SYSTEM_PLL2_333M_CLK,
+ SYSTEM_PLL2_250M_CLK,
+ SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL2_166M_CLK,
+ SYSTEM_PLL2_125M_CLK,
+ SYSTEM_PLL2_100M_CLK,
+ SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL3_CLK,
+ AUDIO_PLL1_CLK,
+ AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK,
+ OSC_32K_CLK,
+ EXT_CLK_1,
+ EXT_CLK_2,
+ EXT_CLK_3,
+ EXT_CLK_4,
+ OSC_HDMI_CLK
+};
+
+enum clk_ccgr_index {
+ CCGR_DVFS = 0,
+ CCGR_ANAMIX = 1,
+ CCGR_CPU = 2,
+ CCGR_CSU = 3,
+ CCGR_DEBUG = 4,
+ CCGR_DDR1 = 5,
+ CCGR_ECSPI1 = 7,
+ CCGR_ECSPI2 = 8,
+ CCGR_ECSPI3 = 9,
+ CCGR_ENET1 = 10,
+ CCGR_GPIO1 = 11,
+ CCGR_GPIO2 = 12,
+ CCGR_GPIO3 = 13,
+ CCGR_GPIO4 = 14,
+ CCGR_GPIO5 = 15,
+ CCGR_GPT1 = 16,
+ CCGR_GPT2 = 17,
+ CCGR_GPT3 = 18,
+ CCGR_GPT4 = 19,
+ CCGR_GPT5 = 20,
+ CCGR_GPT6 = 21,
+ CCGR_HS = 22,
+ CCGR_I2C1 = 23,
+ CCGR_I2C2 = 24,
+ CCGR_I2C3 = 25,
+ CCGR_I2C4 = 26,
+ CCGR_IOMUX = 27,
+ CCGR_IOMUX1 = 28,
+ CCGR_IOMUX2 = 29,
+ CCGR_IOMUX3 = 30,
+ CCGR_IOMUX4 = 31,
+ CCGR_SNVSMIX_IPG_CLK = 32,
+ CCGR_MU = 33,
+ CCGR_OCOTP = 34,
+ CCGR_OCRAM = 35,
+ CCGR_OCRAM_S = 36,
+ CCGR_PCIE = 37,
+ CCGR_PERFMON1 = 38,
+ CCGR_PERFMON2 = 39,
+ CCGR_PWM1 = 40,
+ CCGR_PWM2 = 41,
+ CCGR_PWM3 = 42,
+ CCGR_PWM4 = 43,
+ CCGR_QOS = 44,
+ CCGR_QOS_DISPMIX = 45,
+ CCGR_QOS_ETHENET = 46,
+ CCGR_QSPI = 47,
+ CCGR_RAWNAND = 48,
+ CCGR_RDC = 49,
+ CCGR_ROM = 50,
+ CCGR_SAI1 = 51,
+ CCGR_SAI2 = 52,
+ CCGR_SAI3 = 53,
+ CCGR_SAI4 = 54,
+ CCGR_SAI5 = 55,
+ CCGR_SAI6 = 56,
+ CCGR_SCTR = 57,
+ CCGR_SDMA1 = 58,
+ CCGR_SDMA2 = 59,
+ CCGR_SEC_DEBUG = 60,
+ CCGR_SEMA1 = 61,
+ CCGR_SEMA2 = 62,
+ CCGR_SIM_DISPLAY = 63,
+ CCGR_SIM_ENET = 64,
+ CCGR_SIM_M = 65,
+ CCGR_SIM_MAIN = 66,
+ CCGR_SIM_S = 67,
+ CCGR_SIM_WAKEUP = 68,
+ CCGR_SIM_HSIO = 69,
+ CCGR_SIM_VPU = 70,
+ CCGR_SNVS = 71,
+ CCGR_TRACE = 72,
+ CCGR_UART1 = 73,
+ CCGR_UART2 = 74,
+ CCGR_UART3 = 75,
+ CCGR_UART4 = 76,
+ CCGR_USB_MSCALE_PL301 = 77,
+ CCGR_GPU3D = 79,
+ CCGR_USDHC1 = 81,
+ CCGR_USDHC2 = 82,
+ CCGR_WDOG1 = 83,
+ CCGR_WDOG2 = 84,
+ CCGR_WDOG3 = 85,
+ CCGR_VPUG1 = 86,
+ CCGR_GPU_BUS = 87,
+ CCGR_VPUH1 = 89,
+ CCGR_VPUG2 = 90,
+ CCGR_PDM = 91,
+ CCGR_GIC = 92,
+ CCGR_DISPMIX = 93,
+ CCGR_USDHC3 = 94,
+ CCGR_SDMA3 = 95,
+ CCGR_XTAL = 96,
+ CCGR_PLL = 97,
+ CCGR_TEMP_SENSOR = 98,
+ CCGR_VPUMIX_BUS = 99,
+ CCGR_GPU2D = 102,
+ CCGR_MAX
+};
+
+enum clk_src_index {
+ CLK_SRC_CKIL_SYNC_REQ = 0,
+ CLK_SRC_ARM_PLL_EN = 1,
+ CLK_SRC_GPU_PLL_EN = 2,
+ CLK_SRC_VPU_PLL_EN = 3,
+ CLK_SRC_DRAM_PLL_EN = 4,
+ CLK_SRC_SYSTEM_PLL1_EN = 5,
+ CLK_SRC_SYSTEM_PLL2_EN = 6,
+ CLK_SRC_SYSTEM_PLL3_EN = 7,
+ CLK_SRC_AUDIO_PLL1_EN = 8,
+ CLK_SRC_AUDIO_PLL2_EN = 9,
+ CLK_SRC_VIDEO_PLL1_EN = 10,
+ CLK_SRC_RESERVED = 11,
+ CLK_SRC_ARM_PLL = 12,
+ CLK_SRC_GPU_PLL = 13,
+ CLK_SRC_VPU_PLL = 14,
+ CLK_SRC_DRAM_PLL = 15,
+ CLK_SRC_SYSTEM_PLL1_800M = 16,
+ CLK_SRC_SYSTEM_PLL1_400M = 17,
+ CLK_SRC_SYSTEM_PLL1_266M = 18,
+ CLK_SRC_SYSTEM_PLL1_200M = 19,
+ CLK_SRC_SYSTEM_PLL1_160M = 20,
+ CLK_SRC_SYSTEM_PLL1_133M = 21,
+ CLK_SRC_SYSTEM_PLL1_100M = 22,
+ CLK_SRC_SYSTEM_PLL1_80M = 23,
+ CLK_SRC_SYSTEM_PLL1_40M = 24,
+ CLK_SRC_SYSTEM_PLL2_1000M = 25,
+ CLK_SRC_SYSTEM_PLL2_500M = 26,
+ CLK_SRC_SYSTEM_PLL2_333M = 27,
+ CLK_SRC_SYSTEM_PLL2_250M = 28,
+ CLK_SRC_SYSTEM_PLL2_200M = 29,
+ CLK_SRC_SYSTEM_PLL2_166M = 30,
+ CLK_SRC_SYSTEM_PLL2_125M = 31,
+ CLK_SRC_SYSTEM_PLL2_100M = 32,
+ CLK_SRC_SYSTEM_PLL2_50M = 33,
+ CLK_SRC_SYSTEM_PLL3 = 34,
+ CLK_SRC_AUDIO_PLL1 = 35,
+ CLK_SRC_AUDIO_PLL2 = 36,
+ CLK_SRC_VIDEO_PLL1 = 37,
+};
+
+#define INTPLL_LOCK_MASK BIT(31)
+#define INTPLL_LOCK_SEL_MASK BIT(29)
+#define INTPLL_EXT_BYPASS_MASK BIT(28)
+#define INTPLL_DIV20_CLKE_MASK BIT(27)
+#define INTPLL_DIV20_CLKE_OVERRIDE_MASK BIT(26)
+#define INTPLL_DIV10_CLKE_MASK BIT(25)
+#define INTPLL_DIV10_CLKE_OVERRIDE_MASK BIT(24)
+#define INTPLL_DIV8_CLKE_MASK BIT(23)
+#define INTPLL_DIV8_CLKE_OVERRIDE_MASK BIT(22)
+#define INTPLL_DIV6_CLKE_MASK BIT(21)
+#define INTPLL_DIV6_CLKE_OVERRIDE_MASK BIT(20)
+#define INTPLL_DIV5_CLKE_MASK BIT(19)
+#define INTPLL_DIV5_CLKE_OVERRIDE_MASK BIT(18)
+#define INTPLL_DIV4_CLKE_MASK BIT(17)
+#define INTPLL_DIV4_CLKE_OVERRIDE_MASK BIT(16)
+#define INTPLL_DIV3_CLKE_MASK BIT(15)
+#define INTPLL_DIV3_CLKE_OVERRIDE_MASK BIT(14)
+#define INTPLL_DIV2_CLKE_MASK BIT(13)
+#define INTPLL_DIV2_CLKE_OVERRIDE_MASK BIT(12)
+#define INTPLL_CLKE_MASK BIT(11)
+#define INTPLL_CLKE_OVERRIDE_MASK BIT(10)
+#define INTPLL_RST_MASK BIT(9)
+#define INTPLL_RST_OVERRIDE_MASK BIT(8)
+#define INTPLL_BYPASS_MASK BIT(4)
+#define INTPLL_PAD_CLK_SEL_MASK GENMASK(3, 2)
+#define INTPLL_REF_CLK_SEL_MASK GENMASK(1, 0)
+
+#define INTPLL_MAIN_DIV_MASK GENMASK(21, 12)
+#define INTPLL_MAIN_DIV_VAL(n) ((n << 12) & GENMASK(21, 12))
+#define INTPLL_MAIN_DIV_SHIFT 12
+#define INTPLL_PRE_DIV_MASK GENMASK(9, 4)
+#define INTPLL_PRE_DIV_VAL(n) ((n << 4) & GENMASK(9, 4))
+#define INTPLL_PRE_DIV_SHIFT 4
+#define INTPLL_POST_DIV_MASK GENMASK(2, 0)
+#define INTPLL_POST_DIV_VAL(n) ((n << 0) & GENMASK(2, 0))
+#define INTPLL_POST_DIV_SHIFT 0
+
+#define INTPLL_LOCK_CON_DLY_MASK GENMASK(5, 4)
+#define INTPLL_LOCK_CON_DLY_SHIFT 4
+#define INTPLL_LOCK_CON_OUT_MASK GENMASK(3, 2)
+#define INTPLL_LOCK_CON_OUT_SHIFT 2
+#define INTPLL_LOCK_CON_IN_MASK GENMASK(1, 0)
+#define INTPLL_LOCK_CON_IN_SHIFT 0
+
+#define INTPLL_LRD_EN_MASK BIT(21)
+#define INTPLL_FOUT_MASK BIT(20)
+#define INTPLL_AFC_SEL_MASK BIT(19)
+#define INTPLL_PBIAS_CTRL_MASK BIT(18)
+#define INTPLL_PBIAS_CTRL_EN_MASK BIT(17)
+#define INTPLL_AFCINIT_SEL_MASK BIT(16)
+#define INTPLL_FSEL_MASK BIT(14)
+#define INTPLL_FEED_EN_MASK BIT(13)
+#define INTPLL_EXTAFC_MASK GENMASK(7, 3)
+#define INTPLL_AFC_EN_MASK BIT(2)
+#define INTPLL_ICP_MASK GENMASK(1, 0)
+
+#endif
diff --git a/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
new file mode 100644
index 00000000000..9fa9eb26877
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/clock_imx8mq.h
@@ -0,0 +1,424 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2017 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#ifndef _ASM_ARCH_IMX8M_CLOCK_H
+#define _ASM_ARCH_IMX8M_CLOCK_H
+
+enum pll_clocks {
+ ANATOP_ARM_PLL,
+ ANATOP_GPU_PLL,
+ ANATOP_SYSTEM_PLL1,
+ ANATOP_SYSTEM_PLL2,
+ ANATOP_SYSTEM_PLL3,
+ ANATOP_AUDIO_PLL1,
+ ANATOP_AUDIO_PLL2,
+ ANATOP_VIDEO_PLL1,
+ ANATOP_VIDEO_PLL2,
+ ANATOP_DRAM_PLL,
+};
+
+enum clk_root_index {
+ ARM_A53_CLK_ROOT = 0,
+ ARM_M4_CLK_ROOT = 1,
+ VPU_A53_CLK_ROOT = 2,
+ GPU_CORE_CLK_ROOT = 3,
+ GPU_SHADER_CLK_ROOT = 4,
+ MAIN_AXI_CLK_ROOT = 16,
+ ENET_AXI_CLK_ROOT = 17,
+ NAND_USDHC_BUS_CLK_ROOT = 18,
+ VPU_BUS_CLK_ROOT = 19,
+ DISPLAY_AXI_CLK_ROOT = 20,
+ DISPLAY_APB_CLK_ROOT = 21,
+ DISPLAY_RTRM_CLK_ROOT = 22,
+ USB_BUS_CLK_ROOT = 23,
+ GPU_AXI_CLK_ROOT = 24,
+ GPU_AHB_CLK_ROOT = 25,
+ NOC_CLK_ROOT = 26,
+ NOC_APB_CLK_ROOT = 27,
+ AHB_CLK_ROOT = 32,
+ IPG_CLK_ROOT = 33,
+ AUDIO_AHB_CLK_ROOT = 34,
+ MIPI_DSI_ESC_RX_CLK_ROOT = 36,
+ DRAM_SEL_CFG = 48,
+ CORE_SEL_CFG = 49,
+ DRAM_ALT_CLK_ROOT = 64,
+ DRAM_APB_CLK_ROOT = 65,
+ VPU_G1_CLK_ROOT = 66,
+ VPU_G2_CLK_ROOT = 67,
+ DISPLAY_DTRC_CLK_ROOT = 68,
+ DISPLAY_DC8000_CLK_ROOT = 69,
+ PCIE1_CTRL_CLK_ROOT = 70,
+ PCIE1_PHY_CLK_ROOT = 71,
+ PCIE1_AUX_CLK_ROOT = 72,
+ DC_PIXEL_CLK_ROOT = 73,
+ LCDIF_PIXEL_CLK_ROOT = 74,
+ SAI1_CLK_ROOT = 75,
+ SAI2_CLK_ROOT = 76,
+ SAI3_CLK_ROOT = 77,
+ SAI4_CLK_ROOT = 78,
+ SAI5_CLK_ROOT = 79,
+ SAI6_CLK_ROOT = 80,
+ SPDIF1_CLK_ROOT = 81,
+ SPDIF2_CLK_ROOT = 82,
+ ENET_REF_CLK_ROOT = 83,
+ ENET_TIMER_CLK_ROOT = 84,
+ ENET_PHY_REF_CLK_ROOT = 85,
+ NAND_CLK_ROOT = 86,
+ QSPI_CLK_ROOT = 87,
+ USDHC1_CLK_ROOT = 88,
+ USDHC2_CLK_ROOT = 89,
+ I2C1_CLK_ROOT = 90,
+ I2C2_CLK_ROOT = 91,
+ I2C3_CLK_ROOT = 92,
+ I2C4_CLK_ROOT = 93,
+ UART1_CLK_ROOT = 94,
+ UART2_CLK_ROOT = 95,
+ UART3_CLK_ROOT = 96,
+ UART4_CLK_ROOT = 97,
+ USB_CORE_REF_CLK_ROOT = 98,
+ USB_PHY_REF_CLK_ROOT = 99,
+ GIC_CLK_ROOT = 100,
+ ECSPI1_CLK_ROOT = 101,
+ ECSPI2_CLK_ROOT = 102,
+ PWM1_CLK_ROOT = 103,
+ PWM2_CLK_ROOT = 104,
+ PWM3_CLK_ROOT = 105,
+ PWM4_CLK_ROOT = 106,
+ GPT1_CLK_ROOT = 107,
+ GPT2_CLK_ROOT = 108,
+ GPT3_CLK_ROOT = 109,
+ GPT4_CLK_ROOT = 110,
+ GPT5_CLK_ROOT = 111,
+ GPT6_CLK_ROOT = 112,
+ TRACE_CLK_ROOT = 113,
+ WDOG_CLK_ROOT = 114,
+ WRCLK_CLK_ROOT = 115,
+ IPP_DO_CLKO1 = 116,
+ IPP_DO_CLKO2 = 117,
+ MIPI_DSI_CORE_CLK_ROOT = 118,
+ MIPI_DSI_PHY_REF_CLK_ROOT = 119,
+ MIPI_DSI_DBI_CLK_ROOT = 120,
+ OLD_MIPI_DSI_ESC_CLK_ROOT = 121,
+ MIPI_CSI1_CORE_CLK_ROOT = 122,
+ MIPI_CSI1_PHY_REF_CLK_ROOT = 123,
+ MIPI_CSI1_ESC_CLK_ROOT = 124,
+ MIPI_CSI2_CORE_CLK_ROOT = 125,
+ MIPI_CSI2_PHY_REF_CLK_ROOT = 126,
+ MIPI_CSI2_ESC_CLK_ROOT = 127,
+ PCIE2_CTRL_CLK_ROOT = 128,
+ PCIE2_PHY_CLK_ROOT = 129,
+ PCIE2_AUX_CLK_ROOT = 130,
+ ECSPI3_CLK_ROOT = 131,
+ OLD_MIPI_DSI_ESC_RX_ROOT = 132,
+ DISPLAY_HDMI_CLK_ROOT = 133,
+ CLK_ROOT_MAX,
+};
+
+enum clk_root_src {
+ OSC_25M_CLK,
+ ARM_PLL_CLK,
+ DRAM_PLL1_CLK,
+ VIDEO_PLL2_CLK,
+ VPU_PLL_CLK,
+ GPU_PLL_CLK,
+ SYSTEM_PLL1_800M_CLK,
+ SYSTEM_PLL1_400M_CLK,
+ SYSTEM_PLL1_266M_CLK,
+ SYSTEM_PLL1_200M_CLK,
+ SYSTEM_PLL1_160M_CLK,
+ SYSTEM_PLL1_133M_CLK,
+ SYSTEM_PLL1_100M_CLK,
+ SYSTEM_PLL1_80M_CLK,
+ SYSTEM_PLL1_40M_CLK,
+ SYSTEM_PLL2_1000M_CLK,
+ SYSTEM_PLL2_500M_CLK,
+ SYSTEM_PLL2_333M_CLK,
+ SYSTEM_PLL2_250M_CLK,
+ SYSTEM_PLL2_200M_CLK,
+ SYSTEM_PLL2_166M_CLK,
+ SYSTEM_PLL2_125M_CLK,
+ SYSTEM_PLL2_100M_CLK,
+ SYSTEM_PLL2_50M_CLK,
+ SYSTEM_PLL3_CLK,
+ AUDIO_PLL1_CLK,
+ AUDIO_PLL2_CLK,
+ VIDEO_PLL_CLK,
+ OSC_32K_CLK,
+ EXT_CLK_1,
+ EXT_CLK_2,
+ EXT_CLK_3,
+ EXT_CLK_4,
+ OSC_27M_CLK,
+};
+
+/* CCGR index */
+enum clk_ccgr_index {
+ CCGR_DVFS = 0,
+ CCGR_ANAMIX = 1,
+ CCGR_CPU = 2,
+ CCGR_CSU = 4,
+ CCGR_DRAM1 = 5,
+ CCGR_DRAM2_OBSOLETE = 6,
+ CCGR_ECSPI1 = 7,
+ CCGR_ECSPI2 = 8,
+ CCGR_ECSPI3 = 9,
+ CCGR_ENET1 = 10,
+ CCGR_GPIO1 = 11,
+ CCGR_GPIO2 = 12,
+ CCGR_GPIO3 = 13,
+ CCGR_GPIO4 = 14,
+ CCGR_GPIO5 = 15,
+ CCGR_GPT1 = 16,
+ CCGR_GPT2 = 17,
+ CCGR_GPT3 = 18,
+ CCGR_GPT4 = 19,
+ CCGR_GPT5 = 20,
+ CCGR_GPT6 = 21,
+ CCGR_HS = 22,
+ CCGR_I2C1 = 23,
+ CCGR_I2C2 = 24,
+ CCGR_I2C3 = 25,
+ CCGR_I2C4 = 26,
+ CCGR_IOMUX = 27,
+ CCGR_IOMUX1 = 28,
+ CCGR_IOMUX2 = 29,
+ CCGR_IOMUX3 = 30,
+ CCGR_IOMUX4 = 31,
+ CCGR_M4 = 32,
+ CCGR_MU = 33,
+ CCGR_OCOTP = 34,
+ CCGR_OCRAM = 35,
+ CCGR_OCRAM_S = 36,
+ CCGR_PCIE = 37,
+ CCGR_PERFMON1 = 38,
+ CCGR_PERFMON2 = 39,
+ CCGR_PWM1 = 40,
+ CCGR_PWM2 = 41,
+ CCGR_PWM3 = 42,
+ CCGR_PWM4 = 43,
+ CCGR_QOS = 44,
+ CCGR_DISMIX = 45,
+ CCGR_MEGAMIX = 46,
+ CCGR_QSPI = 47,
+ CCGR_RAWNAND = 48,
+ CCGR_RDC = 49,
+ CCGR_ROM = 50,
+ CCGR_SAI1 = 51,
+ CCGR_SAI2 = 52,
+ CCGR_SAI3 = 53,
+ CCGR_SAI4 = 54,
+ CCGR_SAI5 = 55,
+ CCGR_SAI6 = 56,
+ CCGR_SCTR = 57,
+ CCGR_SDMA1 = 58,
+ CCGR_SDMA2 = 59,
+ CCGR_SEC_DEBUG = 60,
+ CCGR_SEMA1 = 61,
+ CCGR_SEMA2 = 62,
+ CCGR_SIM_DISPLAY = 63,
+ CCGR_SIM_ENET = 64,
+ CCGR_SIM_M = 65,
+ CCGR_SIM_MAIN = 66,
+ CCGR_SIM_S = 67,
+ CCGR_SIM_WAKEUP = 68,
+ CCGR_SIM_USB = 69,
+ CCGR_SIM_VPU = 70,
+ CCGR_SNVS = 71,
+ CCGR_TRACE = 72,
+ CCGR_UART1 = 73,
+ CCGR_UART2 = 74,
+ CCGR_UART3 = 75,
+ CCGR_UART4 = 76,
+ CCGR_USB_CTRL1 = 77,
+ CCGR_USB_CTRL2 = 78,
+ CCGR_USB_PHY1 = 79,
+ CCGR_USB_PHY2 = 80,
+ CCGR_USDHC1 = 81,
+ CCGR_USDHC2 = 82,
+ CCGR_WDOG1 = 83,
+ CCGR_WDOG2 = 84,
+ CCGR_WDOG3 = 85,
+ CCGR_VA53 = 86,
+ CCGR_GPU = 87,
+ CCGR_HEVC = 88,
+ CCGR_AVC = 89,
+ CCGR_VP9 = 90,
+ CCGR_HEVC_INTER = 91,
+ CCGR_GIC = 92,
+ CCGR_DISPLAY = 93,
+ CCGR_HDMI = 94,
+ CCGR_HDMI_PHY = 95,
+ CCGR_XTAL = 96,
+ CCGR_PLL = 97,
+ CCGR_TSENSOR = 98,
+ CCGR_VPU_DEC = 99,
+ CCGR_PCIE2 = 100,
+ CCGR_MIPI_CSI1 = 101,
+ CCGR_MIPI_CSI2 = 102,
+ CCGR_MAX,
+};
+
+/* src index */
+enum clk_src_index {
+ CLK_SRC_CKIL_SYNC_REQ = 0,
+ CLK_SRC_ARM_PLL_EN = 1,
+ CLK_SRC_GPU_PLL_EN = 2,
+ CLK_SRC_VPU_PLL_EN = 3,
+ CLK_SRC_DRAM_PLL_EN = 4,
+ CLK_SRC_SYSTEM_PLL1_EN = 5,
+ CLK_SRC_SYSTEM_PLL2_EN = 6,
+ CLK_SRC_SYSTEM_PLL3_EN = 7,
+ CLK_SRC_AUDIO_PLL1_EN = 8,
+ CLK_SRC_AUDIO_PLL2_EN = 9,
+ CLK_SRC_VIDEO_PLL1_EN = 10,
+ CLK_SRC_VIDEO_PLL2_EN = 11,
+ CLK_SRC_ARM_PLL = 12,
+ CLK_SRC_GPU_PLL = 13,
+ CLK_SRC_VPU_PLL = 14,
+ CLK_SRC_DRAM_PLL = 15,
+ CLK_SRC_SYSTEM_PLL1_800M = 16,
+ CLK_SRC_SYSTEM_PLL1_400M = 17,
+ CLK_SRC_SYSTEM_PLL1_266M = 18,
+ CLK_SRC_SYSTEM_PLL1_200M = 19,
+ CLK_SRC_SYSTEM_PLL1_160M = 20,
+ CLK_SRC_SYSTEM_PLL1_133M = 21,
+ CLK_SRC_SYSTEM_PLL1_100M = 22,
+ CLK_SRC_SYSTEM_PLL1_80M = 23,
+ CLK_SRC_SYSTEM_PLL1_40M = 24,
+ CLK_SRC_SYSTEM_PLL2_1000M = 25,
+ CLK_SRC_SYSTEM_PLL2_500M = 26,
+ CLK_SRC_SYSTEM_PLL2_333M = 27,
+ CLK_SRC_SYSTEM_PLL2_250M = 28,
+ CLK_SRC_SYSTEM_PLL2_200M = 29,
+ CLK_SRC_SYSTEM_PLL2_166M = 30,
+ CLK_SRC_SYSTEM_PLL2_125M = 31,
+ CLK_SRC_SYSTEM_PLL2_100M = 32,
+ CLK_SRC_SYSTEM_PLL2_50M = 33,
+ CLK_SRC_SYSTEM_PLL3 = 34,
+ CLK_SRC_AUDIO_PLL1 = 35,
+ CLK_SRC_AUDIO_PLL2 = 36,
+ CLK_SRC_VIDEO_PLL1 = 37,
+ CLK_SRC_VIDEO_PLL2 = 38,
+ CLK_SRC_OSC_25M = 39,
+ CLK_SRC_OSC_27M = 40,
+};
+
+/* AUDIO PLL1/2 VIDEO PLL1 GPU PLL VPU PLL ARM PLL*/
+#define FRAC_PLL_LOCK_MASK BIT(31)
+#define FRAC_PLL_CLKE_MASK BIT(21)
+#define FRAC_PLL_PD_MASK BIT(19)
+#define FRAC_PLL_REFCLK_SEL_MASK BIT(16)
+#define FRAC_PLL_LOCK_SEL_MASK BIT(15)
+#define FRAC_PLL_BYPASS_MASK BIT(14)
+#define FRAC_PLL_COUNTCLK_SEL_MASK BIT(13)
+#define FRAC_PLL_NEWDIV_VAL_MASK BIT(12)
+#define FRAC_PLL_NEWDIV_ACK_MASK BIT(11)
+#define FRAC_PLL_REFCLK_DIV_VAL(n) (((n) << 5) & (0x3f << 5))
+#define FRAC_PLL_REFCLK_DIV_VAL_MASK (0x3f << 5)
+#define FRAC_PLL_REFCLK_DIV_VAL_SHIFT 5
+#define FRAC_PLL_OUTPUT_DIV_VAL_MASK 0x1f
+#define FRAC_PLL_OUTPUT_DIV_VAL(n) ((n) & 0x1f)
+
+#define FRAC_PLL_REFCLK_SEL_OSC_25M (0 << 16)
+#define FRAC_PLL_REFCLK_SEL_OSC_27M BIT(16)
+#define FRAC_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
+#define FRAC_PLL_REFCLK_SEL_CLK_PN (3 << 16)
+
+#define FRAC_PLL_FRAC_DIV_CTL_MASK (0x1ffffff << 7)
+#define FRAC_PLL_FRAC_DIV_CTL_SHIFT 7
+#define FRAC_PLL_INT_DIV_CTL_MASK 0x7f
+#define FRAC_PLL_INT_DIV_CTL_VAL(n) ((n) & 0x7f)
+
+/* SYS PLL1/2/3 VIDEO PLL2 DRAM PLL */
+#define SSCG_PLL_LOCK_MASK BIT(31)
+#define SSCG_PLL_CLKE_MASK BIT(25)
+#define SSCG_PLL_DIV2_CLKE_MASK BIT(23)
+#define SSCG_PLL_DIV3_CLKE_MASK BIT(21)
+#define SSCG_PLL_DIV4_CLKE_MASK BIT(19)
+#define SSCG_PLL_DIV5_CLKE_MASK BIT(17)
+#define SSCG_PLL_DIV6_CLKE_MASK BIT(15)
+#define SSCG_PLL_DIV8_CLKE_MASK BIT(13)
+#define SSCG_PLL_DIV10_CLKE_MASK BIT(11)
+#define SSCG_PLL_DIV20_CLKE_MASK BIT(9)
+#define SSCG_PLL_VIDEO_PLL2_CLKE_MASK BIT(9)
+#define SSCG_PLL_DRAM_PLL_CLKE_MASK BIT(9)
+#define SSCG_PLL_PLL3_CLKE_MASK BIT(9)
+#define SSCG_PLL_PD_MASK BIT(7)
+#define SSCG_PLL_BYPASS1_MASK BIT(5)
+#define SSCG_PLL_BYPASS2_MASK BIT(4)
+#define SSCG_PLL_LOCK_SEL_MASK BIT(3)
+#define SSCG_PLL_COUNTCLK_SEL_MASK BIT(2)
+#define SSCG_PLL_REFCLK_SEL_MASK 0x3
+#define SSCG_PLL_REFCLK_SEL_OSC_25M (0 << 16)
+#define SSCG_PLL_REFCLK_SEL_OSC_27M BIT(16)
+#define SSCG_PLL_REFCLK_SEL_HDMI_PHY_27M (2 << 16)
+#define SSCG_PLL_REFCLK_SEL_CLK_PN (3 << 16)
+
+#define SSCG_PLL_SSDS_MASK BIT(8)
+#define SSCG_PLL_SSMD_MASK (0x7 << 5)
+#define SSCG_PLL_SSMF_MASK (0xf << 1)
+#define SSCG_PLL_SSE_MASK 0x1
+
+#define SSCG_PLL_REF_DIVR1_MASK (0x7 << 25)
+#define SSCG_PLL_REF_DIVR1_SHIFT 25
+#define SSCG_PLL_REF_DIVR1_VAL(n) (((n) << 25) & SSCG_PLL_REF_DIVR1_MASK)
+#define SSCG_PLL_REF_DIVR2_MASK (0x3f << 19)
+#define SSCG_PLL_REF_DIVR2_SHIFT 19
+#define SSCG_PLL_REF_DIVR2_VAL(n) (((n) << 19) & SSCG_PLL_REF_DIVR2_MASK)
+#define SSCG_PLL_FEEDBACK_DIV_F1_MASK (0x3f << 13)
+#define SSCG_PLL_FEEDBACK_DIV_F1_SHIFT 13
+#define SSCG_PLL_FEEDBACK_DIV_F1_VAL(n) (((n) << 13) & \
+ SSCG_PLL_FEEDBACK_DIV_F1_MASK)
+#define SSCG_PLL_FEEDBACK_DIV_F2_MASK (0x3f << 7)
+#define SSCG_PLL_FEEDBACK_DIV_F2_SHIFT 7
+#define SSCG_PLL_FEEDBACK_DIV_F2_VAL(n) (((n) << 7) & \
+ SSCG_PLL_FEEDBACK_DIV_F2_MASK)
+#define SSCG_PLL_OUTPUT_DIV_VAL_MASK (0x3f << 1)
+#define SSCG_PLL_OUTPUT_DIV_VAL_SHIFT 1
+#define SSCG_PLL_OUTPUT_DIV_VAL(n) (((n) << 1) & \
+ SSCG_PLL_OUTPUT_DIV_VAL_MASK)
+#define SSCG_PLL_FILTER_RANGE_MASK 0x1
+
+#define HW_DIGPROG_MAJOR_UPPER_MASK (0xff << 16)
+#define HW_DIGPROG_MAJOR_LOWER_MASK (0xff << 8)
+#define HW_DIGPROG_MINOR_MASK 0xff
+
+#define HW_OSC_27M_CLKE_MASK BIT(4)
+#define HW_OSC_25M_CLKE_MASK BIT(2)
+#define HW_OSC_32K_SEL_MASK 0x1
+#define HW_OSC_32K_SEL_RTC 0x1
+#define HW_OSC_32K_SEL_25M_DIV800 0x0
+
+#define HW_FRAC_ARM_PLL_DIV_MASK (0x7 << 20)
+#define HW_FRAC_ARM_PLL_DIV_SHIFT 20
+#define HW_FRAC_VPU_PLL_DIV_MASK (0x7 << 16)
+#define HW_FRAC_VPU_PLL_DIV_SHIFT 16
+#define HW_FRAC_GPU_PLL_DIV_MASK (0x7 << 12)
+#define HW_FRAC_GPU_PLL_DIV_SHIFT 12
+#define HW_FRAC_VIDEO_PLL1_DIV_MASK (0x7 << 10)
+#define HW_FRAC_VIDEO_PLL1_DIV_SHIFT 10
+#define HW_FRAC_AUDIO_PLL2_DIV_MASK (0x7 << 4)
+#define HW_FRAC_AUDIO_PLL2_DIV_SHIFT 4
+#define HW_FRAC_AUDIO_PLL1_DIV_MASK 0x7
+#define HW_FRAC_AUDIO_PLL1_DIV_SHIFT 0
+
+#define HW_SSCG_VIDEO_PLL2_DIV_MASK (0x7 << 16)
+#define HW_SSCG_VIDEO_PLL2_DIV_SHIFT 16
+#define HW_SSCG_DRAM_PLL_DIV_MASK (0x7 << 14)
+#define HW_SSCG_DRAM_PLL_DIV_SHIFT 14
+#define HW_SSCG_SYSTEM_PLL3_DIV_MASK (0x7 << 8)
+#define HW_SSCG_SYSTEM_PLL3_DIV_SHIFT 8
+#define HW_SSCG_SYSTEM_PLL2_DIV_MASK (0x7 << 4)
+#define HW_SSCG_SYSTEM_PLL2_DIV_SHIFT 4
+#define HW_SSCG_SYSTEM_PLL1_DIV_MASK 0x7
+#define HW_SSCG_SYSTEM_PLL1_DIV_SHIFT 0
+
+enum frac_pll_out_val {
+ FRAC_PLL_OUT_1000M,
+ FRAC_PLL_OUT_1600M,
+};
+#endif
diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h
index 68666a535b9..62640d996e4 100644
--- a/arch/arm/include/asm/arch-imx8m/imx-regs.h
+++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h
@@ -10,117 +10,49 @@
#include <asm/mach-imx/regs-lcdif.h>
-#define ROM_VERSION_A0 0x800
-#define ROM_VERSION_B0 0x83C
+#define ROM_VERSION_A0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x800 : 0x800
+#define ROM_VERSION_B0 IS_ENABLED(CONFIG_IMX8MQ) ? 0x83C : 0x800
-#define M4_BOOTROM_BASE_ADDR 0x007E0000
+#define M4_BOOTROM_BASE_ADDR 0x007E0000
-#define SAI1_BASE_ADDR 0x30010000
-#define SAI6_BASE_ADDR 0x30030000
-#define SAI5_BASE_ADDR 0x30040000
-#define SAI4_BASE_ADDR 0x30050000
-#define SPBA2_BASE_ADDR 0x300F0000
-#define AIPS1_BASE_ADDR 0x301F0000
#define GPIO1_BASE_ADDR 0X30200000
#define GPIO2_BASE_ADDR 0x30210000
#define GPIO3_BASE_ADDR 0x30220000
#define GPIO4_BASE_ADDR 0x30230000
#define GPIO5_BASE_ADDR 0x30240000
-#define ANA_TSENSOR_BASE_ADDR 0x30260000
-#define ANA_OSC_BASE_ADDR 0x30270000
#define WDOG1_BASE_ADDR 0x30280000
#define WDOG2_BASE_ADDR 0x30290000
#define WDOG3_BASE_ADDR 0x302A0000
-#define SDMA2_BASE_ADDR 0x302C0000
-#define GPT1_BASE_ADDR 0x302D0000
-#define GPT2_BASE_ADDR 0x302E0000
-#define GPT3_BASE_ADDR 0x302F0000
-#define ROMCP_BASE_ADDR 0x30310000
-#define LCDIF_BASE_ADDR 0x30320000
#define IOMUXC_BASE_ADDR 0x30330000
#define IOMUXC_GPR_BASE_ADDR 0x30340000
#define OCOTP_BASE_ADDR 0x30350000
#define ANATOP_BASE_ADDR 0x30360000
-#define SNVS_HP_BASE_ADDR 0x30370000
#define CCM_BASE_ADDR 0x30380000
#define SRC_BASE_ADDR 0x30390000
#define GPC_BASE_ADDR 0x303A0000
-#define SEMAPHORE1_BASE_ADDR 0x303B0000
-#define SEMAPHORE2_BASE_ADDR 0x303C0000
-#define RDC_BASE_ADDR 0x303D0000
-#define CSU_BASE_ADDR 0x303E0000
-#define AIPS2_BASE_ADDR 0x305F0000
-#define PWM1_BASE_ADDR 0x30660000
-#define PWM2_BASE_ADDR 0x30670000
-#define PWM3_BASE_ADDR 0x30680000
-#define PWM4_BASE_ADDR 0x30690000
#define SYSCNT_RD_BASE_ADDR 0x306A0000
#define SYSCNT_CMP_BASE_ADDR 0x306B0000
#define SYSCNT_CTRL_BASE_ADDR 0x306C0000
-#define GPT6_BASE_ADDR 0x306E0000
-#define GPT5_BASE_ADDR 0x306F0000
-#define GPT4_BASE_ADDR 0x30700000
-#define PERFMON1_BASE_ADDR 0x307C0000
-#define PERFMON2_BASE_ADDR 0x307D0000
-#define QOSC_BASE_ADDR 0x307F0000
-#define SPDIF1_BASE_ADDR 0x30810000
-#define ECSPI1_BASE_ADDR 0x30820000
-#define ECSPI2_BASE_ADDR 0x30830000
-#define ECSPI3_BASE_ADDR 0x30840000
#define UART1_BASE_ADDR 0x30860000
#define UART3_BASE_ADDR 0x30880000
#define UART2_BASE_ADDR 0x30890000
-#define SPDIF2_BASE_ADDR 0x308A0000
-#define SAI2_BASE_ADDR 0x308B0000
-#define SAI3_BASE_ADDR 0x308C0000
-#define SPBA1_BASE_ADDR 0x308F0000
-#define CAAM_BASE_ADDR 0x30900000
-#define AIPS3_BASE_ADDR 0x309F0000
-#define MIPI_PHY_BASE_ADDR 0x30A00000
-#define MIPI_DSI_BASE_ADDR 0x30A10000
#define I2C1_BASE_ADDR 0x30A20000
#define I2C2_BASE_ADDR 0x30A30000
#define I2C3_BASE_ADDR 0x30A40000
#define I2C4_BASE_ADDR 0x30A50000
#define UART4_BASE_ADDR 0x30A60000
-#define MIPI_CSI_BASE_ADDR 0x30A70000
-#define MIPI_CSI_PHY1_BASE_ADDR 0x30A80000
-#define CSI1_BASE_ADDR 0x30A90000
-#define MU_A_BASE_ADDR 0x30AA0000
-#define MU_B_BASE_ADDR 0x30AB0000
-#define SEMAPHOR_HS_BASE_ADDR 0x30AC0000
#define USDHC1_BASE_ADDR 0x30B40000
#define USDHC2_BASE_ADDR 0x30B50000
-#define MIPI_CS2_BASE_ADDR 0x30B60000
-#define MIPI_CSI_PHY2_BASE_ADDR 0x30B70000
-#define CSI2_BASE_ADDR 0x30B80000
-#define QSPI0_BASE_ADDR 0x30BB0000
-#define QSPI0_AMBA_BASE 0x08000000
-#define SDMA1_BASE_ADDR 0x30BD0000
-#define ENET1_BASE_ADDR 0x30BE0000
+#ifdef CONFIG_IMX8MM
+#define USDHC3_BASE_ADDR 0x30B60000
+#endif
-#define HDMI_CTRL_BASE_ADDR 0x32C00000
-#define AIPS4_BASE_ADDR 0x32DF0000
-#define DC1_BASE_ADDR 0x32E00000
-#define DC2_BASE_ADDR 0x32E10000
-#define DC3_BASE_ADDR 0x32E20000
-#define HDMI_SEC_BASE_ADDR 0x32E40000
#define TZASC_BASE_ADDR 0x32F80000
-#define MTR_BASE_ADDR 0x32FB0000
-#define PLATFORM_CTRL_BASE_ADDR 0x32FE0000
-
-#define MXS_APBH_BASE 0x33000000
-#define MXS_GPMI_BASE 0x33002000
-#define MXS_BCH_BASE 0x33004000
-
-#define USB1_BASE_ADDR 0x38100000
-#define USB2_BASE_ADDR 0x38200000
-#define USB1_PHY_BASE_ADDR 0x381F0000
-#define USB2_PHY_BASE_ADDR 0x382F0000
-#define MXS_LCDIF_BASE LCDIF_BASE_ADDR
+#define MXS_LCDIF_BASE IS_ENABLED(CONFIG_IMX8MQ) ? \
+ 0x30320000 : 0x32e00000
#define SRC_IPS_BASE_ADDR 0x30390000
#define SRC_DDRC_RCR_ADDR 0x30391000
@@ -205,6 +137,7 @@ struct fuse_bank1_regs {
u32 rsvd3[3];
};
+#ifdef CONFIG_IMX8MQ
struct anamix_pll {
u32 audio_pll1_cfg0;
u32 audio_pll1_cfg1;
@@ -239,6 +172,60 @@ struct anamix_pll {
u32 frac_pllout_div_cfg;
u32 sscg_pllout_div_cfg;
};
+#else
+struct anamix_pll {
+ u32 audio_pll1_gnrl_ctl;
+ u32 audio_pll1_fdiv_ctl0;
+ u32 audio_pll1_fdiv_ctl1;
+ u32 audio_pll1_sscg_ctl;
+ u32 audio_pll1_mnit_ctl;
+ u32 audio_pll2_gnrl_ctl;
+ u32 audio_pll2_fdiv_ctl0;
+ u32 audio_pll2_fdiv_ctl1;
+ u32 audio_pll2_sscg_ctl;
+ u32 audio_pll2_mnit_ctl;
+ u32 video_pll1_gnrl_ctl;
+ u32 video_pll1_fdiv_ctl0;
+ u32 video_pll1_fdiv_ctl1;
+ u32 video_pll1_sscg_ctl;
+ u32 video_pll1_mnit_ctl;
+ u32 reserved[5];
+ u32 dram_pll_gnrl_ctl;
+ u32 dram_pll_fdiv_ctl0;
+ u32 dram_pll_fdiv_ctl1;
+ u32 dram_pll_sscg_ctl;
+ u32 dram_pll_mnit_ctl;
+ u32 gpu_pll_gnrl_ctl;
+ u32 gpu_pll_div_ctl;
+ u32 gpu_pll_locked_ctl1;
+ u32 gpu_pll_mnit_ctl;
+ u32 vpu_pll_gnrl_ctl;
+ u32 vpu_pll_div_ctl;
+ u32 vpu_pll_locked_ctl1;
+ u32 vpu_pll_mnit_ctl;
+ u32 arm_pll_gnrl_ctl;
+ u32 arm_pll_div_ctl;
+ u32 arm_pll_locked_ctl1;
+ u32 arm_pll_mnit_ctl;
+ u32 sys_pll1_gnrl_ctl;
+ u32 sys_pll1_div_ctl;
+ u32 sys_pll1_locked_ctl1;
+ u32 reserved2[24];
+ u32 sys_pll1_mnit_ctl;
+ u32 sys_pll2_gnrl_ctl;
+ u32 sys_pll2_div_ctl;
+ u32 sys_pll2_locked_ctl1;
+ u32 sys_pll2_mnit_ctl;
+ u32 sys_pll3_gnrl_ctl;
+ u32 sys_pll3_div_ctl;
+ u32 sys_pll3_locked_ctl1;
+ u32 sys_pll3_mnit_ctl;
+ u32 anamix_misc_ctl;
+ u32 anamix_clk_mnit_ctl;
+ u32 reserved3[437];
+ u32 digprog;
+};
+#endif
struct fuse_bank9_regs {
u32 mac_addr0;
@@ -288,155 +275,6 @@ struct src {
u32 ddr2_rcr;
};
-struct gpc_reg {
- u32 lpcr_bsc;
- u32 lpcr_ad;
- u32 lpcr_cpu1;
- u32 lpcr_cpu2;
- u32 lpcr_cpu3;
- u32 slpcr;
- u32 mst_cpu_mapping;
- u32 mmdc_cpu_mapping;
- u32 mlpcr;
- u32 pgc_ack_sel;
- u32 pgc_ack_sel_m4;
- u32 gpc_misc;
- u32 imr1_core0;
- u32 imr2_core0;
- u32 imr3_core0;
- u32 imr4_core0;
- u32 imr1_core1;
- u32 imr2_core1;
- u32 imr3_core1;
- u32 imr4_core1;
- u32 imr1_cpu1;
- u32 imr2_cpu1;
- u32 imr3_cpu1;
- u32 imr4_cpu1;
- u32 imr1_cpu3;
- u32 imr2_cpu3;
- u32 imr3_cpu3;
- u32 imr4_cpu3;
- u32 isr1_cpu0;
- u32 isr2_cpu0;
- u32 isr3_cpu0;
- u32 isr4_cpu0;
- u32 isr1_cpu1;
- u32 isr2_cpu1;
- u32 isr3_cpu1;
- u32 isr4_cpu1;
- u32 isr1_cpu2;
- u32 isr2_cpu2;
- u32 isr3_cpu2;
- u32 isr4_cpu2;
- u32 isr1_cpu3;
- u32 isr2_cpu3;
- u32 isr3_cpu3;
- u32 isr4_cpu3;
- u32 slt0_cfg;
- u32 slt1_cfg;
- u32 slt2_cfg;
- u32 slt3_cfg;
- u32 slt4_cfg;
- u32 slt5_cfg;
- u32 slt6_cfg;
- u32 slt7_cfg;
- u32 slt8_cfg;
- u32 slt9_cfg;
- u32 slt10_cfg;
- u32 slt11_cfg;
- u32 slt12_cfg;
- u32 slt13_cfg;
- u32 slt14_cfg;
- u32 pgc_cpu_0_1_mapping;
- u32 cpu_pgc_up_trg;
- u32 mix_pgc_up_trg;
- u32 pu_pgc_up_trg;
- u32 cpu_pgc_dn_trg;
- u32 mix_pgc_dn_trg;
- u32 pu_pgc_dn_trg;
- u32 lpcr_bsc2;
- u32 pgc_cpu_2_3_mapping;
- u32 lps_cpu0;
- u32 lps_cpu1;
- u32 lps_cpu2;
- u32 lps_cpu3;
- u32 gpc_gpr;
- u32 gtor;
- u32 debug_addr1;
- u32 debug_addr2;
- u32 cpu_pgc_up_status1;
- u32 mix_pgc_up_status0;
- u32 mix_pgc_up_status1;
- u32 mix_pgc_up_status2;
- u32 m4_mix_pgc_up_status0;
- u32 m4_mix_pgc_up_status1;
- u32 m4_mix_pgc_up_status2;
- u32 pu_pgc_up_status0;
- u32 pu_pgc_up_status1;
- u32 pu_pgc_up_status2;
- u32 m4_pu_pgc_up_status0;
- u32 m4_pu_pgc_up_status1;
- u32 m4_pu_pgc_up_status2;
- u32 a53_lp_io_0;
- u32 a53_lp_io_1;
- u32 a53_lp_io_2;
- u32 cpu_pgc_dn_status1;
- u32 mix_pgc_dn_status0;
- u32 mix_pgc_dn_status1;
- u32 mix_pgc_dn_status2;
- u32 m4_mix_pgc_dn_status0;
- u32 m4_mix_pgc_dn_status1;
- u32 m4_mix_pgc_dn_status2;
- u32 pu_pgc_dn_status0;
- u32 pu_pgc_dn_status1;
- u32 pu_pgc_dn_status2;
- u32 m4_pu_pgc_dn_status0;
- u32 m4_pu_pgc_dn_status1;
- u32 m4_pu_pgc_dn_status2;
- u32 res[3];
- u32 mix_pdn_flg;
- u32 pu_pdn_flg;
- u32 m4_mix_pdn_flg;
- u32 m4_pu_pdn_flg;
- u32 imr1_core2;
- u32 imr2_core2;
- u32 imr3_core2;
- u32 imr4_core2;
- u32 imr1_core3;
- u32 imr2_core3;
- u32 imr3_core3;
- u32 imr4_core3;
- u32 pgc_ack_sel_pu;
- u32 pgc_ack_sel_m4_pu;
- u32 slt15_cfg;
- u32 slt16_cfg;
- u32 slt17_cfg;
- u32 slt18_cfg;
- u32 slt19_cfg;
- u32 gpc_pu_pwrhsk;
- u32 slt0_cfg_pu;
- u32 slt1_cfg_pu;
- u32 slt2_cfg_pu;
- u32 slt3_cfg_pu;
- u32 slt4_cfg_pu;
- u32 slt5_cfg_pu;
- u32 slt6_cfg_pu;
- u32 slt7_cfg_pu;
- u32 slt8_cfg_pu;
- u32 slt9_cfg_pu;
- u32 slt10_cfg_pu;
- u32 slt11_cfg_pu;
- u32 slt12_cfg_pu;
- u32 slt13_cfg_pu;
- u32 slt14_cfg_pu;
- u32 slt15_cfg_pu;
- u32 slt16_cfg_pu;
- u32 slt17_cfg_pu;
- u32 slt18_cfg_pu;
- u32 slt19_cfg_pu;
-};
-
#define WDOG_WDT_MASK BIT(3)
#define WDOG_WDZST_MASK BIT(0)
struct wdog_regs {
@@ -459,7 +297,8 @@ struct bootrom_sw_info {
u32 reserved_3[3];
};
-#define ROM_SW_INFO_ADDR_B0 0x00000968
+#define ROM_SW_INFO_ADDR_B0 (IS_ENABLED(CONFIG_IMX8MQ) ? 0x00000968 :\
+ 0x000009e8)
#define ROM_SW_INFO_ADDR_A0 0x000009e8
#define ROM_SW_INFO_ADDR is_soc_rev(CHIP_REV_1_0) ? \
diff --git a/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h b/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h
new file mode 100644
index 00000000000..210e96e1dbe
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/imx8mm_pins.h
@@ -0,0 +1,691 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018-2019 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX8MM_PINS_H__
+#define __ASM_ARCH_IMX8MM_PINS_H__
+
+#include <asm/mach-imx/iomux-v3.h>
+
+enum {
+ IMX8MM_PAD_GPIO1_IO00_GPIO1_IO0 = IOMUX_PAD(0x0290, 0x0028, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO00_CCM_ENET_PHY_REF_CLK_ROOT = IOMUX_PAD(0x0290, 0x0028, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO00_XTALOSC_REF_CLK_32K = IOMUX_PAD(0x0290, 0x0028, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO00_CCM_EXT_CLK1 = IOMUX_PAD(0x0290, 0x0028, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO01_GPIO1_IO1 = IOMUX_PAD(0x0294, 0x002C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO01_PWM1_OUT = IOMUX_PAD(0x0294, 0x002C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO01_XTALOSC_REF_CLK_24M = IOMUX_PAD(0x0294, 0x002C, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO01_CCM_EXT_CLK2 = IOMUX_PAD(0x0294, 0x002C, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO02_GPIO1_IO2 = IOMUX_PAD(0x0298, 0x0030, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_B = IOMUX_PAD(0x0298, 0x0030, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO02_WDOG1_WDOG_ANY = IOMUX_PAD(0x0298, 0x0030, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO03_GPIO1_IO3 = IOMUX_PAD(0x029C, 0x0034, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO03_USDHC1_VSELECT = IOMUX_PAD(0x029C, 0x0034, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO03_SDMA1_EXT_EVENT0 = IOMUX_PAD(0x029C, 0x0034, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO04_GPIO1_IO4 = IOMUX_PAD(0x02A0, 0x0038, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO04_USDHC2_VSELECT = IOMUX_PAD(0x02A0, 0x0038, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO04_SDMA1_EXT_EVENT1 = IOMUX_PAD(0x02A0, 0x0038, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO05_GPIO1_IO5 = IOMUX_PAD(0x02A4, 0x003C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO05_ARM_PLATFORM_M4_NMI = IOMUX_PAD(0x02A4, 0x003C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO05_CCM_PMIC_READY = IOMUX_PAD(0x02A4, 0x003C, 5, 0x04BC, 0, 0),
+ IMX8MM_PAD_GPIO1_IO05_SRC_INT_BOOT = IOMUX_PAD(0x02A4, 0x003C, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO06_GPIO1_IO6 = IOMUX_PAD(0x02A8, 0x0040, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO06_ENET1_MDC = IOMUX_PAD(0x02A8, 0x0040, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO06_USDHC1_CD_B = IOMUX_PAD(0x02A8, 0x0040, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO06_CCM_EXT_CLK3 = IOMUX_PAD(0x02A8, 0x0040, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO07_GPIO1_IO7 = IOMUX_PAD(0x02AC, 0x0044, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO07_ENET1_MDIO = IOMUX_PAD(0x02AC, 0x0044, 1, 0x04C0, 0, 0),
+ IMX8MM_PAD_GPIO1_IO07_USDHC1_WP = IOMUX_PAD(0x02AC, 0x0044, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO07_CCM_EXT_CLK4 = IOMUX_PAD(0x02AC, 0x0044, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO08_GPIO1_IO8 = IOMUX_PAD(0x02B0, 0x0048, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO08_ENET1_1588_EVENT0_IN = IOMUX_PAD(0x02B0, 0x0048, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO08_USDHC2_RESET_B = IOMUX_PAD(0x02B0, 0x0048, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO08_CCM_WAIT = IOMUX_PAD(0x02B0, 0x0048, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO09_GPIO1_IO9 = IOMUX_PAD(0x02B4, 0x004C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO09_ENET1_1588_EVENT0_OUT = IOMUX_PAD(0x02B4, 0x004C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO09_USDHC3_RESET_B = IOMUX_PAD(0x02B4, 0x004C, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO09_SDMA2_EXT_EVENT0 = IOMUX_PAD(0x02B4, 0x004C, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO09_CCM_STOP = IOMUX_PAD(0x02B4, 0x004C, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO10_GPIO1_IO10 = IOMUX_PAD(0x02B8, 0x0050, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO10_USB1_OTG_ID = IOMUX_PAD(0x02B8, 0x0050, 1, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO11_GPIO1_IO11 = IOMUX_PAD(0x02BC, 0x0054, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO11_USB2_OTG_ID = IOMUX_PAD(0x02BC, 0x0054, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO11_USDHC3_VSELECT = IOMUX_PAD(0x02BC, 0x0054, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO11_CCM_PMIC_READY = IOMUX_PAD(0x02BC, 0x0054, 5, 0x04BC, 1, 0),
+ IMX8MM_PAD_GPIO1_IO11_CCM_OUT0 = IOMUX_PAD(0x02BC, 0x0054, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO12_GPIO1_IO12 = IOMUX_PAD(0x02C0, 0x0058, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO12_USB1_OTG_PWR = IOMUX_PAD(0x02C0, 0x0058, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO12_SDMA2_EXT_EVENT1 = IOMUX_PAD(0x02C0, 0x0058, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO12_CCM_OUT1 = IOMUX_PAD(0x02C0, 0x0058, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO13_GPIO1_IO13 = IOMUX_PAD(0x02C4, 0x005C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO13_USB1_OTG_OC = IOMUX_PAD(0x02C4, 0x005C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO13_PWM2_OUT = IOMUX_PAD(0x02C4, 0x005C, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO13_CCM_OUT2 = IOMUX_PAD(0x02C4, 0x005C, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO14_GPIO1_IO14 = IOMUX_PAD(0x02C8, 0x0060, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO14_USB2_OTG_PWR = IOMUX_PAD(0x02C8, 0x0060, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO14_USDHC3_CD_B = IOMUX_PAD(0x02C8, 0x0060, 4, 0x0544, 2, 0),
+ IMX8MM_PAD_GPIO1_IO14_PWM3_OUT = IOMUX_PAD(0x02C8, 0x0060, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO14_CCM_CLKO1 = IOMUX_PAD(0x02C8, 0x0060, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_GPIO1_IO15_GPIO1_IO15 = IOMUX_PAD(0x02CC, 0x0064, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO15_USB2_OTG_OC = IOMUX_PAD(0x02CC, 0x0064, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO15_USDHC3_WP = IOMUX_PAD(0x02CC, 0x0064, 4, 0x0548, 2, 0),
+ IMX8MM_PAD_GPIO1_IO15_PWM4_OUT = IOMUX_PAD(0x02CC, 0x0064, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_GPIO1_IO15_CCM_CLKO2 = IOMUX_PAD(0x02CC, 0x0064, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_MDC_ENET1_MDC = IOMUX_PAD(0x02D0, 0x0068, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_MDC_GPIO1_IO16 = IOMUX_PAD(0x02D0, 0x0068, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_MDIO_ENET1_MDIO = IOMUX_PAD(0x02D4, 0x006C, 0, 0x04C0, 1, 0),
+ IMX8MM_PAD_ENET_MDIO_GPIO1_IO17 = IOMUX_PAD(0x02D4, 0x006C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_TD3_ENET1_RGMII_TD3 = IOMUX_PAD(0x02D8, 0x0070, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_TD3_GPIO1_IO18 = IOMUX_PAD(0x02D8, 0x0070, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_TD2_ENET1_RGMII_TD2 = IOMUX_PAD(0x02DC, 0x0074, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_TD2_ENET1_TX_CLK = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_TD2_CCM_ENET_REF_CLK_ROOT = IOMUX_PAD(0x02DC, 0x0074, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_TD2_GPIO1_IO19 = IOMUX_PAD(0x02DC, 0x0074, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_TD1_ENET1_RGMII_TD1 = IOMUX_PAD(0x02E0, 0x0078, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_TD1_GPIO1_IO20 = IOMUX_PAD(0x02E0, 0x0078, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_TD0_ENET1_RGMII_TD0 = IOMUX_PAD(0x02E4, 0x007C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_TD0_GPIO1_IO21 = IOMUX_PAD(0x02E4, 0x007C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_TX_CTL_ENET1_RGMII_TX_CTL = IOMUX_PAD(0x02E8, 0x0080, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_TX_CTL_GPIO1_IO22 = IOMUX_PAD(0x02E8, 0x0080, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_TXC_ENET1_RGMII_TXC = IOMUX_PAD(0x02EC, 0x0084, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_TXC_ENET1_TX_ER = IOMUX_PAD(0x02EC, 0x0084, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_TXC_GPIO1_IO23 = IOMUX_PAD(0x02EC, 0x0084, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_RX_CTL_ENET1_RGMII_RX_CTL = IOMUX_PAD(0x02F0, 0x0088, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_RX_CTL_GPIO1_IO24 = IOMUX_PAD(0x02F0, 0x0088, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_RXC_ENET1_RGMII_RXC = IOMUX_PAD(0x02F4, 0x008C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_RXC_ENET1_RX_ER = IOMUX_PAD(0x02F4, 0x008C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_RXC_GPIO1_IO25 = IOMUX_PAD(0x02F4, 0x008C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_RD0_ENET1_RGMII_RD0 = IOMUX_PAD(0x02F8, 0x0090, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_RD0_GPIO1_IO26 = IOMUX_PAD(0x02F8, 0x0090, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_RD1_ENET1_RGMII_RD1 = IOMUX_PAD(0x02FC, 0x0094, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_RD1_GPIO1_IO27 = IOMUX_PAD(0x02FC, 0x0094, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_RD2_ENET1_RGMII_RD2 = IOMUX_PAD(0x0300, 0x0098, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_RD2_GPIO1_IO28 = IOMUX_PAD(0x0300, 0x0098, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ENET_RD3_ENET1_RGMII_RD3 = IOMUX_PAD(0x0304, 0x009C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ENET_RD3_GPIO1_IO29 = IOMUX_PAD(0x0304, 0x009C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_CLK_USDHC1_CLK = IOMUX_PAD(0x0308, 0x00A0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_CLK_GPIO2_IO0 = IOMUX_PAD(0x0308, 0x00A0, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_CMD_USDHC1_CMD = IOMUX_PAD(0x030C, 0x00A4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_CMD_GPIO2_IO1 = IOMUX_PAD(0x030C, 0x00A4, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_DATA0_USDHC1_DATA0 = IOMUX_PAD(0x0310, 0x00A8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_DATA0_GPIO2_IO2 = IOMUX_PAD(0x0310, 0x00A8, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_DATA1_USDHC1_DATA1 = IOMUX_PAD(0x0314, 0x00AC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_DATA1_GPIO2_IO3 = IOMUX_PAD(0x0314, 0x00AC, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_DATA2_USDHC1_DATA2 = IOMUX_PAD(0x0318, 0x00B0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_DATA2_GPIO2_IO4 = IOMUX_PAD(0x0318, 0x00B0, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_DATA3_USDHC1_DATA3 = IOMUX_PAD(0x031C, 0x00B4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_DATA3_GPIO2_IO5 = IOMUX_PAD(0x031C, 0x00B4, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_DATA4_USDHC1_DATA4 = IOMUX_PAD(0x0320, 0x00B8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_DATA4_GPIO2_IO6 = IOMUX_PAD(0x0320, 0x00B8, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_DATA5_USDHC1_DATA5 = IOMUX_PAD(0x0324, 0x00BC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_DATA5_GPIO2_IO7 = IOMUX_PAD(0x0324, 0x00BC, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_DATA6_USDHC1_DATA6 = IOMUX_PAD(0x0328, 0x00C0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_DATA6_GPIO2_IO8 = IOMUX_PAD(0x0328, 0x00C0, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_DATA7_USDHC1_DATA7 = IOMUX_PAD(0x032C, 0x00C4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_DATA7_GPIO2_IO9 = IOMUX_PAD(0x032C, 0x00C4, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_RESET_B_USDHC1_RESET_B = IOMUX_PAD(0x0330, 0x00C8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_RESET_B_GPIO2_IO10 = IOMUX_PAD(0x0330, 0x00C8, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD1_STROBE_USDHC1_STROBE = IOMUX_PAD(0x0334, 0x00CC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD1_STROBE_GPIO2_IO11 = IOMUX_PAD(0x0334, 0x00CC, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD2_CD_B_USDHC2_CD_B = IOMUX_PAD(0x0338, 0x00D0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_CD_B_GPIO2_IO12 = IOMUX_PAD(0x0338, 0x00D0, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD2_CLK_USDHC2_CLK = IOMUX_PAD(0x033C, 0x00D4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_CLK_GPIO2_IO13 = IOMUX_PAD(0x033C, 0x00D4, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_CLK_CCM_OBSERVE0 = IOMUX_PAD(0x033C, 0x00D4, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD2_CMD_USDHC2_CMD = IOMUX_PAD(0x0340, 0x00D8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_CMD_GPIO2_IO14 = IOMUX_PAD(0x0340, 0x00D8, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_CMD_CCM_OBSERVE1 = IOMUX_PAD(0x0340, 0x00D8, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD2_DATA0_USDHC2_DATA0 = IOMUX_PAD(0x0344, 0x00DC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_DATA0_GPIO2_IO15 = IOMUX_PAD(0x0344, 0x00DC, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_DATA0_CCM_OBSERVE2 = IOMUX_PAD(0x0344, 0x00DC, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD2_DATA1_USDHC2_DATA1 = IOMUX_PAD(0x0348, 0x00E0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_DATA1_GPIO2_IO16 = IOMUX_PAD(0x0348, 0x00E0, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_DATA1_CCM_WAIT = IOMUX_PAD(0x0348, 0x00E0, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD2_DATA2_USDHC2_DATA2 = IOMUX_PAD(0x034C, 0x00E4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_DATA2_GPIO2_IO17 = IOMUX_PAD(0x034C, 0x00E4, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_DATA2_CCM_STOP = IOMUX_PAD(0x034C, 0x00E4, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD2_DATA3_USDHC2_DATA3 = IOMUX_PAD(0x0350, 0x00E8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_DATA3_GPIO2_IO18 = IOMUX_PAD(0x0350, 0x00E8, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_DATA3_SRC_EARLY_RESET = IOMUX_PAD(0x0350, 0x00E8, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD2_RESET_B_USDHC2_RESET_B = IOMUX_PAD(0x0354, 0x00EC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_RESET_B_GPIO2_IO19 = IOMUX_PAD(0x0354, 0x00EC, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_RESET_B_SRC_SYSTEM_RESET = IOMUX_PAD(0x0354, 0x00EC, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SD2_WP_USDHC2_WP = IOMUX_PAD(0x0358, 0x00F0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SD2_WP_GPIO2_IO20 = IOMUX_PAD(0x0358, 0x00F0, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_ALE_RAWNAND_ALE = IOMUX_PAD(0x035C, 0x00F4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_ALE_QSPI_A_SCLK = IOMUX_PAD(0x035C, 0x00F4, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_ALE_GPIO3_IO0 = IOMUX_PAD(0x035C, 0x00F4, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_CE0_B_RAWNAND_CE0_B = IOMUX_PAD(0x0360, 0x00F8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE0_B_QSPI_A_SS0_B = IOMUX_PAD(0x0360, 0x00F8, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE0_B_GPIO3_IO1 = IOMUX_PAD(0x0360, 0x00F8, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_CE1_B_RAWNAND_CE1_B = IOMUX_PAD(0x0364, 0x00FC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE1_B_QSPI_A_SS1_B = IOMUX_PAD(0x0364, 0x00FC, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE1_B_USDHC3_STROBE = IOMUX_PAD(0x0364, 0x00FC, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE1_B_GPIO3_IO2 = IOMUX_PAD(0x0364, 0x00FC, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_CE2_B_RAWNAND_CE2_B = IOMUX_PAD(0x0368, 0x0100, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE2_B_QSPI_B_SS0_B = IOMUX_PAD(0x0368, 0x0100, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE2_B_USDHC3_DATA5 = IOMUX_PAD(0x0368, 0x0100, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE2_B_GPIO3_IO3 = IOMUX_PAD(0x0368, 0x0100, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_CE3_B_RAWNAND_CE3_B = IOMUX_PAD(0x036C, 0x0104, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE3_B_QSPI_B_SS1_B = IOMUX_PAD(0x036C, 0x0104, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE3_B_USDHC3_DATA6 = IOMUX_PAD(0x036C, 0x0104, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CE3_B_GPIO3_IO4 = IOMUX_PAD(0x036C, 0x0104, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_CLE_RAWNAND_CLE = IOMUX_PAD(0x0370, 0x0108, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CLE_QSPI_B_SCLK = IOMUX_PAD(0x0370, 0x0108, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CLE_USDHC3_DATA7 = IOMUX_PAD(0x0370, 0x0108, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_CLE_GPIO3_IO5 = IOMUX_PAD(0x0370, 0x0108, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_DATA00_RAWNAND_DATA00 = IOMUX_PAD(0x0374, 0x010C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA00_QSPI_A_DATA0 = IOMUX_PAD(0x0374, 0x010C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA00_GPIO3_IO6 = IOMUX_PAD(0x0374, 0x010C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_DATA01_RAWNAND_DATA01 = IOMUX_PAD(0x0378, 0x0110, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA01_QSPI_A_DATA1 = IOMUX_PAD(0x0378, 0x0110, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA01_GPIO3_IO7 = IOMUX_PAD(0x0378, 0x0110, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_DATA02_RAWNAND_DATA02 = IOMUX_PAD(0x037C, 0x0114, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA02_QSPI_A_DATA2 = IOMUX_PAD(0x037C, 0x0114, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA02_USDHC3_CD_B = IOMUX_PAD(0x037C, 0x0114, 2, 0x0544, 0, 0),
+ IMX8MM_PAD_NAND_DATA02_GPIO3_IO8 = IOMUX_PAD(0x037C, 0x0114, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_DATA03_RAWNAND_DATA03 = IOMUX_PAD(0x0380, 0x0118, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA03_QSPI_A_DATA3 = IOMUX_PAD(0x0380, 0x0118, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA03_USDHC3_WP = IOMUX_PAD(0x0380, 0x0118, 2, 0x0548, 0, 0),
+ IMX8MM_PAD_NAND_DATA03_GPIO3_IO9 = IOMUX_PAD(0x0380, 0x0118, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_DATA04_RAWNAND_DATA04 = IOMUX_PAD(0x0384, 0x011C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA04_QSPI_B_DATA0 = IOMUX_PAD(0x0384, 0x011C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA04_USDHC3_DATA0 = IOMUX_PAD(0x0384, 0x011C, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA04_GPIO3_IO10 = IOMUX_PAD(0x0384, 0x011C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_DATA05_RAWNAND_DATA05 = IOMUX_PAD(0x0388, 0x0120, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA05_QSPI_B_DATA1 = IOMUX_PAD(0x0388, 0x0120, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA05_USDHC3_DATA1 = IOMUX_PAD(0x0388, 0x0120, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA05_GPIO3_IO11 = IOMUX_PAD(0x0388, 0x0120, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_DATA06_RAWNAND_DATA06 = IOMUX_PAD(0x038C, 0x0124, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA06_QSPI_B_DATA2 = IOMUX_PAD(0x038C, 0x0124, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA06_USDHC3_DATA2 = IOMUX_PAD(0x038C, 0x0124, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA06_GPIO3_IO12 = IOMUX_PAD(0x038C, 0x0124, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_DATA07_RAWNAND_DATA07 = IOMUX_PAD(0x0390, 0x0128, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA07_QSPI_B_DATA3 = IOMUX_PAD(0x0390, 0x0128, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA07_USDHC3_DATA3 = IOMUX_PAD(0x0390, 0x0128, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DATA07_GPIO3_IO13 = IOMUX_PAD(0x0390, 0x0128, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_DQS_RAWNAND_DQS = IOMUX_PAD(0x0394, 0x012C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DQS_QSPI_A_DQS = IOMUX_PAD(0x0394, 0x012C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_DQS_GPIO3_IO14 = IOMUX_PAD(0x0394, 0x012C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_RE_B_RAWNAND_RE_B = IOMUX_PAD(0x0398, 0x0130, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_RE_B_QSPI_B_DQS = IOMUX_PAD(0x0398, 0x0130, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_RE_B_USDHC3_DATA4 = IOMUX_PAD(0x0398, 0x0130, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_RE_B_GPIO3_IO15 = IOMUX_PAD(0x0398, 0x0130, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_READY_B_RAWNAND_READY_B = IOMUX_PAD(0x039C, 0x0134, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_READY_B_USDHC3_RESET_B = IOMUX_PAD(0x039C, 0x0134, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_READY_B_GPIO3_IO16 = IOMUX_PAD(0x039C, 0x0134, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_WE_B_RAWNAND_WE_B = IOMUX_PAD(0x03A0, 0x0138, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_WE_B_USDHC3_CLK = IOMUX_PAD(0x03A0, 0x0138, 2 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_WE_B_GPIO3_IO17 = IOMUX_PAD(0x03A0, 0x0138, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_NAND_WP_B_RAWNAND_WP_B = IOMUX_PAD(0x03A4, 0x013C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_WP_B_USDHC3_CMD = IOMUX_PAD(0x03A4, 0x013C, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_NAND_WP_B_GPIO3_IO18 = IOMUX_PAD(0x03A4, 0x013C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI5_RXFS_SAI5_RX_SYNC = IOMUX_PAD(0x03A8, 0x0140, 0, 0x04E4, 0, 0),
+ IMX8MM_PAD_SAI5_RXFS_SAI1_TX_DATA0 = IOMUX_PAD(0x03A8, 0x0140, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI5_RXFS_GPIO3_IO19 = IOMUX_PAD(0x03A8, 0x0140, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI5_RXC_SAI5_RX_BCLK = IOMUX_PAD(0x03AC, 0x0144, 0, 0x04D0, 0, 0),
+ IMX8MM_PAD_SAI5_RXC_SAI1_TX_DATA1 = IOMUX_PAD(0x03AC, 0x0144, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI5_RXC_PDM_CLK = IOMUX_PAD(0x03AC, 0x0144, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI5_RXC_GPIO3_IO20 = IOMUX_PAD(0x03AC, 0x0144, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI5_RXD0_SAI5_RX_DATA0 = IOMUX_PAD(0x03B0, 0x0148, 0, 0x04D4, 0, 0),
+ IMX8MM_PAD_SAI5_RXD0_SAI1_TX_DATA2 = IOMUX_PAD(0x03B0, 0x0148, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI5_RXD0_PDM_BIT_STREAM0 = IOMUX_PAD(0x03B0, 0x0148, 4, 0x0534, 0, 0),
+ IMX8MM_PAD_SAI5_RXD0_GPIO3_IO21 = IOMUX_PAD(0x03B0, 0x0148, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI5_RXD1_SAI5_RX_DATA1 = IOMUX_PAD(0x03B4, 0x014C, 0, 0x04D8, 0, 0),
+ IMX8MM_PAD_SAI5_RXD1_SAI1_TX_DATA3 = IOMUX_PAD(0x03B4, 0x014C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI5_RXD1_SAI1_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 2, 0x04CC, 0, 0),
+ IMX8MM_PAD_SAI5_RXD1_SAI5_TX_SYNC = IOMUX_PAD(0x03B4, 0x014C, 3, 0x04EC, 0, 0),
+ IMX8MM_PAD_SAI5_RXD1_PDM_BIT_STREAM1 = IOMUX_PAD(0x03B4, 0x014C, 4, 0x0538, 0, 0),
+ IMX8MM_PAD_SAI5_RXD1_GPIO3_IO22 = IOMUX_PAD(0x03B4, 0x014C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI5_RXD2_SAI5_RX_DATA2 = IOMUX_PAD(0x03B8, 0x0150, 0, 0x04DC, 0, 0),
+ IMX8MM_PAD_SAI5_RXD2_SAI1_TX_DATA4 = IOMUX_PAD(0x03B8, 0x0150, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI5_RXD2_SAI1_TX_SYNC = IOMUX_PAD(0x03B8, 0x0150, 2, 0x04CC, 1, 0),
+ IMX8MM_PAD_SAI5_RXD2_SAI5_TX_BCLK = IOMUX_PAD(0x03B8, 0x0150, 3, 0x04E8, 0, 0),
+ IMX8MM_PAD_SAI5_RXD2_PDM_BIT_STREAM2 = IOMUX_PAD(0x03B8, 0x0150, 4, 0x053C, 0, 0),
+ IMX8MM_PAD_SAI5_RXD2_GPIO3_IO23 = IOMUX_PAD(0x03B8, 0x0150, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI5_RXD3_SAI5_RX_DATA3 = IOMUX_PAD(0x03BC, 0x0154, 0, 0x04E0, 0, 0),
+ IMX8MM_PAD_SAI5_RXD3_SAI1_TX_DATA5 = IOMUX_PAD(0x03BC, 0x0154, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI5_RXD3_SAI1_TX_SYNC = IOMUX_PAD(0x03BC, 0x0154, 2, 0x04CC, 2, 0),
+ IMX8MM_PAD_SAI5_RXD3_SAI5_TX_DATA0 = IOMUX_PAD(0x03BC, 0x0154, 3, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI5_RXD3_PDM_BIT_STREAM3 = IOMUX_PAD(0x03BC, 0x0154, 4, 0x0540, 0, 0),
+ IMX8MM_PAD_SAI5_RXD3_GPIO3_IO24 = IOMUX_PAD(0x03BC, 0x0154, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI5_MCLK_SAI5_MCLK = IOMUX_PAD(0x03C0, 0x0158, 0, 0x052C, 0, 0),
+ IMX8MM_PAD_SAI5_MCLK_SAI1_TX_BCLK = IOMUX_PAD(0x03C0, 0x0158, 1, 0x04C8, 0, 0),
+ IMX8MM_PAD_SAI5_MCLK_GPIO3_IO25 = IOMUX_PAD(0x03C0, 0x0158, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI5_MCLK_SRC_TESTER_ACK = IOMUX_PAD(0x03C0, 0x0158, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_RXFS_SAI1_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 0, 0x04C4, 0, 0),
+ IMX8MM_PAD_SAI1_RXFS_SAI5_RX_SYNC = IOMUX_PAD(0x03C4, 0x015C, 1, 0x04E4, 1, 0),
+ IMX8MM_PAD_SAI1_RXFS_ARM_PLATFORM_TRACE_CLK = IOMUX_PAD(0x03C4, 0x015C, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXFS_GPIO4_IO0 = IOMUX_PAD(0x03C4, 0x015C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_RXC_SAI1_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXC_SAI5_RX_BCLK = IOMUX_PAD(0x03C8, 0x0160, 1, 0x04D0, 1, 0),
+ IMX8MM_PAD_SAI1_RXC_ARM_PLATFORM_TRACE_CTL = IOMUX_PAD(0x03C8, 0x0160, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXC_GPIO4_IO1 = IOMUX_PAD(0x03C8, 0x0160, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_RXD0_SAI1_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD0_SAI5_RX_DATA0 = IOMUX_PAD(0x03CC, 0x0164, 1, 0x04D4, 1, 0),
+ IMX8MM_PAD_SAI1_RXD0_SAI1_TX_DATA1 = IOMUX_PAD(0x03CC, 0x0164, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD0_PDM_BIT_STREAM0 = IOMUX_PAD(0x03CC, 0x0164, 3, 0x0534, 1, 0),
+ IMX8MM_PAD_SAI1_RXD0_ARM_PLATFORM_TRACE0 = IOMUX_PAD(0x03CC, 0x0164, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD0_GPIO4_IO2 = IOMUX_PAD(0x03CC, 0x0164, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD0_SRC_BOOT_CFG0 = IOMUX_PAD(0x03CC, 0x0164, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_RXD1_SAI1_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD1_SAI5_RX_DATA1 = IOMUX_PAD(0x03D0, 0x0168, 1, 0x04D8, 1, 0),
+ IMX8MM_PAD_SAI1_RXD1_PDM_BIT_STREAM1 = IOMUX_PAD(0x03D0, 0x0168, 3, 0x0538, 1, 0),
+ IMX8MM_PAD_SAI1_RXD1_ARM_PLATFORM_TRACE1 = IOMUX_PAD(0x03D0, 0x0168, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD1_GPIO4_IO3 = IOMUX_PAD(0x03D0, 0x0168, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD1_SRC_BOOT_CFG1 = IOMUX_PAD(0x03D0, 0x0168, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_RXD2_SAI1_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD2_SAI5_RX_DATA2 = IOMUX_PAD(0x03D4, 0x016C, 1, 0x04DC, 1, 0),
+ IMX8MM_PAD_SAI1_RXD2_PDM_BIT_STREAM2 = IOMUX_PAD(0x03D4, 0x016C, 3, 0x053C, 1, 0),
+ IMX8MM_PAD_SAI1_RXD2_ARM_PLATFORM_TRACE2 = IOMUX_PAD(0x03D4, 0x016C, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD2_GPIO4_IO4 = IOMUX_PAD(0x03D4, 0x016C, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD2_SRC_BOOT_CFG2 = IOMUX_PAD(0x03D4, 0x016C, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_RXD3_SAI1_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD3_SAI5_RX_DATA3 = IOMUX_PAD(0x03D8, 0x0170, 1, 0x04E0, 1, 0),
+ IMX8MM_PAD_SAI1_RXD3_PDM_BIT_STREAM3 = IOMUX_PAD(0x03D8, 0x0170, 3, 0x0540, 1, 0),
+ IMX8MM_PAD_SAI1_RXD3_ARM_PLATFORM_TRACE3 = IOMUX_PAD(0x03D8, 0x0170, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD3_GPIO4_IO5 = IOMUX_PAD(0x03D8, 0x0170, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD3_SRC_BOOT_CFG3 = IOMUX_PAD(0x03D8, 0x0170, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_RXD4_SAI1_RX_DATA4 = IOMUX_PAD(0x03DC, 0x0174, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD4_SAI6_TX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 1, 0x051C, 0, 0),
+ IMX8MM_PAD_SAI1_RXD4_SAI6_RX_BCLK = IOMUX_PAD(0x03DC, 0x0174, 2, 0x0510, 0, 0),
+ IMX8MM_PAD_SAI1_RXD4_ARM_PLATFORM_TRACE4 = IOMUX_PAD(0x03DC, 0x0174, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD4_GPIO4_IO6 = IOMUX_PAD(0x03DC, 0x0174, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD4_SRC_BOOT_CFG4 = IOMUX_PAD(0x03DC, 0x0174, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_RXD5_SAI1_RX_DATA5 = IOMUX_PAD(0x03E0, 0x0178, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD5_SAI6_TX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD5_SAI6_RX_DATA0 = IOMUX_PAD(0x03E0, 0x0178, 2, 0x0514, 0, 0),
+ IMX8MM_PAD_SAI1_RXD5_SAI1_RX_SYNC = IOMUX_PAD(0x03E0, 0x0178, 3, 0x04C4, 1, 0),
+ IMX8MM_PAD_SAI1_RXD5_ARM_PLATFORM_TRACE5 = IOMUX_PAD(0x03E0, 0x0178, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD5_GPIO4_IO7 = IOMUX_PAD(0x03E0, 0x0178, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD5_SRC_BOOT_CFG5 = IOMUX_PAD(0x03E0, 0x0178, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_RXD6_SAI1_RX_DATA6 = IOMUX_PAD(0x03E4, 0x017C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD6_SAI6_TX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 1, 0x0520, 0, 0),
+ IMX8MM_PAD_SAI1_RXD6_SAI6_RX_SYNC = IOMUX_PAD(0x03E4, 0x017C, 2, 0x0518, 0, 0),
+ IMX8MM_PAD_SAI1_RXD6_ARM_PLATFORM_TRACE6 = IOMUX_PAD(0x03E4, 0x017C, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD6_GPIO4_IO8 = IOMUX_PAD(0x03E4, 0x017C, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD6_SRC_BOOT_CFG6 = IOMUX_PAD(0x03E4, 0x017C, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_RXD7_SAI1_RX_DATA7 = IOMUX_PAD(0x03E8, 0x0180, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD7_SAI6_MCLK = IOMUX_PAD(0x03E8, 0x0180, 1, 0x0530, 0, 0),
+ IMX8MM_PAD_SAI1_RXD7_SAI1_TX_SYNC = IOMUX_PAD(0x03E8, 0x0180, 2, 0x04CC, 4, 0),
+ IMX8MM_PAD_SAI1_RXD7_SAI1_TX_DATA4 = IOMUX_PAD(0x03E8, 0x0180, 3, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD7_ARM_PLATFORM_TRACE7 = IOMUX_PAD(0x03E8, 0x0180, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD7_GPIO4_IO9 = IOMUX_PAD(0x03E8, 0x0180, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_RXD7_SRC_BOOT_CFG7 = IOMUX_PAD(0x03E8, 0x0180, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_TXFS_SAI1_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 0, 0x04CC, 3, 0),
+ IMX8MM_PAD_SAI1_TXFS_SAI5_TX_SYNC = IOMUX_PAD(0x03EC, 0x0184, 1, 0x04EC, 1, 0),
+ IMX8MM_PAD_SAI1_TXFS_ARM_PLATFORM_EVENTO = IOMUX_PAD(0x03EC, 0x0184, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXFS_GPIO4_IO10 = IOMUX_PAD(0x03EC, 0x0184, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_TXC_SAI1_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 0, 0x04C8, 1, 0),
+ IMX8MM_PAD_SAI1_TXC_SAI5_TX_BCLK = IOMUX_PAD(0x03F0, 0x0188, 1, 0x04E8, 1, 0),
+ IMX8MM_PAD_SAI1_TXC_ARM_PLATFORM_EVENTI = IOMUX_PAD(0x03F0, 0x0188, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXC_GPIO4_IO11 = IOMUX_PAD(0x03F0, 0x0188, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_TXD0_SAI1_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD0_SAI5_TX_DATA0 = IOMUX_PAD(0x03F4, 0x018C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD0_ARM_PLATFORM_TRACE8 = IOMUX_PAD(0x03F4, 0x018C, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD0_GPIO4_IO12 = IOMUX_PAD(0x03F4, 0x018C, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD0_SRC_BOOT_CFG8 = IOMUX_PAD(0x03F4, 0x018C, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_TXD1_SAI1_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD1_SAI5_TX_DATA1 = IOMUX_PAD(0x03F8, 0x0190, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD1_ARM_PLATFORM_TRACE9 = IOMUX_PAD(0x03F8, 0x0190, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD1_GPIO4_IO13 = IOMUX_PAD(0x03F8, 0x0190, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD1_SRC_BOOT_CFG9 = IOMUX_PAD(0x03F8, 0x0190, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_TXD2_SAI1_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD2_SAI5_TX_DATA2 = IOMUX_PAD(0x03FC, 0x0194, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD2_ARM_PLATFORM_TRACE10 = IOMUX_PAD(0x03FC, 0x0194, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD2_GPIO4_IO14 = IOMUX_PAD(0x03FC, 0x0194, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD2_SRC_BOOT_CFG10 = IOMUX_PAD(0x03FC, 0x0194, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_TXD3_SAI1_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD3_SAI5_TX_DATA3 = IOMUX_PAD(0x0400, 0x0198, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD3_ARM_PLATFORM_TRACE11 = IOMUX_PAD(0x0400, 0x0198, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD3_GPIO4_IO15 = IOMUX_PAD(0x0400, 0x0198, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD3_SRC_BOOT_CFG11 = IOMUX_PAD(0x0400, 0x0198, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_TXD4_SAI1_TX_DATA4 = IOMUX_PAD(0x0404, 0x019C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD4_SAI6_RX_BCLK = IOMUX_PAD(0x0404, 0x019C, 1, 0x0510, 1, 0),
+ IMX8MM_PAD_SAI1_TXD4_SAI6_TX_BCLK = IOMUX_PAD(0x0404, 0x019C, 2, 0x051C, 1, 0),
+ IMX8MM_PAD_SAI1_TXD4_ARM_PLATFORM_TRACE12 = IOMUX_PAD(0x0404, 0x019C, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD4_GPIO4_IO16 = IOMUX_PAD(0x0404, 0x019C, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD4_SRC_BOOT_CFG12 = IOMUX_PAD(0x0404, 0x019C, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_TXD5_SAI1_TX_DATA5 = IOMUX_PAD(0x0408, 0x01A0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD5_SAI6_RX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 1, 0x0514, 1, 0),
+ IMX8MM_PAD_SAI1_TXD5_SAI6_TX_DATA0 = IOMUX_PAD(0x0408, 0x01A0, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD5_ARM_PLATFORM_TRACE13 = IOMUX_PAD(0x0408, 0x01A0, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD5_GPIO4_IO17 = IOMUX_PAD(0x0408, 0x01A0, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD5_SRC_BOOT_CFG13 = IOMUX_PAD(0x0408, 0x01A0, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_TXD6_SAI1_TX_DATA6 = IOMUX_PAD(0x040C, 0x01A4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD6_SAI6_RX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 1, 0x0518, 1, 0),
+ IMX8MM_PAD_SAI1_TXD6_SAI6_TX_SYNC = IOMUX_PAD(0x040C, 0x01A4, 2, 0x0520, 1, 0),
+ IMX8MM_PAD_SAI1_TXD6_ARM_PLATFORM_TRACE14 = IOMUX_PAD(0x040C, 0x01A4, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD6_GPIO4_IO18 = IOMUX_PAD(0x040C, 0x01A4, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD6_SRC_BOOT_CFG14 = IOMUX_PAD(0x040C, 0x01A4, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_TXD7_SAI1_TX_DATA7 = IOMUX_PAD(0x0410, 0x01A8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD7_SAI6_MCLK = IOMUX_PAD(0x0410, 0x01A8, 1, 0x0530, 1, 0),
+ IMX8MM_PAD_SAI1_TXD7_PDM_CLK = IOMUX_PAD(0x0410, 0x01A8, 3, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD7_ARM_PLATFORM_TRACE15 = IOMUX_PAD(0x0410, 0x01A8, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD7_GPIO4_IO19 = IOMUX_PAD(0x0410, 0x01A8, 5, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_TXD7_SRC_BOOT_CFG15 = IOMUX_PAD(0x0410, 0x01A8, 6, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI1_MCLK_SAI1_MCLK = IOMUX_PAD(0x0414, 0x01AC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_MCLK_SAI5_MCLK = IOMUX_PAD(0x0414, 0x01AC, 1, 0x052C, 1, 0),
+ IMX8MM_PAD_SAI1_MCLK_SAI1_TX_BCLK = IOMUX_PAD(0x0414, 0x01AC, 2, 0x04C8, 2, 0),
+ IMX8MM_PAD_SAI1_MCLK_PDM_CLK = IOMUX_PAD(0x0414, 0x01AC, 3, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI1_MCLK_GPIO4_IO20 = IOMUX_PAD(0x0414, 0x01AC, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI2_RXFS_SAI2_RX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_RXFS_SAI5_TX_SYNC = IOMUX_PAD(0x0418, 0x01B0, 1, 0x04EC, 2, 0),
+ IMX8MM_PAD_SAI2_RXFS_SAI5_TX_DATA1 = IOMUX_PAD(0x0418, 0x01B0, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_RXFS_SAI2_RX_DATA1 = IOMUX_PAD(0x0418, 0x01B0, 3, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_RXFS_UART1_TX = IOMUX_PAD(0x0418, 0x01B0, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_RXFS_UART1_RX = IOMUX_PAD(0x0418, 0x01B0, 4, 0x04F4, 2, 0),
+ IMX8MM_PAD_SAI2_RXFS_GPIO4_IO21 = IOMUX_PAD(0x0418, 0x01B0, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI2_RXC_SAI2_RX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_RXC_SAI5_TX_BCLK = IOMUX_PAD(0x041C, 0x01B4, 1, 0x04E8, 2, 0),
+ IMX8MM_PAD_SAI2_RXC_UART1_RX = IOMUX_PAD(0x041C, 0x01B4, 4, 0x04F4, 3, 0),
+ IMX8MM_PAD_SAI2_RXC_UART1_TX = IOMUX_PAD(0x041C, 0x01B4, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_RXC_GPIO4_IO22 = IOMUX_PAD(0x041C, 0x01B4, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI2_RXD0_SAI2_RX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_RXD0_SAI5_TX_DATA0 = IOMUX_PAD(0x0420, 0x01B8, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_RXD0_UART1_RTS_B = IOMUX_PAD(0x0420, 0x01B8, 4, 0x04F0, 2, 0),
+ IMX8MM_PAD_SAI2_RXD0_UART1_CTS_B = IOMUX_PAD(0x0420, 0x01B8, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_RXD0_GPIO4_IO23 = IOMUX_PAD(0x0420, 0x01B8, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI2_TXFS_SAI2_TX_SYNC = IOMUX_PAD(0x0424, 0x01BC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_TXFS_SAI5_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_TXFS_SAI2_TX_DATA1 = IOMUX_PAD(0x0424, 0x01BC, 3, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_TXFS_UART1_CTS_B = IOMUX_PAD(0x0424, 0x01BC, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_TXFS_UART1_RTS_B = IOMUX_PAD(0x0424, 0x01BC, 4, 0x04F0, 3, 0),
+ IMX8MM_PAD_SAI2_TXFS_GPIO4_IO24 = IOMUX_PAD(0x0424, 0x01BC, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI2_TXC_SAI2_TX_BCLK = IOMUX_PAD(0x0428, 0x01C0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_TXC_SAI5_TX_DATA2 = IOMUX_PAD(0x0428, 0x01C0, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_TXC_GPIO4_IO25 = IOMUX_PAD(0x0428, 0x01C0, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI2_TXD0_SAI2_TX_DATA0 = IOMUX_PAD(0x042C, 0x01C4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_TXD0_SAI5_TX_DATA3 = IOMUX_PAD(0x042C, 0x01C4, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_TXD0_GPIO4_IO26 = IOMUX_PAD(0x042C, 0x01C4, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI2_MCLK_SAI2_MCLK = IOMUX_PAD(0x0430, 0x01C8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI2_MCLK_SAI5_MCLK = IOMUX_PAD(0x0430, 0x01C8, 1, 0x052C, 2, 0),
+ IMX8MM_PAD_SAI2_MCLK_GPIO4_IO27 = IOMUX_PAD(0x0430, 0x01C8, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI3_RXFS_SAI3_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_RXFS_GPT1_CAPTURE1 = IOMUX_PAD(0x0434, 0x01CC, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_RXFS_SAI5_RX_SYNC = IOMUX_PAD(0x0434, 0x01CC, 2, 0x04E4, 2, 0),
+ IMX8MM_PAD_SAI3_RXFS_SAI3_RX_DATA1 = IOMUX_PAD(0x0434, 0x01CC, 3, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_RXFS_GPIO4_IO28 = IOMUX_PAD(0x0434, 0x01CC, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI3_RXC_SAI3_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_RXC_GPT1_CLK = IOMUX_PAD(0x0438, 0x01D0, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_RXC_SAI5_RX_BCLK = IOMUX_PAD(0x0438, 0x01D0, 2, 0x04D0, 2, 0),
+ IMX8MM_PAD_SAI3_RXC_UART2_CTS_B = IOMUX_PAD(0x0438, 0x01D0, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_RXC_UART2_RTS_B = IOMUX_PAD(0x0438, 0x01D0, 4, 0x04F8, 2, 0),
+ IMX8MM_PAD_SAI3_RXC_GPIO4_IO29 = IOMUX_PAD(0x0438, 0x01D0, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI3_RXD_SAI3_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_RXD_GPT1_COMPARE1 = IOMUX_PAD(0x043C, 0x01D4, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_RXD_SAI5_RX_DATA0 = IOMUX_PAD(0x043C, 0x01D4, 2, 0x04D4, 2, 0),
+ IMX8MM_PAD_SAI3_RXD_UART2_RTS_B = IOMUX_PAD(0x043C, 0x01D4, 4, 0x04F8, 3, 0),
+ IMX8MM_PAD_SAI3_RXD_UART2_CTS_B = IOMUX_PAD(0x043C, 0x01D4, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_RXD_GPIO4_IO30 = IOMUX_PAD(0x043C, 0x01D4, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI3_TXFS_SAI3_TX_SYNC = IOMUX_PAD(0x0440, 0x01D8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_TXFS_GPT1_CAPTURE2 = IOMUX_PAD(0x0440, 0x01D8, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_TXFS_SAI5_RX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 2, 0x04D8, 2, 0),
+ IMX8MM_PAD_SAI3_TXFS_SAI3_TX_DATA1 = IOMUX_PAD(0x0440, 0x01D8, 3, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_TXFS_UART2_RX = IOMUX_PAD(0x0440, 0x01D8, 4, 0x04FC, 2, 0),
+ IMX8MM_PAD_SAI3_TXFS_UART2_TX = IOMUX_PAD(0x0440, 0x01D8, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_TXFS_GPIO4_IO31 = IOMUX_PAD(0x0440, 0x01D8, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI3_TXC_SAI3_TX_BCLK = IOMUX_PAD(0x0444, 0x01DC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_TXC_GPT1_COMPARE2 = IOMUX_PAD(0x0444, 0x01DC, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_TXC_SAI5_RX_DATA2 = IOMUX_PAD(0x0444, 0x01DC, 2, 0x04DC, 2, 0),
+ IMX8MM_PAD_SAI3_TXC_UART2_TX = IOMUX_PAD(0x0444, 0x01DC, 4, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_TXC_UART2_RX = IOMUX_PAD(0x0444, 0x01DC, 4, 0x04FC, 3, 0),
+ IMX8MM_PAD_SAI3_TXC_GPIO5_IO0 = IOMUX_PAD(0x0444, 0x01DC, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI3_TXD_SAI3_TX_DATA0 = IOMUX_PAD(0x0448, 0x01E0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_TXD_GPT1_COMPARE3 = IOMUX_PAD(0x0448, 0x01E0, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_TXD_SAI5_RX_DATA3 = IOMUX_PAD(0x0448, 0x01E0, 2, 0x04E0, 2, 0),
+ IMX8MM_PAD_SAI3_TXD_GPIO5_IO1 = IOMUX_PAD(0x0448, 0x01E0, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SAI3_MCLK_SAI3_MCLK = IOMUX_PAD(0x044C, 0x01E4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_MCLK_PWM4_OUT = IOMUX_PAD(0x044C, 0x01E4, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SAI3_MCLK_SAI5_MCLK = IOMUX_PAD(0x044C, 0x01E4, 2, 0x052C, 3, 0),
+ IMX8MM_PAD_SAI3_MCLK_GPIO5_IO2 = IOMUX_PAD(0x044C, 0x01E4, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SPDIF_TX_SPDIF1_OUT = IOMUX_PAD(0x0450, 0x01E8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SPDIF_TX_PWM3_OUT = IOMUX_PAD(0x0450, 0x01E8, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SPDIF_TX_GPIO5_IO3 = IOMUX_PAD(0x0450, 0x01E8, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SPDIF_RX_SPDIF1_IN = IOMUX_PAD(0x0454, 0x01EC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SPDIF_RX_PWM2_OUT = IOMUX_PAD(0x0454, 0x01EC, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SPDIF_RX_GPIO5_IO4 = IOMUX_PAD(0x0454, 0x01EC, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_SPDIF_EXT_CLK_SPDIF1_EXT_CLK = IOMUX_PAD(0x0458, 0x01F0, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_SPDIF_EXT_CLK_PWM1_OUT = IOMUX_PAD(0x0458, 0x01F0, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_SPDIF_EXT_CLK_GPIO5_IO5 = IOMUX_PAD(0x0458, 0x01F0, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ECSPI1_SCLK_ECSPI1_SCLK = IOMUX_PAD(0x045C, 0x01F4, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI1_SCLK_UART3_RX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0504, 0, 0),
+ IMX8MM_PAD_ECSPI1_SCLK_UART3_TX = IOMUX_PAD(0x045C, 0x01F4, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI1_SCLK_GPIO5_IO6 = IOMUX_PAD(0x045C, 0x01F4, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ECSPI1_MOSI_ECSPI1_MOSI = IOMUX_PAD(0x0460, 0x01F8, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI1_MOSI_UART3_TX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI1_MOSI_UART3_RX = IOMUX_PAD(0x0460, 0x01F8, 1, 0x0504, 1, 0),
+ IMX8MM_PAD_ECSPI1_MOSI_GPIO5_IO7 = IOMUX_PAD(0x0460, 0x01F8, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ECSPI1_MISO_ECSPI1_MISO = IOMUX_PAD(0x0464, 0x01FC, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI1_MISO_UART3_CTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI1_MISO_UART3_RTS_B = IOMUX_PAD(0x0464, 0x01FC, 1, 0x0500, 0, 0),
+ IMX8MM_PAD_ECSPI1_MISO_GPIO5_IO8 = IOMUX_PAD(0x0464, 0x01FC, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ECSPI1_SS0_ECSPI1_SS0 = IOMUX_PAD(0x0468, 0x0200, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI1_SS0_UART3_RTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0500, 1, 0),
+ IMX8MM_PAD_ECSPI1_SS0_UART3_CTS_B = IOMUX_PAD(0x0468, 0x0200, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI1_SS0_GPIO5_IO9 = IOMUX_PAD(0x0468, 0x0200, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ECSPI2_SCLK_ECSPI2_SCLK = IOMUX_PAD(0x046C, 0x0204, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI2_SCLK_UART4_RX = IOMUX_PAD(0x046C, 0x0204, 1, 0x050C, 0, 0),
+ IMX8MM_PAD_ECSPI2_SCLK_UART4_TX = IOMUX_PAD(0x046C, 0x0204, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI2_SCLK_GPIO5_IO10 = IOMUX_PAD(0x046C, 0x0204, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ECSPI2_MOSI_ECSPI2_MOSI = IOMUX_PAD(0x0470, 0x0208, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI2_MOSI_UART4_TX = IOMUX_PAD(0x0470, 0x0208, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI2_MOSI_UART4_RX = IOMUX_PAD(0x0470, 0x0208, 1, 0x050C, 1, 0),
+ IMX8MM_PAD_ECSPI2_MOSI_GPIO5_IO11 = IOMUX_PAD(0x0470, 0x0208, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ECSPI2_MISO_ECSPI2_MISO = IOMUX_PAD(0x0474, 0x020C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI2_MISO_UART4_CTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI2_MISO_UART4_RTS_B = IOMUX_PAD(0x0474, 0x020C, 1, 0x0508, 0, 0),
+ IMX8MM_PAD_ECSPI2_MISO_GPIO5_IO12 = IOMUX_PAD(0x0474, 0x020C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_ECSPI2_SS0_ECSPI2_SS0 = IOMUX_PAD(0x0478, 0x0210, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI2_SS0_UART4_RTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0508, 1, 0),
+ IMX8MM_PAD_ECSPI2_SS0_UART4_CTS_B = IOMUX_PAD(0x0478, 0x0210, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_ECSPI2_SS0_GPIO5_IO13 = IOMUX_PAD(0x0478, 0x0210, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_I2C1_SCL_I2C1_SCL = IOMUX_PAD(0x047C, 0x0214, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C1_SCL_ENET1_MDC = IOMUX_PAD(0x047C, 0x0214, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C1_SCL_GPIO5_IO14 = IOMUX_PAD(0x047C, 0x0214, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_I2C1_SDA_I2C1_SDA = IOMUX_PAD(0x0480, 0x0218, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C1_SDA_ENET1_MDIO = IOMUX_PAD(0x0480, 0x0218, 1, 0x04C0, 2, 0),
+ IMX8MM_PAD_I2C1_SDA_GPIO5_IO15 = IOMUX_PAD(0x0480, 0x0218, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_I2C2_SCL_I2C2_SCL = IOMUX_PAD(0x0484, 0x021C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C2_SCL_ENET1_1588_EVENT1_IN = IOMUX_PAD(0x0484, 0x021C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C2_SCL_USDHC3_CD_B = IOMUX_PAD(0x0484, 0x021C, 2, 0x0544, 1, 0),
+ IMX8MM_PAD_I2C2_SCL_GPIO5_IO16 = IOMUX_PAD(0x0484, 0x021C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_I2C2_SDA_I2C2_SDA = IOMUX_PAD(0x0488, 0x0220, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C2_SDA_ENET1_1588_EVENT1_OUT = IOMUX_PAD(0x0488, 0x0220, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C2_SDA_USDHC3_WP = IOMUX_PAD(0x0488, 0x0220, 2, 0x0548, 1, 0),
+ IMX8MM_PAD_I2C2_SDA_GPIO5_IO17 = IOMUX_PAD(0x0488, 0x0220, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_I2C3_SCL_I2C3_SCL = IOMUX_PAD(0x048C, 0x0224, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C3_SCL_PWM4_OUT = IOMUX_PAD(0x048C, 0x0224, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C3_SCL_GPT2_CLK = IOMUX_PAD(0x048C, 0x0224, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C3_SCL_GPIO5_IO18 = IOMUX_PAD(0x048C, 0x0224, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_I2C3_SDA_I2C3_SDA = IOMUX_PAD(0x0490, 0x0228, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C3_SDA_PWM3_OUT = IOMUX_PAD(0x0490, 0x0228, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C3_SDA_GPT3_CLK = IOMUX_PAD(0x0490, 0x0228, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C3_SDA_GPIO5_IO19 = IOMUX_PAD(0x0490, 0x0228, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_I2C4_SCL_I2C4_SCL = IOMUX_PAD(0x0494, 0x022C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C4_SCL_PWM2_OUT = IOMUX_PAD(0x0494, 0x022C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C4_SCL_PCIE1_CLKREQ_B = IOMUX_PAD(0x0494, 0x022C, 2, 0x0524, 0, 0),
+ IMX8MM_PAD_I2C4_SCL_GPIO5_IO20 = IOMUX_PAD(0x0494, 0x022C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_I2C4_SDA_I2C4_SDA = IOMUX_PAD(0x0498, 0x0230, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C4_SDA_PWM1_OUT = IOMUX_PAD(0x0498, 0x0230, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_I2C4_SDA_GPIO5_IO21 = IOMUX_PAD(0x0498, 0x0230, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_UART1_RXD_UART1_RX = IOMUX_PAD(0x049C, 0x0234, 0, 0x04F4, 0, 0),
+ IMX8MM_PAD_UART1_RXD_UART1_TX = IOMUX_PAD(0x049C, 0x0234, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_UART1_RXD_ECSPI3_SCLK = IOMUX_PAD(0x049C, 0x0234, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_UART1_RXD_GPIO5_IO22 = IOMUX_PAD(0x049C, 0x0234, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_UART1_TXD_UART1_TX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_UART1_TXD_UART1_RX = IOMUX_PAD(0x04A0, 0x0238, 0, 0x04F4, 1, 0),
+ IMX8MM_PAD_UART1_TXD_ECSPI3_MOSI = IOMUX_PAD(0x04A0, 0x0238, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_UART1_TXD_GPIO5_IO23 = IOMUX_PAD(0x04A0, 0x0238, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_UART2_RXD_UART2_RX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x04FC, 0, 0),
+ IMX8MM_PAD_UART2_RXD_UART2_TX = IOMUX_PAD(0x04A4, 0x023C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_UART2_RXD_ECSPI3_MISO = IOMUX_PAD(0x04A4, 0x023C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_UART2_RXD_GPIO5_IO24 = IOMUX_PAD(0x04A4, 0x023C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_UART2_TXD_UART2_TX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_UART2_TXD_UART2_RX = IOMUX_PAD(0x04A8, 0x0240, 0, 0x04FC, 1, 0),
+ IMX8MM_PAD_UART2_TXD_ECSPI3_SS0 = IOMUX_PAD(0x04A8, 0x0240, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_UART2_TXD_GPIO5_IO25 = IOMUX_PAD(0x04A8, 0x0240, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_UART3_RXD_UART3_RX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0504, 2, 0),
+ IMX8MM_PAD_UART3_RXD_UART3_TX = IOMUX_PAD(0x04AC, 0x0244, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_UART3_RXD_UART1_CTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_UART3_RXD_UART1_RTS_B = IOMUX_PAD(0x04AC, 0x0244, 1, 0x04F0, 0, 0),
+ IMX8MM_PAD_UART3_RXD_USDHC3_RESET_B = IOMUX_PAD(0x04AC, 0x0244, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_UART3_RXD_GPIO5_IO26 = IOMUX_PAD(0x04AC, 0x0244, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_UART3_TXD_UART3_TX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_UART3_TXD_UART3_RX = IOMUX_PAD(0x04B0, 0x0248, 0, 0x0504, 3, 0),
+ IMX8MM_PAD_UART3_TXD_UART1_RTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x04F0, 1, 0),
+ IMX8MM_PAD_UART3_TXD_UART1_CTS_B = IOMUX_PAD(0x04B0, 0x0248, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_UART3_TXD_USDHC3_VSELECT = IOMUX_PAD(0x04B0, 0x0248, 2, 0x0000, 0, 0),
+ IMX8MM_PAD_UART3_TXD_GPIO5_IO27 = IOMUX_PAD(0x04B0, 0x0248, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_UART4_RXD_UART4_RX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x050C, 2, 0),
+ IMX8MM_PAD_UART4_RXD_UART4_TX = IOMUX_PAD(0x04B4, 0x024C, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_UART4_RXD_UART2_CTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_UART4_RXD_UART2_RTS_B = IOMUX_PAD(0x04B4, 0x024C, 1, 0x04F8, 0, 0),
+ IMX8MM_PAD_UART4_RXD_PCIE1_CLKREQ_B = IOMUX_PAD(0x04B4, 0x024C, 2, 0x0524, 1, 0),
+ IMX8MM_PAD_UART4_RXD_GPIO5_IO28 = IOMUX_PAD(0x04B4, 0x024C, 5, 0x0000, 0, 0),
+
+ IMX8MM_PAD_UART4_TXD_UART4_TX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x0000, 0, 0),
+ IMX8MM_PAD_UART4_TXD_UART4_RX = IOMUX_PAD(0x04B8, 0x0250, 0, 0x050C, 3, 0),
+ IMX8MM_PAD_UART4_TXD_UART2_RTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x04F8, 1, 0),
+ IMX8MM_PAD_UART4_TXD_UART2_CTS_B = IOMUX_PAD(0x04B8, 0x0250, 1, 0x0000, 0, 0),
+ IMX8MM_PAD_UART4_TXD_GPIO5_IO29 = IOMUX_PAD(0x04B8, 0x0250, 5, 0x0000, 0, 0),
+};
+#endif
diff --git a/arch/arm/include/asm/arch-imx8m/power-domain.h b/arch/arm/include/asm/arch-imx8m/power-domain.h
new file mode 100644
index 00000000000..0f94945894e
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx8m/power-domain.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright 2017 NXP
+ */
+
+#ifndef _ASM_ARCH_IMX8M_POWER_DOMAIN_H
+#define _ASM_ARCH_IMX8M_POWER_DOMAIN_H
+
+struct imx8m_power_domain_platdata {
+ int resource_id;
+ int has_pd;
+ struct power_domain pd;
+};
+
+#endif
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-13 09:40:51 +0000