diff options
Diffstat (limited to 'arch/arm/include/asm')
| -rw-r--r-- | arch/arm/include/asm/arch-mx31/clock.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-s5pc1xx/clk.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-s5pc1xx/gpio.h | 4 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-s5pc1xx/mmc.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-s5pc1xx/sromc.h (renamed from arch/arm/include/asm/arch-s5pc1xx/smc.h) | 8 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-s5pc2xx/clk.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-s5pc2xx/cpu.h | 12 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-s5pc2xx/gpio.h | 7 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-s5pc2xx/mmc.h | 1 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-s5pc2xx/sromc.h | 51 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-u8500/clock.h | 72 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-u8500/gpio.h | 247 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-u8500/hardware.h | 83 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-u8500/sys_proto.h | 27 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-u8500/u8500.h | 47 |
15 files changed, 552 insertions, 11 deletions
diff --git a/arch/arm/include/asm/arch-mx31/clock.h b/arch/arm/include/asm/arch-mx31/clock.h index 1ff917ed242..9f7ae8036e7 100644 --- a/arch/arm/include/asm/arch-mx31/clock.h +++ b/arch/arm/include/asm/arch-mx31/clock.h @@ -32,5 +32,6 @@ extern void mx31_set_pad(enum iomux_pins pin, u32 config); void mx31_uart1_hw_init(void); void mx31_spi2_hw_init(void); void mxc_hw_watchdog_enable(void); +void mxc_hw_watchdog_reset(void); #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-s5pc1xx/clk.h b/arch/arm/include/asm/arch-s5pc1xx/clk.h index 4c389c1fc53..692dfe0633d 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/clk.h +++ b/arch/arm/include/asm/arch-s5pc1xx/clk.h @@ -33,5 +33,6 @@ unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); unsigned long get_pwm_clk(void); unsigned long get_uart_clk(int dev_index); +void set_mmc_clk(int dev_index, unsigned int div); #endif diff --git a/arch/arm/include/asm/arch-s5pc1xx/gpio.h b/arch/arm/include/asm/arch-s5pc1xx/gpio.h index 2df33a607c0..485b9bf8e05 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/gpio.h +++ b/arch/arm/include/asm/arch-s5pc1xx/gpio.h @@ -149,8 +149,8 @@ void gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); /* Drive Strength level */ #define GPIO_DRV_1X 0x0 -#define GPIO_DRV_2X 0x1 -#define GPIO_DRV_3X 0x2 +#define GPIO_DRV_3X 0x1 +#define GPIO_DRV_2X 0x2 #define GPIO_DRV_4X 0x3 #define GPIO_DRV_FAST 0x0 #define GPIO_DRV_SLOW 0x1 diff --git a/arch/arm/include/asm/arch-s5pc1xx/mmc.h b/arch/arm/include/asm/arch-s5pc1xx/mmc.h index d458d3bb8ef..adef4ee21db 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/mmc.h +++ b/arch/arm/include/asm/arch-s5pc1xx/mmc.h @@ -64,6 +64,7 @@ struct mmc_host { struct s5p_mmc *reg; unsigned int version; /* SDHCI spec. version */ unsigned int clock; /* Current clock (MHz) */ + int dev_index; }; int s5p_mmc_init(int dev_index, int bus_width); diff --git a/arch/arm/include/asm/arch-s5pc1xx/smc.h b/arch/arm/include/asm/arch-s5pc1xx/sromc.h index 88f4ffe33ae..3800a8dbae1 100644 --- a/arch/arm/include/asm/arch-s5pc1xx/smc.h +++ b/arch/arm/include/asm/arch-s5pc1xx/sromc.h @@ -23,8 +23,8 @@ * Only SROMC is defined as of now */ -#ifndef __ASM_ARCH_SMC_H_ -#define __ASM_ARCH_SMC_H_ +#ifndef __ASM_ARCH_SROMC_H_ +#define __ASM_ARCH_SROMC_H_ #define SMC_DATA16_WIDTH(x) (1<<((x*4)+0)) #define SMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/ @@ -41,13 +41,13 @@ #define SMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */ #ifndef __ASSEMBLY__ -struct s5pc1xx_smc { +struct s5p_sromc { unsigned int bw; unsigned int bc[6]; }; #endif /* __ASSEMBLY__ */ /* Configure the Band Width and Bank Control Regs for required SROMC Bank */ -void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf); +void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf); #endif /* __ASM_ARCH_SMC_H_ */ diff --git a/arch/arm/include/asm/arch-s5pc2xx/clk.h b/arch/arm/include/asm/arch-s5pc2xx/clk.h index 5a1cdf15104..ff0f6415d8b 100644 --- a/arch/arm/include/asm/arch-s5pc2xx/clk.h +++ b/arch/arm/include/asm/arch-s5pc2xx/clk.h @@ -32,5 +32,6 @@ unsigned long get_pll_clk(int pllreg); unsigned long get_arm_clk(void); unsigned long get_pwm_clk(void); unsigned long get_uart_clk(int dev_index); +void set_mmc_clk(int dev_index, unsigned int div); #endif diff --git a/arch/arm/include/asm/arch-s5pc2xx/cpu.h b/arch/arm/include/asm/arch-s5pc2xx/cpu.h index d56ee802fc9..f9015c76f12 100644 --- a/arch/arm/include/asm/arch-s5pc2xx/cpu.h +++ b/arch/arm/include/asm/arch-s5pc2xx/cpu.h @@ -51,6 +51,12 @@ #include <asm/io.h> /* CPU detection macros */ extern unsigned int s5p_cpu_id; +extern unsigned int s5p_cpu_rev; + +static inline int s5p_get_cpu_rev(void) +{ + return s5p_cpu_rev; +} static inline void s5p_set_cpu_id(void) { @@ -61,8 +67,12 @@ static inline void s5p_set_cpu_id(void) * 0xC200: S5PC210 EVT0 * 0xC210: S5PC210 EVT1 */ - if (s5p_cpu_id == 0xC200) + if (s5p_cpu_id == 0xC200) { s5p_cpu_id |= 0x10; + s5p_cpu_rev = 0; + } else if (s5p_cpu_id == 0xC210) { + s5p_cpu_rev = 1; + } } #define IS_SAMSUNG_TYPE(type, id) \ diff --git a/arch/arm/include/asm/arch-s5pc2xx/gpio.h b/arch/arm/include/asm/arch-s5pc2xx/gpio.h index 05e5b3e0b7b..38303e4f0cf 100644 --- a/arch/arm/include/asm/arch-s5pc2xx/gpio.h +++ b/arch/arm/include/asm/arch-s5pc2xx/gpio.h @@ -99,14 +99,13 @@ void gpio_set_rate(struct s5p_gpio_bank *bank, int gpio, int mode); /* Pull mode */ #define GPIO_PULL_NONE 0x0 #define GPIO_PULL_DOWN 0x1 -#define GPIO_PULL_UP 0x2 +#define GPIO_PULL_UP 0x3 /* Drive Strength level */ #define GPIO_DRV_1X 0x0 -#define GPIO_DRV_2X 0x1 -#define GPIO_DRV_3X 0x2 +#define GPIO_DRV_3X 0x1 +#define GPIO_DRV_2X 0x2 #define GPIO_DRV_4X 0x3 #define GPIO_DRV_FAST 0x0 #define GPIO_DRV_SLOW 0x1 - #endif diff --git a/arch/arm/include/asm/arch-s5pc2xx/mmc.h b/arch/arm/include/asm/arch-s5pc2xx/mmc.h index 04827cad759..30f82b8aaf6 100644 --- a/arch/arm/include/asm/arch-s5pc2xx/mmc.h +++ b/arch/arm/include/asm/arch-s5pc2xx/mmc.h @@ -64,6 +64,7 @@ struct mmc_host { struct s5p_mmc *reg; unsigned int version; /* SDHCI spec. version */ unsigned int clock; /* Current clock (MHz) */ + int dev_index; }; int s5p_mmc_init(int dev_index, int bus_width); diff --git a/arch/arm/include/asm/arch-s5pc2xx/sromc.h b/arch/arm/include/asm/arch-s5pc2xx/sromc.h new file mode 100644 index 00000000000..f616bcb37bc --- /dev/null +++ b/arch/arm/include/asm/arch-s5pc2xx/sromc.h @@ -0,0 +1,51 @@ +/* + * (C) Copyright 2010 Samsung Electronics + * Naveen Krishna Ch <ch.naveen@samsung.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Note: This file contains the register description for SROMC + * + */ + +#ifndef __ASM_ARCH_SROMC_H_ +#define __ASM_ARCH_SROMC_H_ + +#define SROMC_DATA16_WIDTH(x) (1<<((x*4)+0)) +#define SROMC_BYTE_ADDR_MODE(x) (1<<((x*4)+1)) /* 0-> Half-word base address*/ + /* 1-> Byte base address*/ +#define SROMC_WAIT_ENABLE(x) (1<<((x*4)+2)) +#define SROMC_BYTE_ENABLE(x) (1<<((x*4)+3)) + +#define SROMC_BC_TACS(x) (x << 28) /* address set-up */ +#define SROMC_BC_TCOS(x) (x << 24) /* chip selection set-up */ +#define SROMC_BC_TACC(x) (x << 16) /* access cycle */ +#define SROMC_BC_TCOH(x) (x << 12) /* chip selection hold */ +#define SROMC_BC_TAH(x) (x << 8) /* address holding time */ +#define SROMC_BC_TACP(x) (x << 4) /* page mode access cycle */ +#define SROMC_BC_PMC(x) (x << 0) /* normal(1data)page mode configuration */ + +#ifndef __ASSEMBLY__ +struct s5p_sromc { + unsigned int bw; + unsigned int bc[4]; +}; +#endif /* __ASSEMBLY__ */ + +/* Configure the Band Width and Bank Control Regs for required SROMC Bank */ +void s5p_config_sromc(u32 srom_bank, u32 srom_bw_conf, u32 srom_bc_conf); + +#endif /* __ASM_ARCH_SROMC_H_ */ diff --git a/arch/arm/include/asm/arch-u8500/clock.h b/arch/arm/include/asm/arch-u8500/clock.h new file mode 100644 index 00000000000..b00ab0d215f --- /dev/null +++ b/arch/arm/include/asm/arch-u8500/clock.h @@ -0,0 +1,72 @@ +/* + * Copyright (C) ST-Ericsson SA 2009 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ASM_ARCH_CLOCK +#define __ASM_ARCH_CLOCK + +struct prcmu { + unsigned int armclkfix_mgt; + unsigned int armclk_mgt; + unsigned int svammdspclk_mgt; + unsigned int siammdspclk_mgt; + unsigned int reserved; + unsigned int sgaclk_mgt; + unsigned int uartclk_mgt; + unsigned int msp02clk_mgt; + unsigned int i2cclk_mgt; + unsigned int sdmmcclk_mgt; + unsigned int slimclk_mgt; + unsigned int per1clk_mgt; + unsigned int per2clk_mgt; + unsigned int per3clk_mgt; + unsigned int per5clk_mgt; + unsigned int per6clk_mgt; + unsigned int per7clk_mgt; + unsigned int lcdclk_mgt; + unsigned int reserved1; + unsigned int bmlclk_mgt; + unsigned int hsitxclk_mgt; + unsigned int hsirxclk_mgt; + unsigned int hdmiclk_mgt; + unsigned int apeatclk_mgt; + unsigned int apetraceclk_mgt; + unsigned int mcdeclk_mgt; + unsigned int ipi2cclk_mgt; + unsigned int dsialtclk_mgt; + unsigned int spare2clk_mgt; + unsigned int dmaclk_mgt; + unsigned int b2r2clk_mgt; + unsigned int tvclk_mgt; + unsigned int unused[82]; + unsigned int tcr; + unsigned int unused1[23]; + unsigned int ape_softrst; +}; + +extern void u8500_clock_enable(int periph, int kern, int cluster); + +static inline void u8500_prcmu_enable(unsigned int *reg) +{ + writel(readl(reg) | (1 << 8), reg); +} + +#endif /* __ASM_ARCH_CLOCK */ diff --git a/arch/arm/include/asm/arch-u8500/gpio.h b/arch/arm/include/asm/arch-u8500/gpio.h new file mode 100644 index 00000000000..769def19b54 --- /dev/null +++ b/arch/arm/include/asm/arch-u8500/gpio.h @@ -0,0 +1,247 @@ +/* + * Copyright (C) ST-Ericsson SA 2009 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _UX500_GPIO_h +#define _UX500_GPIO_h + +#include <asm/types.h> +#include <asm/io.h> +#include <asm/errno.h> + +#include <asm/arch/sys_proto.h> +#include <asm/arch/u8500.h> + +#define GPIO_TOTAL_PINS 268 + +#define GPIO_PINS_PER_BLOCK 32 +#define GPIO_BLOCKS_COUNT (GPIO_TOTAL_PINS/GPIO_PINS_PER_BLOCK + 1) +#define GPIO_BLOCK(pin) (((pin + GPIO_PINS_PER_BLOCK) >> 5) - 1) + + +struct gpio_register { + u32 gpio_dat; /* data register *//*0x000 */ + u32 gpio_dats; /* data Set register *//*0x004 */ + u32 gpio_datc; /* data Clear register *//*0x008 */ + u32 gpio_pdis; /* Pull disable register *//*0x00C */ + u32 gpio_dir; /* data direction register *//*0x010 */ + u32 gpio_dirs; /* data dir Set register *//*0x014 */ + u32 gpio_dirc; /* data dir Clear register *//*0x018 */ + u32 gpio_slpm; /* Sleep mode register *//*0x01C */ + u32 gpio_afsa; /* AltFun A Select reg *//*0x020 */ + u32 gpio_afsb; /* AltFun B Select reg *//*0x024 */ + u32 gpio_lowemi;/* low EMI Select reg *//*0x028 */ + u32 reserved_1[(0x040 - 0x02C) >> 2]; /*0x028-0x3C Reserved*/ + u32 gpio_rimsc; /* rising edge intr set/clear *//*0x040 */ + u32 gpio_fimsc; /* falling edge intr set/clear register *//*0x044 */ + u32 gpio_mis; /* masked interrupt status register *//*0x048 */ + u32 gpio_ic; /* Interrupt Clear register *//*0x04C */ + u32 gpio_rwimsc;/* Rising-edge Wakeup IMSC register *//*0x050 */ + u32 gpio_fwimsc;/* Falling-edge Wakeup IMSC register *//*0x054 */ + u32 gpio_wks; /* Wakeup Status register *//*0x058 */ +}; + +/* Error values returned by functions */ +enum gpio_error { + GPIO_OK = 0, + GPIO_UNSUPPORTED_HW = -2, + GPIO_UNSUPPORTED_FEATURE = -3, + GPIO_INVALID_PARAMETER = -4, + GPIO_REQUEST_NOT_APPLICABLE = -5, + GPIO_REQUEST_PENDING = -6, + GPIO_NOT_CONFIGURED = -7, + GPIO_INTERNAL_ERROR = -8, + GPIO_INTERNAL_EVENT = 1, + GPIO_REMAINING_EVENT = 2, + GPIO_NO_MORE_PENDING_EVENT = 3, + GPIO_INVALID_CLIENT = -25, + GPIO_INVALID_PIN = -26, + GPIO_PIN_BUSY = -27, + GPIO_PIN_NOT_ALLOCATED = -28, + GPIO_WRONG_CLIENT = -29, + GPIO_UNSUPPORTED_ALTFUNC = -30, +}; + +/*GPIO DEVICE ID */ +enum gpio_device_id { + GPIO_DEVICE_ID_0, + GPIO_DEVICE_ID_1, + GPIO_DEVICE_ID_2, + GPIO_DEVICE_ID_3, + GPIO_DEVICE_ID_INVALID +}; + +/* + * Alternate Function: + * refered in altfun_table to pointout particular altfun to be enabled + * when using GPIO_ALT_FUNCTION A/B/C enable/disable operation + */ +enum gpio_alt_function { + GPIO_ALT_UART_0_MODEM, + GPIO_ALT_UART_0_NO_MODEM, + GPIO_ALT_UART_1, + GPIO_ALT_UART_2, + GPIO_ALT_I2C_0, + GPIO_ALT_I2C_1, + GPIO_ALT_I2C_2, + GPIO_ALT_I2C_3, + GPIO_ALT_MSP_0, + GPIO_ALT_MSP_1, + GPIO_ALT_MSP_2, + GPIO_ALT_MSP_3, + GPIO_ALT_MSP_4, + GPIO_ALT_MSP_5, + GPIO_ALT_SSP_0, + GPIO_ALT_SSP_1, + GPIO_ALT_MM_CARD0, + GPIO_ALT_SD_CARD0, + GPIO_ALT_DMA_0, + GPIO_ALT_DMA_1, + GPIO_ALT_HSI0, + GPIO_ALT_CCIR656_INPUT, + GPIO_ALT_CCIR656_OUTPUT, + GPIO_ALT_LCD_PANEL, + GPIO_ALT_MDIF, + GPIO_ALT_SDRAM, + GPIO_ALT_HAMAC_AUDIO_DBG, + GPIO_ALT_HAMAC_VIDEO_DBG, + GPIO_ALT_CLOCK_RESET, + GPIO_ALT_TSP, + GPIO_ALT_IRDA, + GPIO_ALT_USB_MINIMUM, + GPIO_ALT_USB_I2C, + GPIO_ALT_OWM, + GPIO_ALT_PWL, + GPIO_ALT_FSMC, + GPIO_ALT_COMP_FLASH, + GPIO_ALT_SRAM_NOR_FLASH, + GPIO_ALT_FSMC_ADDLINE_0_TO_15, + GPIO_ALT_SCROLL_KEY, + GPIO_ALT_MSHC, + GPIO_ALT_HPI, + GPIO_ALT_USB_OTG, + GPIO_ALT_SDIO, + GPIO_ALT_HSMMC, + GPIO_ALT_FSMC_ADD_DATA_0_TO_25, + GPIO_ALT_HSI1, + GPIO_ALT_NOR, + GPIO_ALT_NAND, + GPIO_ALT_KEYPAD, + GPIO_ALT_VPIP, + GPIO_ALT_CAM, + GPIO_ALT_CCP1, + GPIO_ALT_EMMC, + GPIO_ALT_POP_EMMC, + GPIO_ALT_FUNMAX /* Add new alt func before this */ +}; + +/* Defines pin assignment(Software mode or Alternate mode) */ +enum gpio_mode { + GPIO_MODE_LEAVE_UNCHANGED, /* Parameter will be ignored */ + GPIO_MODE_SOFTWARE, /* Pin connected to GPIO (SW controlled) */ + GPIO_ALTF_A, /* Pin connected to altfunc 1 (HW periph 1) */ + GPIO_ALTF_B, /* Pin connected to altfunc 2 (HW periph 2) */ + GPIO_ALTF_C, /* Pin connected to altfunc 3 (HW periph 3) */ + GPIO_ALTF_FIND, /* Pin connected to altfunc 3 (HW periph 3) */ + GPIO_ALTF_DISABLE /* Pin connected to altfunc 3 (HW periph 3) */ +}; + +/* Defines GPIO pin direction */ +enum gpio_direction { + GPIO_DIR_LEAVE_UNCHANGED, /* Parameter will be ignored */ + GPIO_DIR_INPUT, /* GPIO set as input */ + GPIO_DIR_OUTPUT /* GPIO set as output */ +}; + +/* Interrupt trigger mode */ +enum gpio_trig { + GPIO_TRIG_LEAVE_UNCHANGED, /* Parameter will be ignored */ + GPIO_TRIG_DISABLE, /* Trigger no IT */ + GPIO_TRIG_RISING_EDGE, /* Trigger an IT on rising edge */ + GPIO_TRIG_FALLING_EDGE, /* Trigger an IT on falling edge */ + GPIO_TRIG_BOTH_EDGES, /* Trigger an IT on rising and falling edge */ + GPIO_TRIG_HIGH_LEVEL, /* Trigger an IT on high level */ + GPIO_TRIG_LOW_LEVEL /* Trigger an IT on low level */ +}; + +/* Configuration parameters for one GPIO pin.*/ +struct gpio_config { + enum gpio_mode mode; + enum gpio_direction direction; + enum gpio_trig trig; + char *dev_name; /* Who owns the gpio pin */ +}; + +/* GPIO pin data*/ +enum gpio_data { + GPIO_DATA_LOW, + GPIO_DATA_HIGH +}; + +/* GPIO behaviour in sleep mode */ +enum gpio_sleep_mode { + GPIO_SLEEP_MODE_LEAVE_UNCHANGED, /* Parameter will be ignored */ + GPIO_SLEEP_MODE_INPUT_DEFAULTVOLT, /* GPIO is an input with pull + up/down enabled when in sleep + mode. */ + GPIO_SLEEP_MODE_CONTROLLED_BY_GPIO /* GPIO pin is controlled by + GPIO IP. So mode, direction + and data values for GPIO pin + in sleep mode are determined + by configuration set to GPIO + pin before entering to sleep + mode. */ +}; + +/* GPIO ability to wake the system up from sleep mode.*/ +enum gpio_wake { + GPIO_WAKE_LEAVE_UNCHANGED, /* Parameter will be ignored */ + GPIO_WAKE_DISABLE, /* No wake of system from sleep mode. */ + GPIO_WAKE_LOW_LEVEL, /* Wake the system up on a LOW level. */ + GPIO_WAKE_HIGH_LEVEL, /* Wake the system up on a HIGH level. */ + GPIO_WAKE_RISING_EDGE, /* Wake the system up on a RISING edge. */ + GPIO_WAKE_FALLING_EDGE, /* Wake the system up on a FALLING edge. */ + GPIO_WAKE_BOTH_EDGES /* Wake the system up on both RISE and FALL. */ +}; + +/* Configuration parameters for one GPIO pin in sleep mode.*/ +struct gpio_sleep_config { + enum gpio_sleep_mode sleep_mode;/* GPIO behaviour in sleep mode. */ + enum gpio_wake wake; /* GPIO ability to wake up system. */ +}; + +extern int gpio_setpinconfig(int pin_id, struct gpio_config *pin_config); +extern int gpio_resetpinconfig(int pin_id, char *dev_name); +extern int gpio_writepin(int pin_id, enum gpio_data value, char *dev_name); +extern int gpio_readpin(int pin_id, enum gpio_data *value); +extern int gpio_altfuncenable(enum gpio_alt_function altfunc, + char *dev_name); +extern int gpio_altfuncdisable(enum gpio_alt_function altfunc, + char *dev_name); + +struct gpio_altfun_data { + u16 altfun; + u16 start; + u16 end; + u16 cont; + u8 type; +}; +#endif diff --git a/arch/arm/include/asm/arch-u8500/hardware.h b/arch/arm/include/asm/arch-u8500/hardware.h new file mode 100644 index 00000000000..6bb95ec0707 --- /dev/null +++ b/arch/arm/include/asm/arch-u8500/hardware.h @@ -0,0 +1,83 @@ +/* + * Copyright (C) ST-Ericsson SA 2009 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#ifndef __ASM_ARCH_HARDWARE_H +#define __ASM_ARCH_HARDWARE_H + +/* Peripheral clusters */ + +#define U8500_PER3_BASE 0x80000000 +#define U8500_PER2_BASE 0x80110000 +#define U8500_PER1_BASE 0x80120000 +#define U8500_PER4_BASE 0x80150000 + +#define U8500_PER6_BASE 0xa03c0000 +#define U8500_PER7_BASE 0xa03d0000 +#define U8500_PER5_BASE 0xa03e0000 + +/* GPIO */ + +#define U8500_GPIO0_BASE (U8500_PER1_BASE + 0xE000) +#define U8500_GPIO1_BASE (U8500_PER1_BASE + 0xE000 + 0x80) + +#define U8500_GPIO2_BASE (U8500_PER3_BASE + 0xE000) +#define U8500_GPIO3_BASE (U8500_PER3_BASE + 0xE000 + 0x80) +#define U8500_GPIO4_BASE (U8500_PER3_BASE + 0xE000 + 0x100) +#define U8500_GPIO5_BASE (U8500_PER3_BASE + 0xE000 + 0x180) + +#define U8500_GPIO6_BASE (U8500_PER2_BASE + 0xE000) +#define U8500_GPIO7_BASE (U8500_PER2_BASE + 0xE000 + 0x80) + +#define U8500_GPIO8_BASE (U8500_PER5_BASE + 0x1E000) + +/* Per7 */ +#define U8500_CLKRST7_BASE (U8500_PER7_BASE + 0xf000) + +/* Per6 */ +#define U8500_MTU0_BASE_V1 (U8500_PER6_BASE + 0x6000) +#define U8500_MTU1_BASE_V1 (U8500_PER6_BASE + 0x7000) +#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000) + +/* Per5 */ +#define U8500_CLKRST5_BASE (U8500_PER5_BASE + 0x1f000) + +/* Per4 */ +#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000) +#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x0f000) + +/* Per3 */ +#define U8500_UART2_BASE (U8500_PER3_BASE + 0x7000) +#define U8500_CLKRST3_BASE (U8500_PER3_BASE + 0xf000) + +/* Per2 */ +#define U8500_CLKRST2_BASE (U8500_PER2_BASE + 0xf000) + +/* Per1 */ +#define U8500_UART0_BASE (U8500_PER1_BASE + 0x0000) +#define U8500_UART1_BASE (U8500_PER1_BASE + 0x1000) +#define U8500_CLKRST1_BASE (U8500_PER1_BASE + 0xf000) + +/* Last page of Boot ROM */ +#define U8500_BOOTROM_BASE 0x9001f000 +#define U8500_BOOTROM_ASIC_ID_OFFSET 0x0ff4 + +#endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-u8500/sys_proto.h b/arch/arm/include/asm/arch-u8500/sys_proto.h new file mode 100644 index 00000000000..bac5e799908 --- /dev/null +++ b/arch/arm/include/asm/arch-u8500/sys_proto.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) ST-Ericsson SA 2010 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +void gpio_init(void); + +#endif /* _SYS_PROTO_H_ */ diff --git a/arch/arm/include/asm/arch-u8500/u8500.h b/arch/arm/include/asm/arch-u8500/u8500.h new file mode 100644 index 00000000000..0d6dbb7dbba --- /dev/null +++ b/arch/arm/include/asm/arch-u8500/u8500.h @@ -0,0 +1,47 @@ +/* + * Copyright (C) ST-Ericsson SA 2009 + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __U8500_H +#define __U8500_H + +/* + * base register values for U8500 + */ +#define CFG_PRCMU_BASE 0x80157000 /* Power, reset and clock + Management Unit */ +#define CFG_SDRAMC_BASE 0x903CF000 /* SDRAMC cnf registers */ +#define CFG_FSMC_BASE 0x80000000 /* FSMC Controller */ + +/* + * U8500 GPIO register base for 9 banks + */ +#define U8500_GPIO_0_BASE 0x8012E000 +#define U8500_GPIO_1_BASE 0x8012E080 +#define U8500_GPIO_2_BASE 0x8000E000 +#define U8500_GPIO_3_BASE 0x8000E080 +#define U8500_GPIO_4_BASE 0x8000E100 +#define U8500_GPIO_5_BASE 0x8000E180 +#define U8500_GPIO_6_BASE 0x8011E000 +#define U8500_GPIO_7_BASE 0x8011E080 +#define U8500_GPIO_8_BASE 0xA03FE000 + +#endif /* __U8500_H */ |