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-rw-r--r--arch/arm/mach-k3/include/mach/am64_hardware.h55
-rw-r--r--arch/arm/mach-k3/include/mach/am64_spl.h44
-rw-r--r--arch/arm/mach-k3/include/mach/hardware.h4
-rw-r--r--arch/arm/mach-k3/include/mach/spl.h4
4 files changed, 107 insertions, 0 deletions
diff --git a/arch/arm/mach-k3/include/mach/am64_hardware.h b/arch/arm/mach-k3/include/mach/am64_hardware.h
new file mode 100644
index 00000000000..c368aa7e6bf
--- /dev/null
+++ b/arch/arm/mach-k3/include/mach/am64_hardware.h
@@ -0,0 +1,55 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * K3: AM64 SoC definitions, structures etc.
+ *
+ * (C) Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ */
+#ifndef __ASM_ARCH_AM64_HARDWARE_H
+#define __ASM_ARCH_AM64_HARDWARE_H
+
+#include <config.h>
+
+#define CTRL_MMR0_BASE 0x43000000
+#define CTRLMMR_MAIN_DEVSTAT (CTRL_MMR0_BASE + 0x30)
+
+#define PADCFG_MMR1_BASE 0xf0000
+
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_MASK 0x00000078
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_SHIFT 3
+
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_MASK 0x00000380
+#define MAIN_DEVSTAT_PRIMARY_BOOTMODE_CFG_SHIFT 7
+
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_MASK 0x00001c00
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT 10
+
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK 0x00002000
+#define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT 13
+
+/* After the cfg mask and shifts have been applied */
+#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_SHIFT 2
+#define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK 0x04
+
+/*
+ * The CTRL_MMR and PADCFG_MMR memory space is divided into several
+ * equally-spaced partitions, so defining the partition size allows us to
+ * determine register addresses common to those partitions.
+ */
+#define CTRL_MMR0_PARTITION_SIZE 0x4000
+
+/*
+ * CTRL_MMR and PADCFG_MMR lock/kick-mechanism shared register definitions.
+ */
+#define CTRLMMR_LOCK_KICK0 0x01008
+#define CTRLMMR_LOCK_KICK0_UNLOCK_VAL 0x68ef3490
+#define CTRLMMR_LOCK_KICK0_UNLOCKED_MASK BIT(0)
+#define CTRLMMR_LOCK_KICK0_UNLOCKED_SHIFT 0
+#define CTRLMMR_LOCK_KICK1 0x0100c
+#define CTRLMMR_LOCK_KICK1_UNLOCK_VAL 0xd172bc5a
+
+#define ROM_ENTENDED_BOOT_DATA_INFO 0x701beb00
+
+/* Use Last 1K as Scratch pad */
+#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x701bfc00
+
+#endif /* __ASM_ARCH_DRA8_HARDWARE_H */
diff --git a/arch/arm/mach-k3/include/mach/am64_spl.h b/arch/arm/mach-k3/include/mach/am64_spl.h
new file mode 100644
index 00000000000..36826cfc4ed
--- /dev/null
+++ b/arch/arm/mach-k3/include/mach/am64_spl.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Keerthy <j-keerthy@ti.com>
+ */
+#ifndef _ASM_ARCH_AM64_SPL_H_
+#define _ASM_ARCH_AM64_SPL_H_
+
+/* Primary BootMode devices */
+#define BOOT_DEVICE_RAM 0x00
+#define BOOT_DEVICE_OSPI 0x01
+#define BOOT_DEVICE_QSPI 0x02
+#define BOOT_DEVICE_SPI 0x03
+#define BOOT_DEVICE_ETHERNET 0x04
+#define BOOT_DEVICE_ETHERNET_RGMII 0x04
+#define BOOT_DEVICE_ETHERNET_RMII 0x05
+#define BOOT_DEVICE_I2C 0x06
+#define BOOT_DEVICE_UART 0x07
+#define BOOT_DEVICE_MMC 0x08
+#define BOOT_DEVICE_EMMC 0x09
+
+#define BOOT_DEVICE_USB 0x0A
+#define BOOT_DEVICE_GPMC_NOR 0x0C
+#define BOOT_DEVICE_PCIE 0x0D
+#define BOOT_DEVICE_XSPI 0x0E
+
+#define BOOT_DEVICE_NOBOOT 0x0F
+
+#define BOOT_DEVICE_MMC2 0x08
+#define BOOT_DEVICE_MMC1 0x09
+/* INVALID */
+#define BOOT_DEVICE_MMC2_2 0x1F
+
+/* Backup BootMode devices */
+#define BACKUP_BOOT_DEVICE_USB 0x01
+#define BACKUP_BOOT_DEVICE_UART 0x03
+#define BACKUP_BOOT_DEVICE_ETHERNET 0x04
+#define BACKUP_BOOT_DEVICE_MMC 0x05
+#define BACKUP_BOOT_DEVICE_SPI 0x06
+#define BACKUP_BOOT_DEVICE_I2C 0x07
+
+#define K3_PRIMARY_BOOTMODE 0x0
+
+#endif
diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h
index 02b3df0e1b7..8725e7d51a5 100644
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -14,6 +14,10 @@
#include "j721e_hardware.h"
#endif
+#ifdef CONFIG_SOC_K3_AM642
+#include "am64_hardware.h"
+#endif
+
/* Assuming these addresses and definitions stay common across K3 devices */
#define CTRLMMR_WKUP_JTAG_ID 0x43000014
#define JTAG_ID_VARIANT_SHIFT 28
diff --git a/arch/arm/mach-k3/include/mach/spl.h b/arch/arm/mach-k3/include/mach/spl.h
index a26c8ecdd5b..ef1c3fb8cae 100644
--- a/arch/arm/mach-k3/include/mach/spl.h
+++ b/arch/arm/mach-k3/include/mach/spl.h
@@ -13,4 +13,8 @@
#ifdef CONFIG_SOC_K3_J721E
#include "j721e_spl.h"
#endif
+
+#ifdef CONFIG_SOC_K3_AM642
+#include "am64_spl.h"
+#endif
#endif /* _ASM_ARCH_SPL_H_ */