2 files changed, 65 insertions, 1 deletions
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index 316b326d417..5cf9e23e2ba 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -8,7 +8,7 @@
 #
 
 obj-y	+= misc.o timer.o reset_manager.o system_manager.o clock_manager.o \
-	   fpga_manager.o scan_manager.o
+	   fpga_manager.o scan_manager.o board.o
 obj-$(CONFIG_SPL_BUILD) += spl.o freeze_controller.o
 
 # QTS-generated config file wrappers
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
new file mode 100644
index 00000000000..a41d0899d77
--- /dev/null
+++ b/arch/arm/mach-socfpga/board.c
@@ -0,0 +1,64 @@
+/*
+ * Altera SoCFPGA common board code
+ *
+ * Copyright (C) 2015 Marek Vasut <marex@denx.de>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/io.h>
+
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void s_init(void) {}
+
+/*
+ * Miscellaneous platform dependent initialisations
+ */
+int board_init(void)
+{
+	/* Address of boot parameters for ATAG (if ATAG is used) */
+	gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+	return 0;
+}
+
+#ifdef CONFIG_USB_GADGET
+struct dwc2_plat_otg_data socfpga_otg_data = {
+	.usb_gusbcfg	= 0x1417,
+};
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+	int node[2], count;
+	fdt_addr_t addr;
+
+	count = fdtdec_find_aliases_for_id(gd->fdt_blob, "udc",
+					   COMPAT_ALTERA_SOCFPGA_DWC2USB,
+					   node, 2);
+	if (count <= 0)	/* No controller found. */
+		return 0;
+
+	addr = fdtdec_get_addr(gd->fdt_blob, node[0], "reg");
+	if (addr == FDT_ADDR_T_NONE) {
+		printf("UDC Controller has no 'reg' property!\n");
+		return -EINVAL;
+	}
+
+	/* Patch the address from OF into the controller pdata. */
+	socfpga_otg_data.regs_otg = addr;
+
+	return dwc2_udc_probe(&socfpga_otg_data);
+}
+
+int g_dnl_board_usb_cable_connected(void)
+{
+	return 1;
+}
+#endif