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-rw-r--r--arch/arm/Kconfig4
-rw-r--r--arch/arm/dts/Makefile1
-rw-r--r--arch/arm/dts/socfpga_agilex5-u-boot.dtsi71
-rw-r--r--arch/arm/dts/socfpga_agilex5.dtsi575
-rw-r--r--arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi124
-rw-r--r--arch/arm/dts/socfpga_agilex5_socdk.dts163
-rw-r--r--arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi38
-rw-r--r--arch/arm/mach-socfpga/Kconfig19
-rw-r--r--arch/arm/mach-socfpga/Makefile14
-rw-r--r--arch/arm/mach-socfpga/board.c56
-rw-r--r--arch/arm/mach-socfpga/clock_manager_agilex5.c89
-rw-r--r--arch/arm/mach-socfpga/include/mach/base_addr_soc64.h38
-rw-r--r--arch/arm/mach-socfpga/include/mach/clock_manager.h4
-rw-r--r--arch/arm/mach-socfpga/include/mach/clock_manager_agilex5.h12
-rw-r--r--arch/arm/mach-socfpga/include/mach/handoff_soc64.h25
-rw-r--r--arch/arm/mach-socfpga/include/mach/mailbox_s10.h1
-rw-r--r--arch/arm/mach-socfpga/mmu-arm64_s10.c59
-rw-r--r--arch/arm/mach-socfpga/wrap_handoff_soc64.c1
18 files changed, 1262 insertions, 32 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 16864f8afac..a0c1f6b5b1a 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -28,6 +28,7 @@ config COUNTER_FREQUENCY
ROCKCHIP_RK3288 || ROCKCHIP_RK322X || ROCKCHIP_RK3036
default 25000000 if ARCH_LX2160A || ARCH_LX2162A || ARCH_LS1088A
default 100000000 if ARCH_ZYNQMP
+ default 200000000 if ARCH_SOCFPGA && ARM64 && TARGET_SOCFPGA_AGILEX5
default 0
help
For platforms with ARMv8-A and ARMv7-A which features a system
@@ -1126,7 +1127,8 @@ config ARCH_SOCFPGA
select SYS_THUMB_BUILD if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
select SYSRESET
select SYSRESET_SOCFPGA if TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
- select SYSRESET_SOCFPGA_SOC64 if TARGET_SOCFPGA_SOC64
+ select SYSRESET_SOCFPGA_SOC64 if !TARGET_SOCFPGA_AGILEX5 && \
+ TARGET_SOCFPGA_SOC64
imply CMD_DM
imply CMD_MTDPARTS
imply CRC32_VERIFY
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index b102ffb5f68..51ea975fbb2 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -548,6 +548,7 @@ dtb-$(CONFIG_TARGET_THUNDERX_88XX) += thunderx-88xx.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += \
socfpga_agilex_socdk.dtb \
+ socfpga_agilex5_socdk.dtb \
socfpga_arria5_secu1.dtb \
socfpga_arria5_socdk.dtb \
socfpga_arria10_chameleonv3_270_2.dtb \
diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
new file mode 100644
index 00000000000..a8167e5c14a
--- /dev/null
+++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ */
+
+#include "socfpga_soc64_fit-u-boot.dtsi"
+
+/{
+ memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ bootph-all;
+ };
+};
+
+&clkmgr {
+ bootph-all;
+};
+
+&i2c0 {
+ reset-names = "i2c";
+};
+
+&i2c1 {
+ reset-names = "i2c";
+};
+
+&i2c2 {
+ reset-names = "i2c";
+};
+
+&i2c3 {
+ reset-names = "i2c";
+};
+
+&mmc {
+ resets = <&rst SDMMC_RESET>, <&rst SDMMC_OCP_RESET>;
+};
+
+&porta {
+ bank-name = "porta";
+};
+
+&portb {
+ bank-name = "portb";
+};
+
+&qspi {
+ bootph-all;
+};
+
+&rst {
+ compatible = "altr,rst-mgr";
+ altr,modrst-offset = <0x24>;
+ bootph-all;
+};
+
+&sysmgr {
+ compatible = "altr,sys-mgr", "syscon";
+ bootph-all;
+};
+
+&uart0 {
+ bootph-all;
+};
+
+&watchdog0 {
+ bootph-all;
+};
diff --git a/arch/arm/dts/socfpga_agilex5.dtsi b/arch/arm/dts/socfpga_agilex5.dtsi
new file mode 100644
index 00000000000..03b55040497
--- /dev/null
+++ b/arch/arm/dts/socfpga_agilex5.dtsi
@@ -0,0 +1,575 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ */
+
+/dts-v1/;
+#include <dt-bindings/reset/altr,rst-mgr-agx5.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/agilex5-clock.h>
+
+/ {
+ compatible = "intel,socfpga-agilex";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ service_reserved: svcbuffer@0 {
+ compatible = "shared-dma-pool";
+ reg = <0x0 0x0 0x0 0x1000000>;
+ alignment = <0x1000>;
+ no-map;
+ };
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ compatible = "arm,cortex-a55";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x0>;
+ };
+
+ cpu1: cpu@1 {
+ compatible = "arm,cortex-a55";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x1>;
+ };
+
+ cpu2: cpu@2 {
+ compatible = "arm,cortex-a76";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x2>;
+ };
+
+ cpu3: cpu@3 {
+ compatible = "arm,cortex-a76";
+ device_type = "cpu";
+ enable-method = "psci";
+ reg = <0x3>;
+ };
+ };
+
+ pmu {
+ compatible = "arm,armv8-pmuv3";
+ interrupts = <0 170 4>,
+ <0 171 4>,
+ <0 172 4>,
+ <0 173 4>;
+ interrupt-affinity = <&cpu0>,
+ <&cpu1>,
+ <&cpu2>,
+ <&cpu3>;
+ interrupt-parent = <&intc>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ intc: intc@fffc1000 {
+ compatible = "arm,gic-400", "arm,cortex-a15-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x0 0x1d000000 0x0 0x10000>;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ device_type = "soc";
+ interrupt-parent = <&intc>;
+ ranges = <0 0 0 0xffffffff>;
+
+ base_fpga_region {
+ #address-cells = <0x1>;
+ #size-cells = <0x1>;
+ compatible = "fpga-region";
+ fpga-mgr = <&fpga_mgr>;
+ };
+
+ clkmgr: clock-controller@10d10000 {
+ compatible = "intel,agilex5-clkmgr";
+ reg = <0x10d10000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ clocks {
+ cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ cb_intosc_ls_clk: cb-intosc-ls-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ f2s_free_clk: f2s-free-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ osc1: osc1 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+
+ qspi_clk: qspi-clk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <200000000>;
+ };
+ };
+ gmac0: ethernet@10810000 {
+ compatible = "intel,socfpga-dwxgmac", "snps,dwxgmac-2.10", "snps,dwxgmac";
+ reg = <0x10810000 0x3500>;
+ interrupts = <0 190 4>;
+ interrupt-names = "macirq";
+ mac-address = [00 00 00 00 00 00];
+ resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
+ reset-names = "stmmaceth", "stmmaceth-ocp";
+ tx-fifo-depth = <32768>;
+ rx-fifo-depth = <16384>;
+ iommus = <&smmu 1>;
+ altr,sysmgr-syscon = <&sysmgr 0x44 0>;
+ clocks = <&clkmgr AGILEX5_EMAC0_CLK>;
+ clock-names = "stmmaceth";
+ status = "disabled";
+ };
+
+ gmac1: ethernet@10820000 {
+ compatible = "intel,socfpga-dwxgmac", "snps,dwxgmac-2.10", "snps,dwxgmac";
+ reg = <0x10820000 0x3500>;
+ interrupts = <0 207 4>;
+ interrupt-names = "macirq";
+ mac-address = [00 00 00 00 00 00];
+ resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
+ reset-names = "stmmaceth", "stmmaceth-ocp";
+ tx-fifo-depth = <32768>;
+ rx-fifo-depth = <16384>;
+ iommus = <&smmu 2>;
+ altr,sysmgr-syscon = <&sysmgr 0x48 0>;
+ clocks = <&clkmgr AGILEX5_EMAC1_CLK>;
+ clock-names = "stmmaceth";
+ status = "disabled";
+ };
+
+ gmac2: ethernet@10830000 {
+ compatible = "intel,socfpga-dwxgmac", "snps,dwxgmac-2.10", "snps,dwxgmac";
+ reg = <0x10830000 0x3500>;
+ interrupts = <0 224 4>;
+ interrupt-names = "macirq";
+ mac-address = [00 00 00 00 00 00];
+ resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
+ reset-names = "stmmaceth", "stmmaceth-ocp";
+ tx-fifo-depth = <32768>;
+ rx-fifo-depth = <16384>;
+ iommus = <&smmu 3>;
+ altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
+ clocks = <&clkmgr AGILEX5_EMAC2_CLK>;
+ clock-names = "stmmaceth";
+ status = "disabled";
+ };
+
+ gpio0: gpio@10c03200 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x10c03200 0x80>;
+ resets = <&rst GPIO0_RESET>;
+ status = "disabled";
+
+ porta: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <24>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <0 110 4>;
+ };
+ };
+
+ gpio1: gpio@10c03300 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dw-apb-gpio";
+ reg = <0x10c03300 0x80>;
+ resets = <&rst GPIO1_RESET>;
+ status = "disabled";
+
+ portb: gpio-controller@0 {
+ compatible = "snps,dw-apb-gpio-port";
+ gpio-controller;
+ #gpio-cells = <2>;
+ snps,nr-gpios = <24>;
+ reg = <0>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ interrupts = <0 111 4>;
+ };
+ };
+
+ i2c0: i2c@10c02800 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0x10c02800 0x100>;
+ interrupts = <0 103 4>;
+ resets = <&rst I2C0_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@10c02900 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0x10c02900 0x100>;
+ interrupts = <0 104 4>;
+ resets = <&rst I2C1_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@10c02a00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0x10c02a00 0x100>;
+ interrupts = <0 105 4>;
+ resets = <&rst I2C2_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@10c02b00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0x10c02b00 0x100>;
+ interrupts = <0 106 4>;
+ resets = <&rst I2C3_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@10c02c00 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,designware-i2c";
+ reg = <0x10c02c00 0x100>;
+ interrupts = <0 107 4>;
+ resets = <&rst I2C4_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
+ status = "disabled";
+ };
+
+ i3c0: i3c@10da0000 {
+ compatible = "snps,dw-i3c-master-1.00a";
+ reg = <0x10da0000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 164 4>;
+ resets = <&rst I3C0_RESET>;
+ max_devices = <11>;
+ clocks = <&clkmgr AGILEX5_L4_MP_CLK>;
+ status = "disabled";
+ };
+
+ i3c1: i3c@10da1000 {
+ compatible = "snps,dw-i3c-master-1.00a";
+ reg = <0x10da1000 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ interrupts = <0 165 4>;
+ resets = <&rst I3C1_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_MP_CLK>;
+ max_devices = <11>;
+ status = "disabled";
+ };
+
+ combophy0: combophy@0 {
+ #phy-cells = <0>;
+ phy-type = <1>;
+ compatible = "cdns,combophy";
+ reg = <0x10808000 0x1000>;
+ resets = <&rst COMBOPHY_RESET>;
+ reset-names = "reset";
+ status = "disabled";
+ };
+
+ mmc: mmc0@10808000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "cdns,sd4hc";
+ reg = <0x10808000 0x1000>;
+ interrupts = <0 96 4>;
+ phys = <&combophy0>;
+ phy-names = "combo-phy";
+ clocks = <&clkmgr AGILEX5_L4_MP_CLK>,
+ <&clkmgr AGILEX5_SDMMC_CLK>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x800>;
+ resets = <&rst SDMMC_RESET>;
+ reset-names = "reset";
+ iommus = <&smmu 5>;
+ status = "disabled";
+ };
+
+ ocram: sram@00000000 {
+ compatible = "mmio-sram";
+ reg = <0x00000000 0x200000>;
+ };
+
+ rst: rstmgr@10d11000 {
+ #reset-cells = <1>;
+ compatible = "altr,stratix10-rst-mgr";
+ reg = <0x10d11000 0x1000>;
+ };
+
+ smmu: iommu@16000000 {
+ compatible = "arm,mmu-500", "arm,smmu-v2";
+ reg = <0x16000000 0x40000>;
+ #global-interrupts = <2>;
+ #iommu-cells = <1>;
+ interrupt-parent = <&intc>;
+ interrupts = <0 128 4>, /* Global Secure Fault */
+ <0 129 4>, /* Global Non-secure Fault */
+ /* Non-secure Context Interrupts (32) */
+ <0 138 4>, <0 139 4>, <0 140 4>, <0 141 4>,
+ <0 142 4>, <0 143 4>, <0 144 4>, <0 145 4>,
+ <0 146 4>, <0 147 4>, <0 148 4>, <0 149 4>,
+ <0 150 4>, <0 151 4>, <0 152 4>, <0 153 4>,
+ <0 154 4>, <0 155 4>, <0 156 4>, <0 157 4>,
+ <0 158 4>, <0 159 4>, <0 160 4>, <0 161 4>,
+ <0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
+ <0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
+ stream-match-mask = <0x7ff0>;
+ status = "disabled";
+ };
+
+ spi0: spi@10da4000 {
+ compatible = "intel,agilex-spi",
+ "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x10da4000 0x1000>;
+ interrupts = <0 99 4>;
+ resets = <&rst SPIM0_RESET>;
+ reg-io-width = <4>;
+ num-cs = <4>;
+ clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
+ status = "disabled";
+ };
+
+ spi1: spi@10da5000 {
+ compatible = "intel,agilex-spi",
+ "snps,dw-apb-ssi-4.00a", "snps,dw-apb-ssi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x10da5000 0x1000>;
+ interrupts = <0 100 4>;
+ resets = <&rst SPIM1_RESET>;
+ reg-io-width = <4>;
+ num-cs = <4>;
+ clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>;
+ status = "disabled";
+ };
+
+ sysmgr: sysmgr@10d12000 {
+ compatible = "altr,sys-mgr-s10","altr,sys-mgr";
+ reg = <0x10d12000 0x500>;
+ };
+
+ /* Local timer */
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <1 13 0xf08>,
+ <1 14 0xf08>,
+ <1 11 0xf08>,
+ <1 10 0xf08>;
+ };
+
+ timer0: timer0@10c03000 {
+ compatible = "snps,dw-apb-timer";
+ interrupts = <0 113 4>;
+ reg = <0x10c03000 0x100>;
+ resets = <&rst SPTIMER0_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
+ clock-names = "timer";
+ status = "disabled";
+ };
+
+ timer1: timer1@10c03100 {
+ compatible = "snps,dw-apb-timer";
+ interrupts = <0 114 4>;
+ reg = <0x10c03100 0x100>;
+ resets = <&rst SPTIMER1_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
+ clock-names = "timer";
+ status = "disabled";
+ };
+
+ timer2: timer2@10d00000 {
+ compatible = "snps,dw-apb-timer";
+ interrupts = <0 115 4>;
+ reg = <0x10d00000 0x100>;
+ resets = <&rst L4SYSTIMER0_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
+ clock-names = "timer";
+ status = "disabled";
+ };
+
+ timer3: timer3@10d00100 {
+ compatible = "snps,dw-apb-timer";
+ interrupts = <0 116 4>;
+ reg = <0x10d00100 0x100>;
+ resets = <&rst L4SYSTIMER1_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
+ clock-names = "timer";
+ status = "disabled";
+ };
+
+ uart0: serial0@10c02000 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x10c02000 0x100>;
+ interrupts = <0 108 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ resets = <&rst UART0_RESET>;
+ status = "disabled";
+ clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
+ clock-frequency = <100000000>;
+ };
+
+ uart1: serial1@10c02100 {
+ compatible = "snps,dw-apb-uart";
+ reg = <0x10c02100 0x100>;
+ interrupts = <0 109 4>;
+ reg-shift = <2>;
+ reg-io-width = <4>;
+ resets = <&rst UART1_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SP_CLK>;
+ status = "disabled";
+ };
+
+ usbphy0: usbphy@0 {
+ #phy-cells = <0>;
+ compatible = "usb-nop-xceiv";
+ clocks = <&clkmgr AGILEX5_USB_CLK>;
+ status = "disabled";
+ };
+
+ usb0: usb@10b00000 {
+ compatible = "snps,dwc2";
+ reg = <0x10b00000 0x40000>;
+ interrupts = <0 93 4>;
+ phys = <&usbphy0>;
+ phy-names = "usb2-phy";
+ resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
+ reset-names = "dwc2", "dwc2-ecc";
+ clocks = <&clkmgr AGILEX5_USB_CLK>;
+ iommus = <&smmu 6>;
+ status = "disabled";
+ };
+
+ usb31: usb31@11000000 {
+ compatible = "snps,dwc3";
+ reg = <0x11000000 0x100000>;
+ resets = <&rst USB1_RESET>;
+ phys = <&usbphy0>, <&usbphy0>;
+ phy-names = "usb2-phy", "usb3-phy";
+ dr_mode = "host";
+ maximum-speed = "super-speed";
+ snps,dis_u2_susphy_quirk;
+ status = "disabled";
+ };
+
+ watchdog0: watchdog@10d00200 {
+ compatible = "snps,dw-wdt";
+ reg = <0x10d00200 0x100>;
+ interrupts = <0 117 4>;
+ resets = <&rst WATCHDOG0_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
+ status = "disabled";
+ };
+
+ watchdog1: watchdog@10d00300 {
+ compatible = "snps,dw-wdt";
+ reg = <0x10d00300 0x100>;
+ interrupts = <0 118 4>;
+ resets = <&rst WATCHDOG1_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
+ status = "disabled";
+ };
+
+ watchdog2: watchdog@10d00400 {
+ compatible = "snps,dw-wdt";
+ reg = <0x10d00400 0x100>;
+ interrupts = <0 125 4>;
+ resets = <&rst WATCHDOG2_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
+ status = "disabled";
+ };
+
+ watchdog3: watchdog@10d00500 {
+ compatible = "snps,dw-wdt";
+ reg = <0x10d00500 0x100>;
+ interrupts = <0 126 4>;
+ resets = <&rst WATCHDOG3_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
+ status = "disabled";
+ };
+
+ watchdog4: watchdog@10d00600 {
+ compatible = "snps,dw-wdt";
+ reg = <0x10d00600 0x100>;
+ interrupts = <0 175 4>;
+ resets = <&rst WATCHDOG4_RESET>;
+ clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>;
+ status = "disabled";
+ };
+
+ /* QSPI address not available yet */
+ qspi: spi@108d2000 {
+ compatible = "cdns,qspi-nor";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x108d2000 0x100>,
+ <0x10900000 0x100000>;
+ interrupts = <0 3 4>;
+ cdns,fifo-depth = <128>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x00000000>;
+ clocks = <&qspi_clk>;
+
+ status = "disabled";
+ };
+
+ firmware {
+ svc {
+ compatible = "intel,stratix10-svc";
+ method = "smc";
+ memory-region = <&service_reserved>;
+
+ fpga_mgr: fpga-mgr {
+ compatible = "intel,stratix10-soc-fpga-mgr";
+ };
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
new file mode 100644
index 00000000000..9eb21d65428
--- /dev/null
+++ b/arch/arm/dts/socfpga_agilex5_socdk-u-boot.dtsi
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot additions
+ *
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ */
+
+#include "socfpga_agilex5-u-boot.dtsi"
+
+/{
+ aliases {
+ spi0 = &qspi;
+ freeze_br0 = &freeze_controller;
+ };
+
+ soc {
+ freeze_controller: freeze_controller@0x20000450 {
+ compatible = "altr,freeze-bridge-controller";
+ reg = <0x20000450 0x00000010>;
+ status = "disabled";
+ };
+ };
+
+ memory {
+ /* 8GB */
+ reg = <0 0x80000000 0 0x80000000>,
+ <8 0x80000000 1 0x80000000>;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ u-boot,spl-boot-order = &mmc,&flash0,"/memory";
+ };
+};
+
+&flash0 {
+ compatible = "jedec,spi-nor";
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ bootph-all;
+ /delete-property/ cdns,read-delay;
+};
+
+&i3c0 {
+ bootph-all;
+};
+
+&i3c1 {
+ bootph-all;
+};
+
+&mmc {
+ status = "okay";
+ bus-width = <4>;
+ sd-uhs-sdr50;
+ cap-mmc-highspeed;
+ bootph-all;
+};
+
+&combophy0 {
+ status = "okay";
+ bootph-all;
+ cdns,phy-use-ext-lpbk-dqs = <1>;
+ cdns,phy-use-lpbk-dqs = <1>;
+ cdns,phy-use-phony-dqs = <1>;
+ cdns,phy-use-phony-dqs-cmd = <1>;
+ cdns,phy-io-mask-always-on = <0>;
+ cdns,phy-io-mask-end = <5>;
+ cdns,phy-io-mask-start = <0>;
+ cdns,phy-data-select-oe-end = <1>;
+ cdns,phy-sync-method = <1>;
+ cdns,phy-sw-half-cycle-shift = <0>;
+ cdns,phy-rd-del-sel = <52>;
+ cdns,phy-underrun-suppress = <1>;
+ cdns,phy-gate-cfg-always-on = <1>;
+ cdns,phy-param-dll-bypass-mode = <1>;
+ cdns,phy-param-phase-detect-sel = <2>;
+ cdns,phy-param-dll-start-point = <254>;
+ cdns,phy-read-dqs-cmd-delay = <0>;
+ cdns,phy-clk-wrdqs-delay = <0>;
+ cdns,phy-clk-wr-delay = <0>;
+ cdns,phy-read-dqs-delay = <0>;
+ cdns,phy-phony-dqs-timing = <0>;
+ cdns,hrs09-rddata-en = <1>;
+ cdns,hrs09-rdcmd-en = <1>;
+ cdns,hrs09-extended-wr-mode = <1>;
+ cdns,hrs09-extended-rd-mode = <1>;
+ cdns,hrs10-hcsdclkadj = <3>;
+ cdns,hrs16-wrdata1-sdclk-dly = <0>;
+ cdns,hrs16-wrdata0-sdclk-dly = <0>;
+ cdns,hrs16-wrcmd1-sdclk-dly = <0>;
+ cdns,hrs16-wrcmd0-sdclk-dly = <0>;
+ cdns,hrs16-wrdata1-dly = <0>;
+ cdns,hrs16-wrdata0-dly = <0>;
+ cdns,hrs16-wrcmd1-dly = <0>;
+ cdns,hrs16-wrcmd0-dly = <0>;
+ cdns,hrs07-rw-compensate = <10>;
+ cdns,hrs07-idelay-val = <0>;
+};
+
+&qspi {
+ status = "okay";
+};
+
+&timer0 {
+ bootph-all;
+};
+
+&timer1 {
+ bootph-all;
+};
+
+&timer2 {
+ bootph-all;
+};
+
+&timer3 {
+ bootph-all;
+};
+
+&watchdog0 {
+ bootph-all;
+};
+
diff --git a/arch/arm/dts/socfpga_agilex5_socdk.dts b/arch/arm/dts/socfpga_agilex5_socdk.dts
new file mode 100644
index 00000000000..852e1e5ae3c
--- /dev/null
+++ b/arch/arm/dts/socfpga_agilex5_socdk.dts
@@ -0,0 +1,163 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ */
+#include "socfpga_agilex5.dtsi"
+
+/ {
+ model = "SoCFPGA Agilex5 SoCDK";
+
+ aliases {
+ serial0 = &uart0;
+ ethernet0 = &gmac0;
+ ethernet2 = &gmac2;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ hps0 {
+ label = "hps_led0";
+ gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
+ };
+
+ hps1 {
+ label = "hps_led1";
+ gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
+ };
+
+ hps2 {
+ label = "hps_led2";
+ gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the reg */
+ reg = <0 0 0 0>;
+ };
+
+ soc {
+ clocks {
+ osc1 {
+ clock-frequency = <25000000>;
+ };
+ };
+ };
+};
+
+&gpio0 {
+ status = "okay";
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+};
+
+&i2c1 {
+ status = "okay";
+};
+
+&i3c0 {
+ status = "okay";
+};
+
+&i3c1 {
+ status = "okay";
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&usbphy0 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ disable-over-current;
+};
+
+&watchdog0 {
+ status = "okay";
+};
+
+&watchdog1 {
+ status = "okay";
+};
+
+&watchdog2 {
+ status = "okay";
+};
+
+&watchdog3 {
+ status = "okay";
+};
+
+&watchdog4 {
+ status = "okay";
+};
+
+&timer0 {
+ status = "okay";
+};
+
+&timer1 {
+ status = "okay";
+};
+
+&timer2 {
+ status = "okay";
+};
+
+&timer3 {
+ status = "okay";
+};
+
+&spi0 {
+ status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+};
+
+&qspi {
+ flash0: flash@0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "mt25qu02g";
+ reg = <0>;
+ spi-max-frequency = <100000000>;
+
+ m25p,fast-read;
+ cdns,page-size = <256>;
+ cdns,block-size = <16>;
+ cdns,read-delay = <1>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qspi_boot: partition@0 {
+ label = "u-boot";
+ reg = <0x0 0x04200000>;
+ };
+
+ root: partition@4200000 {
+ label = "root";
+ reg = <0x04200000 0x0BE00000>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
index 84b91e8df09..15306db6002 100644
--- a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
+++ b/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
@@ -2,7 +2,7 @@
/*
* U-Boot additions
*
- * Copyright (C) 2020 Intel Corporation <www.intel.com>
+ * Copyright (C) 2020-2024 Intel Corporation <www.intel.com>
*/
#if defined(CONFIG_FIT)
@@ -21,14 +21,18 @@
description = "FIT with firmware and bootloader";
#address-cells = <1>;
- images {
+ images: images {
uboot {
description = "U-Boot SoC64";
type = "standalone";
os = "U-Boot";
arch = "arm64";
compression = "none";
+ #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+ load = <0x80200000>;
+ #else
load = <0x00200000>;
+ #endif
uboot_blob: blob-ext {
filename = "u-boot-nodtb.bin";
};
@@ -43,8 +47,13 @@
os = "arm-trusted-firmware";
arch = "arm64";
compression = "none";
+ #if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+ load = <0x80000000>;
+ entry = <0x80000000>;
+ #else
load = <0x00001000>;
entry = <0x00001000>;
+ #endif
atf_blob: blob-ext {
filename = "bl31.bin";
};
@@ -53,11 +62,11 @@
};
};
- fdt {
- description = "U-Boot SoC64 flat device-tree";
+ fdt-0 {
+ description = "socfpga_socdk";
type = "flat_dt";
compression = "none";
- uboot_fdt_blob: blob-ext {
+ fdt_0_blob: blob-ext {
filename = "u-boot.dtb";
};
hash {
@@ -66,17 +75,18 @@
};
};
- configurations {
- default = "conf";
- conf {
- description = "Intel SoC64 FPGA";
+ board_config: configurations {
+ default = "board-0";
+
+ board-0 {
+ description = "board_0";
firmware = "atf";
loadables = "uboot";
- fdt = "fdt";
+ fdt = "fdt-0";
signature {
algo = "crc32";
key-name-hint = "dev";
- sign-images = "atf", "fdt", "uboot";
+ sign-images = "atf", "uboot", "fdt-0";
};
};
};
@@ -96,8 +106,8 @@
arch = "arm64";
os = "linux";
compression = "none";
- load = <0x4080000>;
- entry = <0x4080000>;
+ load = <0x6000000>;
+ entry = <0x6000000>;
kernel_blob: blob-ext {
filename = "Image";
};
@@ -146,7 +156,7 @@
filename = "signed-bl31.bin";
};
-&uboot_fdt_blob {
+&fdt_0_blob {
filename = "signed-u-boot.dtb";
};
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 114d2438129..1008232cac8 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -8,7 +8,8 @@ config NR_DRAM_BANKS
config SOCFPGA_SECURE_VAB_AUTH
bool "Enable boot image authentication with Secure Device Manager"
- depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X
+ depends on TARGET_SOCFPGA_AGILEX || TARGET_SOCFPGA_N5X || \
+ TARGET_SOCFPGA_AGILEX5
select FIT_IMAGE_POST_PROCESS
select SHA384
select SHA512
@@ -58,6 +59,15 @@ config TARGET_SOCFPGA_AGILEX
select SPL_CLK if SPL
select TARGET_SOCFPGA_SOC64
+config TARGET_SOCFPGA_AGILEX5
+ bool
+ select BINMAN if SPL_ATF
+ select CLK
+ select FPGA_INTEL_SDM_MAILBOX
+ select GICV3
+ select SPL_CLK if SPL
+ select TARGET_SOCFPGA_SOC64
+
config TARGET_SOCFPGA_ARRIA5
bool
select TARGET_SOCFPGA_GEN5
@@ -129,6 +139,10 @@ config TARGET_SOCFPGA_AGILEX_SOCDK
bool "Intel SOCFPGA SoCDK (Agilex)"
select TARGET_SOCFPGA_AGILEX
+config TARGET_SOCFPGA_AGILEX5_SOCDK
+ bool "Intel SOCFPGA SoCDK (Agilex5)"
+ select TARGET_SOCFPGA_AGILEX5
+
config TARGET_SOCFPGA_ARIES_MCVEVK
bool "Aries MCVEVK (Cyclone V)"
select TARGET_SOCFPGA_CYCLONE5
@@ -202,6 +216,7 @@ config TARGET_SOCFPGA_TERASIC_SOCKIT
endchoice
config SYS_BOARD
+ default "agilex5-socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK
default "agilex-socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
default "arria5-socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
default "arria10-socdk" if TARGET_SOCFPGA_ARRIA10_SOCDK
@@ -223,6 +238,7 @@ config SYS_BOARD
default "vining_fpga" if TARGET_SOCFPGA_SOFTING_VINING_FPGA
config SYS_VENDOR
+ default "intel" if TARGET_SOCFPGA_AGILEX5_SOCDK
default "intel" if TARGET_SOCFPGA_AGILEX_SOCDK
default "intel" if TARGET_SOCFPGA_N5X_SOCDK
default "altera" if TARGET_SOCFPGA_ARRIA5_SOCDK
@@ -245,6 +261,7 @@ config SYS_SOC
default "socfpga"
config SYS_CONFIG_NAME
+ default "socfpga_agilex5_socdk" if TARGET_SOCFPGA_AGILEX5_SOCDK
default "socfpga_agilex_socdk" if TARGET_SOCFPGA_AGILEX_SOCDK
default "socfpga_arria5_secu1" if TARGET_SOCFPGA_ARRIA5_SECU1
default "socfpga_arria5_socdk" if TARGET_SOCFPGA_ARRIA5_SOCDK
diff --git a/arch/arm/mach-socfpga/Makefile b/arch/arm/mach-socfpga/Makefile
index ec38b64dd4d..67c6a8dfec5 100644
--- a/arch/arm/mach-socfpga/Makefile
+++ b/arch/arm/mach-socfpga/Makefile
@@ -4,7 +4,7 @@
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
-# Copyright (C) 2017-2021 Intel Corporation <www.intel.com>
+# Copyright (C) 2017-2024 Intel Corporation <www.intel.com>
obj-y += board.o
obj-y += clock_manager.o
@@ -56,6 +56,15 @@ obj-y += wrap_handoff_soc64.o
obj-y += wrap_pll_config_soc64.o
endif
+ifdef CONFIG_TARGET_SOCFPGA_AGILEX5
+obj-y += clock_manager_agilex5.o
+obj-y += mailbox_s10.o
+obj-y += misc_soc64.o
+obj-y += mmu-arm64_s10.o
+obj-y += reset_manager_s10.o
+obj-y += wrap_pll_config_soc64.o
+endif
+
ifdef CONFIG_TARGET_SOCFPGA_N5X
obj-y += clock_manager_n5x.o
obj-y += lowlevel_init_soc64.o
@@ -95,6 +104,9 @@ endif
ifdef CONFIG_TARGET_SOCFPGA_N5X
obj-y += spl_n5x.o
endif
+ifdef CONFIG_TARGET_SOCFPGA_AGILEX5
+obj-y += spl_soc64.o
+endif
else
obj-$(CONFIG_SPL_ATF) += secure_reg_helper.o
obj-$(CONFIG_SPL_ATF) += smc_api.o
diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c
index 09e09192fba..616e1afe5de 100644
--- a/arch/arm/mach-socfpga/board.c
+++ b/arch/arm/mach-socfpga/board.c
@@ -7,9 +7,11 @@
#include <common.h>
#include <asm/arch/clock_manager.h>
+#include <asm/arch/mailbox_s10.h>
#include <asm/arch/misc.h>
#include <asm/arch/reset_manager.h>
#include <asm/arch/secure_vab.h>
+#include <asm/arch/smc_api.h>
#include <asm/global_data.h>
#include <asm/io.h>
#include <errno.h>
@@ -23,6 +25,8 @@
DECLARE_GLOBAL_DATA_PTR;
+#define DEFAULT_JTAG_USERCODE 0xFFFFFFFF
+
void s_init(void) {
#ifndef CONFIG_ARM64
/*
@@ -92,13 +96,50 @@ int g_dnl_board_usb_cable_connected(void)
}
#endif
-#ifdef CONFIG_SPL_BUILD
-__weak int board_fit_config_name_match(const char *name)
+u8 socfpga_get_board_id(void)
{
- /* Just empty function now - can't decide what to choose */
- debug("%s: %s\n", __func__, name);
+ u8 board_id = 0;
+ u32 jtag_usercode;
+ int err;
- return 0;
+#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_SPL_ATF)
+ err = smc_get_usercode(&jtag_usercode);
+#else
+ u32 resp_len = 1;
+
+ err = mbox_send_cmd(MBOX_ID_UBOOT, MBOX_GET_USERCODE, MBOX_CMD_DIRECT, 0,
+ NULL, 0, &resp_len, &jtag_usercode);
+#endif
+
+ if (err) {
+ puts("Fail to read JTAG Usercode. Default Board ID to 0\n");
+ return board_id;
+ }
+
+ debug("Valid JTAG Usercode: %u\n", jtag_usercode);
+
+ if (jtag_usercode == DEFAULT_JTAG_USERCODE) {
+ debug("JTAG Usercode is not set. Default Board ID to 0\n");
+ } else if (jtag_usercode >= 0 && jtag_usercode <= 255) {
+ board_id = jtag_usercode;
+ debug("Valid JTAG Usercode. Set Board ID to %u\n", board_id);
+ } else {
+ puts("Board ID is not in range 0 to 255\n");
+ }
+
+ return board_id;
+}
+
+#if IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_TARGET_SOCFPGA_SOC64)
+int board_fit_config_name_match(const char *name)
+{
+ char board_name[10];
+
+ sprintf(board_name, "board_%u", socfpga_get_board_id());
+
+ debug("Board name: %s\n", board_name);
+
+ return strcmp(name, board_name);
}
#endif
@@ -116,6 +157,8 @@ void board_fit_image_post_process(const void *fit, int node, void **p_image,
#if !IS_ENABLED(CONFIG_SPL_BUILD) && IS_ENABLED(CONFIG_FIT)
void board_prep_linux(struct bootm_headers *images)
{
+ bool use_fit = false;
+
if (!images->fit_uname_cfg) {
if (IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH) &&
!IS_ENABLED(CONFIG_SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE)) {
@@ -127,12 +170,13 @@ void board_prep_linux(struct bootm_headers *images)
hang();
}
} else {
+ use_fit = true;
/* Update fdt_addr in enviroment variable */
env_set_hex("fdt_addr", (ulong)images->ft_addr);
debug("images->ft_addr = 0x%08lx\n", (ulong)images->ft_addr);
}
- if (IS_ENABLED(CONFIG_CADENCE_QSPI)) {
+ if (use_fit && IS_ENABLED(CONFIG_CADENCE_QSPI)) {
if (env_get("linux_qspi_enable"))
run_command(env_get("linux_qspi_enable"), 0);
}
diff --git a/arch/arm/mach-socfpga/clock_manager_agilex5.c b/arch/arm/mach-socfpga/clock_manager_agilex5.c
new file mode 100644
index 00000000000..b92f0b3af80
--- /dev/null
+++ b/arch/arm/mach-socfpga/clock_manager_agilex5.c
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ *
+ */
+
+#include <clk.h>
+#include <config.h>
+#include <dm.h>
+#include <errno.h>
+#include <log.h>
+#include <malloc.h>
+#include <stdarg.h>
+#include <stdio.h>
+#include <time.h>
+#include <vsprintf.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/u-boot.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/types.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/system_manager.h>
+#include <dt-bindings/clock/agilex5-clock.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static ulong cm_get_rate_dm(u32 id)
+{
+ struct udevice *dev;
+ struct clk clk;
+ ulong rate;
+ int ret;
+
+ ret = uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(socfpga_agilex5_clk),
+ &dev);
+ if (ret)
+ return 0;
+
+ clk.id = id;
+ ret = clk_request(dev, &clk);
+ if (ret < 0)
+ return 0;
+
+ rate = clk_get_rate(&clk);
+
+ if ((rate == (unsigned long)-ENOSYS) ||
+ (rate == (unsigned long)-ENXIO) ||
+ (rate == (unsigned long)-EIO)) {
+ debug("%s id %u: clk_get_rate err: %ld\n",
+ __func__, id, rate);
+ return 0;
+ }
+
+ return rate;
+}
+
+static u32 cm_get_rate_dm_khz(u32 id)
+{
+ return cm_get_rate_dm(id) / 1000;
+}
+
+unsigned long cm_get_mpu_clk_hz(void)
+{
+ return cm_get_rate_dm(AGILEX5_MPU_CLK);
+}
+
+unsigned int cm_get_l4_sys_free_clk_hz(void)
+{
+ return cm_get_rate_dm(AGILEX5_L4_SYS_FREE_CLK);
+}
+
+void cm_print_clock_quick_summary(void)
+{
+ printf("MPU %10d kHz\n",
+ cm_get_rate_dm_khz(AGILEX5_MPU_CLK));
+ printf("L4 Main %8d kHz\n",
+ cm_get_rate_dm_khz(AGILEX5_L4_MAIN_CLK));
+ printf("L4 sys free %8d kHz\n",
+ cm_get_rate_dm_khz(AGILEX5_L4_SYS_FREE_CLK));
+ printf("L4 MP %8d kHz\n",
+ cm_get_rate_dm_khz(AGILEX5_L4_MP_CLK));
+ printf("L4 SP %8d kHz\n",
+ cm_get_rate_dm_khz(AGILEX5_L4_SP_CLK));
+ printf("SDMMC %8d kHz\n",
+ cm_get_rate_dm_khz(AGILEX5_SDMMC_CLK));
+}
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
index 3f899fcfa3a..65721098b2b 100644
--- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h
@@ -1,11 +1,46 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
- * Copyright (C) 2016-2021 Intel Corporation <www.intel.com>
+ * Copyright (C) 2016-2024 Intel Corporation <www.intel.com>
*/
#ifndef _SOCFPGA_SOC64_BASE_HARDWARE_H_
#define _SOCFPGA_SOC64_BASE_HARDWARE_H_
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define SOCFPGA_CCU_ADDRESS 0x1c000000
+#define SOCFPGA_F2SDRAM_MGR_ADDRESS 0x18001000
+#define SOCFPGA_SMMU_ADDRESS 0x16000000
+#define SOCFPGA_OCRAM_FIREWALL_ADDRESS 0x108cc400
+#define SOCFPGA_MAILBOX_ADDRESS 0x10a30000
+#define SOCFPGA_UART0_ADDRESS 0x10c02000
+#define SOCFPGA_UART1_ADDRESS 0x10c02100
+#define SOCFPGA_SPTIMER0_ADDRESS 0x10c03000
+#define SOCFPGA_SPTIMER1_ADDRESS 0x10c03100
+#define SOCFPGA_SYSTIMER0_ADDRESS 0x10d00000
+#define SOCFPGA_SYSTIMER1_ADDRESS 0x10d00100
+#define SOCFPGA_L4WD0_ADDRESS 0x10d00200
+#define SOCFPGA_L4WD1_ADDRESS 0x10d00300
+#define SOCFPGA_L4WD2_ADDRESS 0x10d00400
+#define SOCFPGA_L4WD3_ADDRESS 0x10d00500
+#define SOCFPGA_L4WD4_ADDRESS 0x10d00600
+#define SOCFPGA_GTIMER_SEC_ADDRESS 0x10d01000
+#define SOCFPGA_GTIMER_NSEC_ADDRESS 0x10d02000
+#define SOCFPGA_CLKMGR_ADDRESS 0x10d10000
+#define SOCFPGA_RSTMGR_ADDRESS 0x10d11000
+#define SOCFPGA_SYSMGR_ADDRESS 0x10d12000
+#define SOCFPGA_OCRAM_ADDRESS 0x00000000
+#define SOCFPGA_FW_DDR_CCU_DMI0_ADDRESS 0x18000800
+#define SOCFPGA_FW_DDR_CCU_DMI1_ADDRESS 0x18000A00
+#define SOCFPGA_FW_TBU2NOC_ADDRESS 0x18000C00
+#define SOCFPGA_FIREWALL_L4_PER 0x10d21000
+#define SOCFPGA_FIREWALL_L4_SYS 0x10d21100
+#define SOCFPGA_FIREWALL_SOC2FPGA 0x10d21200
+#define SOCFPGA_FIREWALL_LWSOC2FPGA 0x10d21300
+#define SOCFPGA_FIREWALL_TCU 0x10d21400
+#define SOCFPGA_FIREWALL_PRIV_MEMORYMAP_PRIV 0x10d24800
+#define GICD_BASE 0x1d000000
+#define GICR_BASE 0x1d060000
+#else
#define SOCFPGA_CCU_ADDRESS 0xf7000000
#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xf8000400
#define SOCFPGA_HMC_MMR_IO48_ADDRESS 0xf8010000
@@ -44,5 +79,6 @@
#define SOCFPGA_OCRAM_ADDRESS 0xffe00000
#define GICD_BASE 0xfffc1000
#define GICC_BASE 0xfffc2000
+#endif /* IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) */
#endif /* _SOCFPGA_SOC64_BASE_HARDWARE_H_ */
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h
index a8cb07a1c47..6c9d32b9dd8 100644
--- a/arch/arm/mach-socfpga/include/mach/clock_manager.h
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
- * Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
+ * Copyright (C) 2013-2024 Altera Corporation <www.altera.com>
*/
#ifndef _CLOCK_MANAGER_H_
@@ -28,6 +28,8 @@ int cm_set_qspi_controller_clk_hz(u32 clk_hz);
#include <asm/arch/clock_manager_s10.h>
#elif defined(CONFIG_TARGET_SOCFPGA_AGILEX)
#include <asm/arch/clock_manager_agilex.h>
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#include <asm/arch/clock_manager_agilex5.h>
#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
#include <asm/arch/clock_manager_n5x.h>
#endif
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager_agilex5.h b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex5.h
new file mode 100644
index 00000000000..1ae0a926032
--- /dev/null
+++ b/arch/arm/mach-socfpga/include/mach/clock_manager_agilex5.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2024 Intel Corporation <www.intel.com>
+ */
+
+#ifndef _CLOCK_MANAGER_AGILEX5_
+#define _CLOCK_MANAGER_AGILEX5_
+
+#include <asm/arch/clock_manager_soc64.h>
+#include "../../../../../drivers/clk/altera/clk-agilex5.h"
+
+#endif /* _CLOCK_MANAGER_AGILEX5_ */
diff --git a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
index 9b85e5865ba..d839f288411 100644
--- a/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
+++ b/arch/arm/mach-socfpga/include/mach/handoff_soc64.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0
*
- * Copyright (C) 2016-2021 Intel Corporation <www.intel.com>
+ * Copyright (C) 2016-2024 Intel Corporation <www.intel.com>
*
*/
@@ -17,7 +17,12 @@
#define SOC64_HANDOFF_MAGIC_FPGA 0x46504741
#define SOC64_HANDOFF_MAGIC_DELAY 0x444C4159
#define SOC64_HANDOFF_MAGIC_CLOCK 0x434C4B53
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define SOC64_HANDOFF_MAGIC_PERI 0x50455249
+#define SOC64_HANDOFF_MAGIC_SDRAM 0x5344524d
+#else
#define SOC64_HANDOFF_MAGIC_MISC 0x4D495343
+#endif
#define SOC64_HANDOFF_OFFSET_LENGTH 0x4
#define SOC64_HANDOFF_OFFSET_DATA 0x10
@@ -27,6 +32,8 @@
IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX)
#define SOC64_HANDOFF_BASE 0xFFE3F000
#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x610)
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define SOC64_HANDOFF_BASE 0x0007F000
#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X)
#define SOC64_HANDOFF_BASE 0xFFE5F000
#define SOC64_HANDOFF_MISC (SOC64_HANDOFF_BASE + 0x630)
@@ -58,13 +65,21 @@
#define SOC64_HANDOFF_FPGA (SOC64_HANDOFF_BASE + 0x330)
#define SOC64_HANDOFF_DELAY (SOC64_HANDOFF_BASE + 0x3F0)
#define SOC64_HANDOFF_CLOCK (SOC64_HANDOFF_BASE + 0x580)
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define SOC64_HANDOFF_PERI (SOC64_HANDOFF_BASE + 0x620)
+#define SOC64_HANDOFF_SDRAM (SOC64_HANDOFF_BASE + 0x634)
+#define SOC64_HANDOFF_SDRAM_LEN 1
+#endif
#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_STRATIX10)
-#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x608)
-#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x60C)
+#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x608)
+#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x60C)
+#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x60c)
+#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x610)
#else
-#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x5fc)
-#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x600)
+#define SOC64_HANDOFF_CLOCK_OSC (SOC64_HANDOFF_BASE + 0x5fc)
+#define SOC64_HANDOFF_CLOCK_FPGA (SOC64_HANDOFF_BASE + 0x600)
#endif
#define SOC64_HANDOFF_MUX_LEN 96
diff --git a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
index fbaf11597ed..2cc7c890449 100644
--- a/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
+++ b/arch/arm/mach-socfpga/include/mach/mailbox_s10.h
@@ -119,6 +119,7 @@ enum ALT_SDM_MBOX_RESP_CODE {
#define MBOX_RECONFIG_DATA 8
#define MBOX_RECONFIG_STATUS 9
#define MBOX_VAB_SRC_CERT 11
+#define MBOX_GET_USERCODE 19
#define MBOX_QSPI_OPEN 50
#define MBOX_QSPI_CLOSE 51
#define MBOX_QSPI_DIRECT 59
diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach-socfpga/mmu-arm64_s10.c
index a55b7b7cf3b..91c6d7c55f1 100644
--- a/arch/arm/mach-socfpga/mmu-arm64_s10.c
+++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
+ * Copyright (C) 2016-2024 Intel Corporation <www.intel.com>
*
*/
@@ -10,6 +10,62 @@
DECLARE_GLOBAL_DATA_PTR;
+#if IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5)
+static struct mm_region socfpga_agilex5_mem_map[] = {
+ {
+ /* OCRAM 512KB */
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x00080000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE,
+ }, {
+ /* DEVICE */
+ .virt = 0x10808000UL,
+ .phys = 0x10808000UL,
+ .size = 0x0F7F8000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+ }, {
+ /* FPGA 1.5GB */
+ .virt = 0x20000000UL,
+ .phys = 0x20000000UL,
+ .size = 0x60000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+ }, {
+ /* FPGA 15GB */
+ .virt = 0x440000000UL,
+ .phys = 0x440000000UL,
+ .size = 0x3C0000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+ }, {
+ /* FPGA 240GB */
+ .virt = 0x4400000000UL,
+ .phys = 0x4400000000UL,
+ .size = 0x3C00000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN,
+ }, {
+ /* MEM 2GB */
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE,
+ }, {
+ /* List terminator */
+ },
+};
+
+struct mm_region *mem_map = socfpga_agilex5_mem_map;
+
+#else
static struct mm_region socfpga_stratix10_mem_map[] = {
{
/* MEM 2GB*/
@@ -70,3 +126,4 @@ static struct mm_region socfpga_stratix10_mem_map[] = {
};
struct mm_region *mem_map = socfpga_stratix10_mem_map;
+#endif
diff --git a/arch/arm/mach-socfpga/wrap_handoff_soc64.c b/arch/arm/mach-socfpga/wrap_handoff_soc64.c
index df0701ec85e..6aa9bb26b4e 100644
--- a/arch/arm/mach-socfpga/wrap_handoff_soc64.c
+++ b/arch/arm/mach-socfpga/wrap_handoff_soc64.c
@@ -11,7 +11,6 @@
#include "log.h"
#ifndef __ASSEMBLY__
-#include <asm/types.h>
enum endianness {
LITTLE_ENDIAN = 0,
BIG_ENDIAN,
generated by cgit v1.2.3 (git 2.39.1) at 2024-09-20 19:33:05 +0000