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-rw-r--r--arch/arm/dts/Makefile1
-rw-r--r--arch/arm/dts/rk3368-lion-u-boot.dtsi88
-rw-r--r--arch/arm/dts/rk3368-lion.dts195
-rw-r--r--arch/arm/dts/rk3368.dtsi4
-rw-r--r--arch/arm/mach-rockchip/rk3368/Kconfig21
5 files changed, 305 insertions, 4 deletions
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index c2dc240edf6..2cbdb17ca54 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -42,6 +42,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \
rk3288-veyron-mickey.dtb \
rk3288-veyron-minnie.dtb \
rk3328-evb.dtb \
+ rk3368-lion.dtb \
rk3368-sheep.dtb \
rk3368-geekbox.dtb \
rk3368-px5-evb.dtb \
diff --git a/arch/arm/dts/rk3368-lion-u-boot.dtsi b/arch/arm/dts/rk3368-lion-u-boot.dtsi
new file mode 100644
index 00000000000..2053fb14954
--- /dev/null
+++ b/arch/arm/dts/rk3368-lion-u-boot.dtsi
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/ {
+ config {
+ u-boot,spl-payload-offset = <0x40000>; /* @ 256KB */
+ u-boot,mmc-env-offset = <0x4000>; /* @ 16KB */
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ u-boot,spl-boot-order = &emmc, &sdmmc;
+ };
+
+};
+
+&pinctrl {
+ u-boot,dm-pre-reloc;
+};
+
+&service_msch {
+ u-boot,dm-pre-reloc;
+};
+
+&dmc {
+ u-boot,dm-pre-reloc;
+
+ /*
+ * Validation of throughput using SPEC2000 shows the following
+ * relative performance for the different memory schedules:
+ * - CBDR: 30.1
+ * - CBRD: 29.8
+ * - CRBD: 29.9
+ * Note that the best performance for any given application workload
+ * may vary from the default configured here (e.g. 164.gzip is fastest
+ * with CBRD, whereas 252.eon and 186.crafty are fastest with CRBD).
+ *
+ * See doc/device-tree-bindings/clock/rockchip,rk3368-dmc.txt for
+ * details on the 'rockchip,memory-schedule' property and how it
+ * affects the physical-address to device-address mapping.
+ */
+ rockchip,memory-schedule = <DMC_MSCH_CBDR>;
+ rockchip,ddr-frequency = <800000000>;
+ rockchip,ddr-speed-bin = <DDR3_1600K>;
+
+ status = "okay";
+};
+
+&pmugrf {
+ u-boot,dm-pre-reloc;
+};
+
+&sgrf {
+ u-boot,dm-pre-reloc;
+};
+
+&cru {
+ u-boot,dm-pre-reloc;
+};
+
+&grf {
+ u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+};
+
+&emmc {
+ u-boot,dm-pre-reloc;
+};
+
+&sdmmc {
+ u-boot,dm-pre-reloc;
+};
+
+&spi1 {
+ u-boot,dm-pre-reloc;
+
+ spiflash: w25q32dw@0 {
+ u-boot,dm-pre-reloc;
+ };
+};
+
+
diff --git a/arch/arm/dts/rk3368-lion.dts b/arch/arm/dts/rk3368-lion.dts
new file mode 100644
index 00000000000..850db500e4e
--- /dev/null
+++ b/arch/arm/dts/rk3368-lion.dts
@@ -0,0 +1,195 @@
+/*
+ * (C) Copyright 2017 Theobroma Systems Design und Consulting GmbH
+ *
+ * SPDX-License-Identifier: GPL-2.0+ X11
+ */
+
+/dts-v1/;
+#include "rk3368.dtsi"
+#include "rk3368-lion-u-boot.dtsi"
+#include <dt-bindings/input/input.h>
+
+/ {
+ model = "Theobroma Systems RK3368-uQ7 SoM";
+ compatible = "tsd,rk3368-uq7", "tsd,lion", "rockchip,rk3368";
+
+ aliases {
+ mmc0 = &emmc;
+ mmc1 = &sdmmc;
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ ext_gmac: gmac-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "ext_gmac";
+ #clock-cells = <0>;
+ };
+
+ vcc_sys: vcc-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_sys";
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ regulator-always-on;
+ regulator-boot-on;
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&emmc {
+ status = "okay";
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ clock-frequency = <150000000>;
+ disable-wp;
+ keep-power-in-suspend;
+ non-removable;
+ num-slots = <1>;
+ vmmc-supply = <&vcc33_io>;
+ vqmmc-supply = <&vcc18_io>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&emmc_clk>, <&emmc_cmd>, <&emmc_bus8>;
+};
+
+&sdmmc {
+ status = "okay";
+};
+
+&gmac {
+ status = "okay";
+ phy-supply = <&vcc33_io>;
+ phy-mode = "rgmii";
+ clock_in_out = "input";
+ snps,reset-gpio = <&gpio3 11 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <2 10000 50000>;
+ assigned-clocks = <&cru SCLK_MAC>;
+ assigned-clock-parents = <&ext_gmac>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&rgmii_pins>;
+ tx_delay = <0x10>;
+ rx_delay = <0x10>;
+};
+
+&i2c0 {
+ status = "okay";
+
+ rk808: pmic@1b {
+ compatible = "rockchip,rk808";
+ reg = <0x1b>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
+ rockchip,system-power-controller;
+ vcc1-supply = <&vcc_sys>;
+ vcc2-supply = <&vcc_sys>;
+ vcc3-supply = <&vcc_sys>;
+ vcc4-supply = <&vcc_sys>;
+ vcc6-supply = <&vcc_sys>;
+ vcc7-supply = <&vcc_sys>;
+ vcc8-supply = <&vcc_sys>;
+ vcc9-supply = <&vcc_sys>;
+ vcc10-supply = <&vcc_sys>;
+ vcc11-supply = <&vcc_sys>;
+ vcc12-supply = <&vcc_sys>;
+ clock-output-names = "xin32k", "rk808-clkout2";
+ #clock-cells = <1>;
+
+ regulators {
+ vdd_cpu: DCDC_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vdd_cpu";
+ };
+
+ vdd_log: DCDC_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <700000>;
+ regulator-max-microvolt = <1500000>;
+ regulator-name = "vdd_log";
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-name = "vcc_ddr";
+ };
+
+ vcc33_io: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc33_io";
+ };
+
+ vcc33_video: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc33_video";
+ };
+
+ vdd10_pll: LDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-name = "vdd10_pll";
+ };
+
+ vcc18_io: LDO_REG4 {
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc18_io";
+ };
+
+ vdd10_video: LDO_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1000000>;
+ regulator-name = "vdd10_video";
+ };
+
+ vcc18_video: LDO_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcc18_video";
+ };
+ };
+ };
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&spi1 {
+ status = "okay";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ spiflash: w25q32dw@0 {
+ compatible = "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <49500000>;
+ spi-cpol;
+ spi-cpha;
+ };
+};
diff --git a/arch/arm/dts/rk3368.dtsi b/arch/arm/dts/rk3368.dtsi
index 0dad34dc20a..22fb7e78943 100644
--- a/arch/arm/dts/rk3368.dtsi
+++ b/arch/arm/dts/rk3368.dtsi
@@ -238,7 +238,6 @@
};
service_msch: syscon@ffac0000 {
- u-boot,dm-pre-reloc;
compatible = "rockchip,rk3368-msch", "syscon";
reg = <0x0 0xffac0000 0x0 0x2000>;
status = "okay";
@@ -658,7 +657,6 @@
};
pmugrf: syscon@ff738000 {
- u-boot,dm-pre-reloc;
compatible = "rockchip,rk3368-pmugrf", "syscon";
reg = <0x0 0xff738000 0x0 0x1000>;
};
@@ -669,7 +667,6 @@
};
cru: clock-controller@ff760000 {
- u-boot,dm-pre-reloc;
compatible = "rockchip,rk3368-cru";
reg = <0x0 0xff760000 0x0 0x1000>;
rockchip,grf = <&grf>;
@@ -678,7 +675,6 @@
};
grf: syscon@ff770000 {
- u-boot,dm-pre-reloc;
compatible = "rockchip,rk3368-grf", "syscon";
reg = <0x0 0xff770000 0x0 0x1000>;
};
diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig
index 6d320689206..f8189f14687 100644
--- a/arch/arm/mach-rockchip/rk3368/Kconfig
+++ b/arch/arm/mach-rockchip/rk3368/Kconfig
@@ -3,6 +3,26 @@ if ROCKCHIP_RK3368
choice
prompt "RK3368 board"
+config TARGET_LION_RK3368
+ bool "Theobroma Systems RK3368-uQ7 (Lion) module"
+ help
+ The RK3368-uQ7 is a micro-Qseven form-factor (40mm x 70mm,
+ MXM-230 connector) system-on-module designed by Theobroma
+ Systems for industrial applications.
+
+ It provides the following features:
+ - 8x Cortex-A53 (in 2 clusters of 4 cores each)
+ - (on-module) up to 4GB of DDR3 memory
+ - (on-module) SPI-NOR flash
+ - (on-module) eMMC
+ - Gigabit Ethernet (with an on-module KSZ9031 PHY)
+ - USB
+ - HDMI
+ - MIPI-DSI/single-channel LVDS (muxed on the 'LVDS-A' pin-group)
+ - various 'slow' interfaces (e.g. UART, SPI, I2C, I2S, ...)
+ - on-module STM32 providing CAN, RTC and fan-control
+ - (optional on-module) EAL4+-certified security module
+
config TARGET_SHEEP
bool "Sheep board"
help
@@ -25,6 +45,7 @@ endchoice
config SYS_SOC
default "rockchip"
+source "board/theobroma-systems/lion_rk3368/Kconfig"
source "board/rockchip/sheep_rk3368/Kconfig"
source "board/geekbuying/geekbox/Kconfig"
source "board/rockchip/evb_px5/Kconfig"
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-11 10:54:47 +0000