aboutsummaryrefslogtreecommitdiff
path: root/arch/arm
diff options
context:
space:
mode:
Diffstat (limited to 'arch/arm')
-rw-r--r--arch/arm/Makefile8
-rw-r--r--arch/arm/cpu/armv7/cache_v7.c10
-rw-r--r--arch/arm/cpu/armv7/psci-common.c2
-rw-r--r--arch/arm/cpu/armv7/sunxi/psci.c12
-rw-r--r--arch/arm/include/asm/barriers.h11
-rw-r--r--arch/arm/include/asm/io.h4
-rw-r--r--arch/arm/include/asm/system.h8
-rw-r--r--arch/arm/lib/Makefile5
-rw-r--r--arch/arm/mach-exynos/include/mach/system.h10
-rw-r--r--arch/arm/mach-sunxi/dram_helpers.c2
-rw-r--r--arch/arm/mach-tegra/tegra20/Makefile3
11 files changed, 35 insertions, 40 deletions
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 6a07cd178e6..82f2fd0839d 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -20,6 +20,14 @@ arch-$(CONFIG_CPU_V7) =$(call cc-option, -march=armv7-a, \
$(call cc-option, -march=armv7, -march=armv5))
arch-$(CONFIG_ARM64) =-march=armv8-a
+# On Tegra systems we must build SPL for the armv4 core on the device
+# but otherwise we can use the value in CONFIG_SYS_ARM_ARCH
+ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TEGRA),yy)
+arch-y += -D__LINUX_ARM_ARCH__=4
+else
+arch-y += -D__LINUX_ARM_ARCH__=$(CONFIG_SYS_ARM_ARCH)
+endif
+
# Evaluate arch cc-option calls now
arch-y := $(arch-y)
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c
index 52f18565db2..c4bbcc3cc3e 100644
--- a/arch/arm/cpu/armv7/cache_v7.c
+++ b/arch/arm/cpu/armv7/cache_v7.c
@@ -75,7 +75,7 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op)
}
/* DSB to make sure the operation is complete */
- DSB;
+ dsb();
}
/* Invalidate TLB */
@@ -88,9 +88,9 @@ static void v7_inval_tlb(void)
/* Invalidate entire instruction TLB */
asm volatile ("mcr p15, 0, %0, c8, c5, 0" : : "r" (0));
/* Full system DSB - make sure that the invalidation is complete */
- DSB;
+ dsb();
/* Full system ISB - make sure the instruction stream sees it */
- ISB;
+ isb();
}
void invalidate_dcache_all(void)
@@ -194,10 +194,10 @@ void invalidate_icache_all(void)
asm volatile ("mcr p15, 0, %0, c7, c5, 6" : : "r" (0));
/* Full system DSB - make sure that the invalidation is complete */
- DSB;
+ dsb();
/* ISB - make sure the instruction stream sees it */
- ISB;
+ isb();
}
#else
void invalidate_icache_all(void)
diff --git a/arch/arm/cpu/armv7/psci-common.c b/arch/arm/cpu/armv7/psci-common.c
index d14b6937473..8cb4107be61 100644
--- a/arch/arm/cpu/armv7/psci-common.c
+++ b/arch/arm/cpu/armv7/psci-common.c
@@ -29,7 +29,7 @@ static u32 psci_target_pc[CONFIG_ARMV7_PSCI_NR_CPUS] __secure_data = { 0 };
void __secure psci_save_target_pc(int cpu, u32 pc)
{
psci_target_pc[cpu] = pc;
- DSB;
+ dsb();
}
u32 __secure psci_get_target_pc(int cpu)
diff --git a/arch/arm/cpu/armv7/sunxi/psci.c b/arch/arm/cpu/armv7/sunxi/psci.c
index 7ac84065f4a..766b8c79d93 100644
--- a/arch/arm/cpu/armv7/sunxi/psci.c
+++ b/arch/arm/cpu/armv7/sunxi/psci.c
@@ -53,16 +53,16 @@ static void __secure __mdelay(u32 ms)
u32 reg = ONE_MS * ms;
cp15_write_cntp_tval(reg);
- ISB;
+ isb();
cp15_write_cntp_ctl(3);
do {
- ISB;
+ isb();
reg = cp15_read_cntp_ctl();
} while (!(reg & BIT(2)));
cp15_write_cntp_ctl(0);
- ISB;
+ isb();
}
static void __secure clamp_release(u32 __maybe_unused *clamp)
@@ -164,7 +164,7 @@ static u32 __secure cp15_read_scr(void)
static void __secure cp15_write_scr(u32 scr)
{
asm volatile ("mcr p15, 0, %0, c1, c1, 0" : : "r" (scr));
- ISB;
+ isb();
}
/*
@@ -190,7 +190,7 @@ void __secure __irq psci_fiq_enter(void)
/* End of interrupt */
writel(reg, GICC_BASE + GICC_EOIR);
- DSB;
+ dsb();
/* Get CPU number */
cpu = (reg >> 10) & 0x7;
@@ -242,7 +242,7 @@ void __secure psci_cpu_off(void)
/* Ask CPU0 via SGI15 to pull the rug... */
writel(BIT(16) | 15, GICD_BASE + GICD_SGIR);
- DSB;
+ dsb();
/* Wait to be turned off */
while (1)
diff --git a/arch/arm/include/asm/barriers.h b/arch/arm/include/asm/barriers.h
index 37870f9d717..04784b7cb62 100644
--- a/arch/arm/include/asm/barriers.h
+++ b/arch/arm/include/asm/barriers.h
@@ -30,15 +30,22 @@
#endif /* !CONFIG_ARM64 */
-#if defined(__ARM_ARCH_7A__) || defined(CONFIG_ARM64)
+#if __LINUX_ARM_ARCH__ >= 7
#define ISB asm volatile ("isb sy" : : : "memory")
#define DSB asm volatile ("dsb sy" : : : "memory")
#define DMB asm volatile ("dmb sy" : : : "memory")
-#else
+#elif __LINUX_ARM_ARCH__ == 6
#define ISB CP15ISB
#define DSB CP15DSB
#define DMB CP15DMB
+#else
+#define ISB asm volatile ("" : : : "memory")
+#define DSB CP15DSB
+#define DMB asm volatile ("" : : : "memory")
#endif
+#define isb() ISB
+#define dsb() DSB
+#define dmb() DMB
#endif /* __ASSEMBLY__ */
#endif /* __BARRIERS_H__ */
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 6121f1ddcac..5834f5b3dc9 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -25,6 +25,7 @@
#include <linux/types.h>
#include <asm/byteorder.h>
#include <asm/memory.h>
+#include <asm/barriers.h>
#if 0 /* XXX###XXX */
#include <asm/arch/hardware.h>
#endif /* XXX###XXX */
@@ -136,8 +137,7 @@ static inline void __raw_readsl(unsigned long addr, void *data, int longlen)
* TODO: The kernel offers some more advanced versions of barriers, it might
* have some advantages to use them instead of the simple one here.
*/
-#define mb() asm volatile("dsb sy" : : : "memory")
-#define dmb() __asm__ __volatile__ ("" : : : "memory")
+#define mb() dsb()
#define __iormb() dmb()
#define __iowmb() dmb()
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 2bdc0bec824..7b7b8675215 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -3,6 +3,7 @@
#include <common.h>
#include <linux/compiler.h>
+#include <asm/barriers.h>
#ifdef CONFIG_ARM64
@@ -34,11 +35,6 @@ enum dcache_option {
DCACHE_WRITEALLOC = 4 << 2,
};
-#define isb() \
- ({asm volatile( \
- "isb" : : : "memory"); \
- })
-
#define wfi() \
({asm volatile( \
"wfi" : : : "memory"); \
@@ -227,8 +223,6 @@ void __noreturn psci_system_reset(bool smc);
*/
void save_boot_params_ret(void);
-#define isb() __asm__ __volatile__ ("" : : : "memory")
-
#define nop() __asm__ __volatile__("mov\tr0,r0\t@ nop\n\t");
#ifdef __ARM_ARCH_7A__
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile
index 9f71376d30a..a8d15576293 100644
--- a/arch/arm/lib/Makefile
+++ b/arch/arm/lib/Makefile
@@ -67,11 +67,6 @@ extra-y += eabi_compat.o
endif
asflags-y += -DCONFIG_ARM_ASM_UNIFIED
-ifeq ($(CONFIG_SPL_BUILD)$(CONFIG_TEGRA),yy)
-asflags-y += -D__LINUX_ARM_ARCH__=4
-else
-asflags-y += -D__LINUX_ARM_ARCH__=$(CONFIG_SYS_ARM_ARCH)
-endif
# some files can only build in ARM or THUMB2, not THUMB1
diff --git a/arch/arm/mach-exynos/include/mach/system.h b/arch/arm/mach-exynos/include/mach/system.h
index 3ffb296a57f..2c94a6bea0b 100644
--- a/arch/arm/mach-exynos/include/mach/system.h
+++ b/arch/arm/mach-exynos/include/mach/system.h
@@ -38,16 +38,6 @@ struct exynos5_sysreg {
#define USB20_PHY_CFG_HOST_LINK_EN (1 << 0)
/*
- * Data Synchronization Barrier acts as a special kind of memory barrier.
- * No instruction in program order after this instruction executes until
- * this instruction completes. This instruction completes when:
- * - All explicit memory accesses before this instruction complete.
- * - All Cache, Branch predictor and TLB maintenance operations before
- * this instruction complete.
- */
-#define dsb() __asm__ __volatile__ ("dsb\n\t" : : );
-
-/*
* This instruction causes an event to be signaled to all cores
* within a multiprocessor system. If SEV is implemented,
* WFE must also be implemented.
diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c
index 20b430f859a..95143d19ab5 100644
--- a/arch/arm/mach-sunxi/dram_helpers.c
+++ b/arch/arm/mach-sunxi/dram_helpers.c
@@ -32,7 +32,7 @@ bool mctl_mem_matches(u32 offset)
/* Try to write different values to RAM at two addresses */
writel(0, CONFIG_SYS_SDRAM_BASE);
writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset);
- DSB;
+ dsb();
/* Check if the same value is actually observed when reading back */
return readl(CONFIG_SYS_SDRAM_BASE) ==
readl((ulong)CONFIG_SYS_SDRAM_BASE + offset);
diff --git a/arch/arm/mach-tegra/tegra20/Makefile b/arch/arm/mach-tegra/tegra20/Makefile
index 17c19900e21..72d82a5218f 100644
--- a/arch/arm/mach-tegra/tegra20/Makefile
+++ b/arch/arm/mach-tegra/tegra20/Makefile
@@ -10,7 +10,8 @@ endif
# The AVP is ARMv4T architecture so we must use special compiler
# flags for any startup files it might use.
-CFLAGS_warmboot_avp.o += -march=armv4t
+CFLAGS_warmboot_avp.o = -march=armv4t -U__LINUX_ARM_ARCH__ \
+ -D__LINUX_ARM_ARCH__=4
obj-y += clock.o funcmux.o pinmux.o
obj-$(CONFIG_TEGRA_LP0) += warmboot.o crypto.o warmboot_avp.o
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-11 17:26:29 +0000