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-rw-r--r--arch/powerpc/cpu/mpc85xx/Makefile2
-rw-r--r--arch/powerpc/cpu/mpc85xx/cmd_errata.c3
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu.c24
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu_init.c17
-rw-r--r--arch/powerpc/cpu/mpc85xx/cpu_init_early.c2
-rw-r--r--arch/powerpc/cpu/mpc85xx/fdt.c2
-rw-r--r--arch/powerpc/cpu/mpc85xx/speed.c3
-rw-r--r--arch/powerpc/cpu/mpc85xx/spl_minimal.c4
-rw-r--r--arch/powerpc/cpu/mpc85xx/start.S4
-rw-r--r--arch/powerpc/cpu/mpc85xx/t4240_ids.c2
-rw-r--r--arch/powerpc/cpu/mpc85xx/t4240_serdes.c2
-rw-r--r--arch/powerpc/cpu/mpc85xx/u-boot-nand.lds2
-rw-r--r--arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds2
-rw-r--r--arch/powerpc/cpu/mpc85xx/u-boot-spl.lds2
-rw-r--r--arch/powerpc/cpu/mpc85xx/u-boot.lds2
-rw-r--r--arch/powerpc/cpu/mpc86xx/start.S1
-rw-r--r--arch/powerpc/cpu/mpc8xxx/cpu.c6
17 files changed, 64 insertions, 16 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile
index 409478539ec..ad26b432f18 100644
--- a/arch/powerpc/cpu/mpc85xx/Makefile
+++ b/arch/powerpc/cpu/mpc85xx/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_PPC_P5020) += p5020_ids.o
obj-$(CONFIG_PPC_P5040) += p5040_ids.o
obj-$(CONFIG_PPC_T4240) += t4240_ids.o
obj-$(CONFIG_PPC_T4160) += t4240_ids.o
+obj-$(CONFIG_PPC_T4080) += t4240_ids.o
obj-$(CONFIG_PPC_B4420) += b4860_ids.o
obj-$(CONFIG_PPC_B4860) += b4860_ids.o
obj-$(CONFIG_PPC_T1040) += t1040_ids.o
@@ -88,6 +89,7 @@ obj-$(CONFIG_PPC_P5020) += p5020_serdes.o
obj-$(CONFIG_PPC_P5040) += p5040_serdes.o
obj-$(CONFIG_PPC_T4240) += t4240_serdes.o
obj-$(CONFIG_PPC_T4160) += t4240_serdes.o
+obj-$(CONFIG_PPC_T4080) += t4240_serdes.o
obj-$(CONFIG_PPC_B4420) += b4860_serdes.o
obj-$(CONFIG_PPC_B4860) += b4860_serdes.o
obj-$(CONFIG_BSC9132) += bsc9132_serdes.o
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
index 9d8acd0aa17..3d37a7614f9 100644
--- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c
+++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c
@@ -299,6 +299,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
check_erratum_a007212();
#endif
+#ifdef CONFIG_SYS_FSL_ERRATUM_A005434
+ puts("Work-around for Erratum A-005434 enabled\n");
+#endif
return 0;
}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 12e8e10d483..684d4007e48 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -77,6 +77,30 @@ int checkcpu (void)
major = SVR_MAJ(svr);
minor = SVR_MIN(svr);
+#if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500)
+ if (SVR_SOC_VER(svr) == SVR_T4080) {
+ ccsr_rcpm_t *rcpm =
+ (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR);
+
+ setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 ||
+ FSL_CORENET_DEVDISR2_DTSEC1_9);
+ setbits_be32(&gur->devdisr3, FSL_CORENET_DEVDISR3_PCIE3);
+ setbits_be32(&gur->devdisr5, FSL_CORENET_DEVDISR5_DDR3);
+
+ /* It needs SW to disable core4~7 as HW design sake on T4080 */
+ for (i = 4; i < 8; i++)
+ cpu_disable(i);
+
+ /* request core4~7 into PH20 state, prior to entering PCL10
+ * state, all cores in cluster should be placed in PH20 state.
+ */
+ setbits_be32(&rcpm->pcph20setr, 0xf0);
+
+ /* put the 2nd cluster into PCL10 state */
+ setbits_be32(&rcpm->clpcl10setr, 1 << 1);
+ }
+#endif
+
if (cpu_numcores() > 1) {
#ifndef CONFIG_MP
puts("Unicore software on multiprocessor system!!\n"
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 36ef23232ed..d6cf88555a1 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -368,12 +368,12 @@ void fsl_erratum_a007212_workaround(void)
}
#endif
-void cpu_init_f (void)
+ulong cpu_init_f(void)
{
+ ulong flag = 0;
extern void m8560_cpm_reset (void);
#ifdef CONFIG_SYS_DCSRBAR_PHYS
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
- gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
#endif
#if defined(CONFIG_SECURE_BOOT)
struct law_entry law;
@@ -442,13 +442,14 @@ void cpu_init_f (void)
#ifdef CONFIG_DEEP_SLEEP
/* disable the console if boot from deep sleep */
if (in_be32(&gur->scrtsr[0]) & (1 << 3))
- gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
+ flag = GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
#endif
#endif
#ifdef CONFIG_SYS_FSL_ERRATUM_A007212
fsl_erratum_a007212_workaround();
#endif
+ return flag;
}
/* Implement a dummy function for those platforms w/o SERDES */
@@ -462,10 +463,17 @@ __attribute__((weak, alias("__fsl_serdes__init"))) void fsl_serdes_init(void);
int enable_cluster_l2(void)
{
int i = 0;
- u32 cluster;
+ u32 cluster, svr = get_svr();
ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
struct ccsr_cluster_l2 __iomem *l2cache;
+ /* only the L2 of first cluster should be enabled as expected on T4080,
+ * but there is no EOC in the first cluster as HW sake, so return here
+ * to skip enabling L2 cache of the 2nd cluster.
+ */
+ if (SVR_SOC_VER(svr) == SVR_T4080)
+ return 0;
+
cluster = in_be32(&gur->tp_cluster[i].lower);
if (cluster & TP_CLUSTER_EOC)
return 0;
@@ -888,6 +896,7 @@ skip_l2:
}
#endif
+ init_used_tlb_cams();
return 0;
}
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
index 998781b706b..47b712d56b5 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c
@@ -102,11 +102,13 @@ void cpu_init_early_f(void *fdt)
for (i = 0; i < sizeof(gd_t); i++)
((char *)gd)[i] = 0;
+#ifdef CONFIG_QEMU_E500
/*
* CONFIG_SYS_CCSRBAR_PHYS below may use gd->fdt_blob on ePAPR systems,
* so we need to populate it before it accesses it.
*/
gd->fdt_blob = fdt;
+#endif
mas0 = MAS0_TLBSEL(1) | MAS0_ESEL(13);
mas1 = MAS1_VALID | MAS1_TID(0) | MAS1_TS | MAS1_TSIZE(BOOKE_PAGESZ_1M);
diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c
index 0cc21c7f680..ed80a841804 100644
--- a/arch/powerpc/cpu/mpc85xx/fdt.c
+++ b/arch/powerpc/cpu/mpc85xx/fdt.c
@@ -674,7 +674,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
#ifdef CONFIG_CPM2
do_fixup_by_compat_u32(blob, "fsl,cpm2-scc-uart",
- "current-speed", bd->bi_baudrate, 1);
+ "current-speed", gd->baudrate, 1);
do_fixup_by_compat_u32(blob, "fsl,cpm2-brg",
"clock-frequency", bd->bi_brgfreq, 1);
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c
index d516d4e4a62..3236f6a5da6 100644
--- a/arch/powerpc/cpu/mpc85xx/speed.c
+++ b/arch/powerpc/cpu/mpc85xx/speed.c
@@ -123,7 +123,8 @@ void get_sys_info(sys_info_t *sys_info)
* T4240/T4160 Rev1.0. eg. It's 12 in Rev1.0, however, for Rev2.0
* it uses 6.
*/
-#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160)
+#if defined(CONFIG_PPC_T4240) || defined(CONFIG_PPC_T4160) || \
+ defined(CONFIG_PPC_T4080)
if (SVR_MAJ(get_svr()) >= 2)
mem_pll_rat *= 2;
#endif
diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c
index 9e4c6c90788..cc45f715e84 100644
--- a/arch/powerpc/cpu/mpc85xx/spl_minimal.c
+++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c
@@ -12,7 +12,7 @@
DECLARE_GLOBAL_DATA_PTR;
-void cpu_init_f(void)
+ulong cpu_init_f(void)
{
#ifdef CONFIG_SYS_INIT_L2_ADDR
ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR;
@@ -27,6 +27,8 @@ void cpu_init_f(void)
out_be32(&l2cache->l2ctl,
(MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE));
#endif
+
+ return 0;
}
#ifndef CONFIG_SYS_FSL_TBCLK_DIV
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S
index 0e3c86a0f8f..d8c9fb6b287 100644
--- a/arch/powerpc/cpu/mpc85xx/start.S
+++ b/arch/powerpc/cpu/mpc85xx/start.S
@@ -314,7 +314,7 @@ l2_disabled:
#endif
mtspr HID0,r0
-#ifndef CONFIG_E500MC
+#if !defined(CONFIG_E500MC) && !defined(CONFIG_QEMU_E500)
li r0,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */
mfspr r3,PVR
andi. r3,r3, 0xff
@@ -1158,7 +1158,7 @@ _start_cont:
mtmsr r3
isync
- bl cpu_init_f
+ bl cpu_init_f /* return boot_flag for calling board_init_f */
bl board_init_f
isync
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_ids.c b/arch/powerpc/cpu/mpc85xx/t4240_ids.c
index f1813151346..1a3cb339874 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_ids.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_ids.c
@@ -64,11 +64,13 @@ struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
};
#endif
+#ifdef CONFIG_SYS_SRIO
struct srio_liodn_id_table srio_liodn_tbl[] = {
SET_SRIO_LIODN_BASE(1, 307),
SET_SRIO_LIODN_BASE(2, 387),
};
int srio_liodn_tbl_sz = ARRAY_SIZE(srio_liodn_tbl);
+#endif
struct liodn_id_table liodn_tbl[] = {
#ifdef CONFIG_SYS_DPAA_QBMAN
diff --git a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
index ff55e3c357c..1f99a0a8978 100644
--- a/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
+++ b/arch/powerpc/cpu/mpc85xx/t4240_serdes.c
@@ -172,7 +172,7 @@ static const struct serdes_config serdes4_cfg_tbl[] = {
{18, {PCIE3, PCIE3, PCIE3, PCIE3, AURORA, AURORA, AURORA, AURORA}},
{}
};
-#elif defined(CONFIG_PPC_T4160)
+#elif defined(CONFIG_PPC_T4160) || defined(CONFIG_PPC_T4080)
static const struct serdes_config serdes1_cfg_tbl[] = {
/* SerDes 1 */
{1, {XAUI_FM1_MAC9, XAUI_FM1_MAC9,
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
index d77a6dc62d8..f933b219449 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand.lds
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "config.h" /* CONFIG_BOARDDIR */
+#include "config.h"
#ifndef CONFIG_SYS_MONITOR_LEN
#define CONFIG_SYS_MONITOR_LEN 0x80000
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
index 844f7e94f13..b83c55388cf 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-nand_spl.lds
@@ -7,7 +7,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "config.h" /* CONFIG_BOARDDIR */
+#include "config.h"
OUTPUT_ARCH(powerpc)
SECTIONS
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
index 8453f3a3fe8..5ae7b3eedbc 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot-spl.lds
@@ -7,7 +7,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "config.h" /* CONFIG_BOARDDIR */
+#include "config.h"
OUTPUT_ARCH(powerpc)
#ifdef CONFIG_SYS_MPC85XX_NO_RESETVEC
diff --git a/arch/powerpc/cpu/mpc85xx/u-boot.lds b/arch/powerpc/cpu/mpc85xx/u-boot.lds
index 0b9086dfd09..2cf0b259525 100644
--- a/arch/powerpc/cpu/mpc85xx/u-boot.lds
+++ b/arch/powerpc/cpu/mpc85xx/u-boot.lds
@@ -4,7 +4,7 @@
* SPDX-License-Identifier: GPL-2.0+
*/
-#include "config.h" /* CONFIG_BOARDDIR */
+#include "config.h"
#ifdef CONFIG_RESET_VECTOR_ADDRESS
#define RESET_VECTOR_ADDRESS CONFIG_RESET_VECTOR_ADDRESS
diff --git a/arch/powerpc/cpu/mpc86xx/start.S b/arch/powerpc/cpu/mpc86xx/start.S
index e33672a3a01..ec5f4a756af 100644
--- a/arch/powerpc/cpu/mpc86xx/start.S
+++ b/arch/powerpc/cpu/mpc86xx/start.S
@@ -273,6 +273,7 @@ diag_done:
/* bl l2cache_enable */
/* run 1st part of board init code (from Flash) */
+ li r3, 0 /* clear boot_flag for calling board_init_f */
bl board_init_f
sync
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c
index 35795c4fbe7..15561a15331 100644
--- a/arch/powerpc/cpu/mpc8xxx/cpu.c
+++ b/arch/powerpc/cpu/mpc8xxx/cpu.c
@@ -62,10 +62,12 @@ static struct cpu_type cpu_type_list[] = {
CPU_TYPE_ENTRY(T4240, T4240, 0),
CPU_TYPE_ENTRY(T4120, T4120, 0),
CPU_TYPE_ENTRY(T4160, T4160, 0),
+ CPU_TYPE_ENTRY(T4080, T4080, 4),
CPU_TYPE_ENTRY(B4860, B4860, 0),
CPU_TYPE_ENTRY(G4860, G4860, 0),
CPU_TYPE_ENTRY(G4060, G4060, 0),
CPU_TYPE_ENTRY(B4440, B4440, 0),
+ CPU_TYPE_ENTRY(B4460, B4460, 0),
CPU_TYPE_ENTRY(G4440, G4440, 0),
CPU_TYPE_ENTRY(B4420, B4420, 0),
CPU_TYPE_ENTRY(B4220, B4220, 0),
@@ -176,7 +178,7 @@ struct cpu_type *identify_cpu(u32 ver)
/*
* Return a 32-bit mask indicating which cores are present on this SOC.
*/
-u32 cpu_mask(void)
+__weak u32 cpu_mask(void)
{
ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR;
struct cpu_type *cpu = gd->arch.cpu;
@@ -195,7 +197,7 @@ u32 cpu_mask(void)
/*
* Return the number of cores on this SOC.
*/
-int cpu_numcores(void)
+__weak int cpu_numcores(void)
{
struct cpu_type *cpu = gd->arch.cpu;
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-11 00:01:40 +0000