diff options
Diffstat (limited to 'arch/x86/cpu/slimbootloader')
| -rw-r--r-- | arch/x86/cpu/slimbootloader/Kconfig | 20 | ||||
| -rw-r--r-- | arch/x86/cpu/slimbootloader/Makefile | 5 | ||||
| -rw-r--r-- | arch/x86/cpu/slimbootloader/car.S | 14 | ||||
| -rw-r--r-- | arch/x86/cpu/slimbootloader/sdram.c | 152 | ||||
| -rw-r--r-- | arch/x86/cpu/slimbootloader/serial.c | 65 | ||||
| -rw-r--r-- | arch/x86/cpu/slimbootloader/slimbootloader.c | 61 |
6 files changed, 317 insertions, 0 deletions
diff --git a/arch/x86/cpu/slimbootloader/Kconfig b/arch/x86/cpu/slimbootloader/Kconfig new file mode 100644 index 00000000000..58a9ca01a9e --- /dev/null +++ b/arch/x86/cpu/slimbootloader/Kconfig @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 Intel Corporation <www.intel.com> + +config SYS_SLIMBOOTLOADER + bool + select USE_HOB + imply SYS_NS16550 + imply AHCI_PCI + imply SCSI + imply SCSI_AHCI + imply MMC + imply MMC_PCI + imply MMC_SDHCI + imply MMC_SDHCI_SDMA + imply USB + imply USB_EHCI_HCD + imply USB_XHCI_HCD + imply E1000 + imply X86_TSC_READ_BASE diff --git a/arch/x86/cpu/slimbootloader/Makefile b/arch/x86/cpu/slimbootloader/Makefile new file mode 100644 index 00000000000..aac9fa3db86 --- /dev/null +++ b/arch/x86/cpu/slimbootloader/Makefile @@ -0,0 +1,5 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 Intel Corporation <www.intel.com> + +obj-y += car.o slimbootloader.o sdram.o serial.o diff --git a/arch/x86/cpu/slimbootloader/car.S b/arch/x86/cpu/slimbootloader/car.S new file mode 100644 index 00000000000..6e0304333c8 --- /dev/null +++ b/arch/x86/cpu/slimbootloader/car.S @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + */ + +#include <generated/asm-offsets.h> + +.section .text + +.globl car_init +car_init: + /* Get hob pointer parameter from previous stage's stack */ + mov 0x4(%esp), %esi + jmp car_init_ret diff --git a/arch/x86/cpu/slimbootloader/sdram.c b/arch/x86/cpu/slimbootloader/sdram.c new file mode 100644 index 00000000000..75ca5273625 --- /dev/null +++ b/arch/x86/cpu/slimbootloader/sdram.c @@ -0,0 +1,152 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + */ + +#include <init.h> +#include <asm/global_data.h> +#include <linux/sizes.h> +#include <asm/e820.h> +#include <asm/arch/slimbootloader.h> + +DECLARE_GLOBAL_DATA_PTR; + +/** + * This returns a data pointer of memory map info from the guid hob. + * + * @return: A data pointer of memory map info hob + */ +static struct sbl_memory_map_info *get_memory_map_info(void) +{ + struct sbl_memory_map_info *data; + const efi_guid_t guid = SBL_MEMORY_MAP_INFO_GUID; + + if (!gd->arch.hob_list) + return NULL; + + data = hob_get_guid_hob_data(gd->arch.hob_list, NULL, &guid); + if (!data) + panic("memory map info hob not found\n"); + if (!data->count) + panic("invalid number of memory map entries\n"); + + return data; +} + +#define for_each_if(condition) if (!(condition)) {} else + +#define for_each_memory_map_entry_reversed(iter, entries) \ + for (iter = entries->count - 1; iter >= 0; iter--) \ + for_each_if(entries->entry[iter].type == E820_RAM) + +/** + * This is to give usable memory region information for u-boot relocation. + * so search usable memory region lower than 4GB. + * The memory map entries from Slim Bootloader hob are already sorted. + * + * @total_size: The memory size that u-boot occupies + * Return: : The top available memory address lower than 4GB + */ +phys_addr_t board_get_usable_ram_top(phys_size_t total_size) +{ + struct sbl_memory_map_info *data; + int i; + u64 addr_start; + u64 addr_end; + ulong ram_top; + + data = get_memory_map_info(); + + /** + * sorted memory map entries from Slim Bootloader based on physical + * start memory address, from low to high. So do reversed search to + * get highest usable, suitable size, 4KB aligned available memory + * under 4GB. + */ + ram_top = 0; + for_each_memory_map_entry_reversed(i, data) { + addr_start = data->entry[i].addr; + addr_end = addr_start + data->entry[i].size; + + if (addr_start > SZ_4G) + continue; + + if (addr_end > SZ_4G) + addr_end = SZ_4G; + + if (addr_end < total_size) + continue; + + /* to relocate u-boot at 4K aligned memory */ + addr_end = rounddown(addr_end - total_size, SZ_4K); + if (addr_end >= addr_start) { + ram_top = (ulong)addr_end + total_size; + break; + } + } + + if (!ram_top) + panic("failed to find available memory for relocation!"); + + return ram_top; +} + +/** + * The memory initialization has already been done in previous Slim Bootloader + * stage thru FSP-M. Instead, this sets the ram_size from the memory map info + * hob. + */ +int dram_init(void) +{ + struct sbl_memory_map_info *data; + int i; + u64 ram_size; + + data = get_memory_map_info(); + + /** + * sorted memory map entries from Slim Bootloader based on physical + * start memory address, from low to high. So do reversed search to + * simply get highest usable memory address as RAM size + */ + ram_size = 0; + for_each_memory_map_entry_reversed(i, data) { + /* simply use the highest usable memory address as RAM size */ + ram_size = data->entry[i].addr + data->entry[i].size; + break; + } + + if (!ram_size) + panic("failed to detect memory size"); + + gd->ram_size = ram_size; + return 0; +} + +int dram_init_banksize(void) +{ + if (!CONFIG_NR_DRAM_BANKS) + return 0; + + /* simply use a single bank to have whole size for now */ + gd->bd->bi_dram[0].start = 0; + gd->bd->bi_dram[0].size = gd->ram_size; + return 0; +} + +unsigned int install_e820_map(unsigned int max_entries, + struct e820_entry *entries) +{ + struct sbl_memory_map_info *data; + unsigned int i; + + data = get_memory_map_info(); + + for (i = 0; i < data->count; i++) { + entries[i].addr = data->entry[i].addr; + entries[i].size = data->entry[i].size; + entries[i].type = data->entry[i].type; + } + + return i; +} diff --git a/arch/x86/cpu/slimbootloader/serial.c b/arch/x86/cpu/slimbootloader/serial.c new file mode 100644 index 00000000000..4c889dad6d2 --- /dev/null +++ b/arch/x86/cpu/slimbootloader/serial.c @@ -0,0 +1,65 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + */ + +#include <dm.h> +#include <log.h> +#include <ns16550.h> +#include <serial.h> +#include <asm/arch/slimbootloader.h> +#include <asm/global_data.h> + +/** + * The serial port info hob is generated by Slim Bootloader, so eligible for + * Slim Bootloader based boards only. + */ +static int slimbootloader_serial_of_to_plat(struct udevice *dev) +{ + const efi_guid_t guid = SBL_SERIAL_PORT_INFO_GUID; + struct sbl_serial_port_info *data; + struct ns16550_plat *plat = dev_get_plat(dev); + + if (!gd->arch.hob_list) + panic("hob list not found!"); + + data = hob_get_guid_hob_data(gd->arch.hob_list, NULL, &guid); + if (!data) { + debug("failed to get serial port information\n"); + return -ENOENT; + } + debug("type:%d base=0x%08x baudrate=%d stride=%d clk=%d\n", + data->type, + data->base, + data->baud, + data->stride, + data->clk); + + plat->base = data->base; + /* ns16550 uses reg_shift, then covert stride to shift */ + plat->reg_shift = data->stride >> 1; + plat->reg_width = data->stride; + plat->clock = data->clk; + plat->fcr = UART_FCR_DEFVAL; + plat->flags = 0; + if (data->type == 1) + plat->flags |= NS16550_FLAG_IO; + + return 0; +} + +static const struct udevice_id slimbootloader_serial_ids[] = { + { .compatible = "intel,slimbootloader-uart" }, + {} +}; + +U_BOOT_DRIVER(serial_slimbootloader) = { + .name = "serial_slimbootloader", + .id = UCLASS_SERIAL, + .of_match = slimbootloader_serial_ids, + .of_to_plat = slimbootloader_serial_of_to_plat, + .plat_auto = sizeof(struct ns16550_plat), + .priv_auto = sizeof(struct ns16550), + .probe = ns16550_serial_probe, + .ops = &ns16550_serial_ops, +}; diff --git a/arch/x86/cpu/slimbootloader/slimbootloader.c b/arch/x86/cpu/slimbootloader/slimbootloader.c new file mode 100644 index 00000000000..142c9341cf8 --- /dev/null +++ b/arch/x86/cpu/slimbootloader/slimbootloader.c @@ -0,0 +1,61 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 Intel Corporation <www.intel.com> + */ + +#include <cpu_func.h> +#include <init.h> +#include <log.h> +#include <asm/arch/slimbootloader.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +/** + * This sets tsc_base and clock_rate for early_timer and tsc_timer. + * The performance info guid hob has all performance timestamp data, but + * the only tsc frequency info is used for the timer driver for now. + * + * Slim Bootloader already calibrated TSC and provides it to U-Boot. + * Therefore, U-Boot does not have to re-calibrate TSC. + * Configuring tsc_base and clock_rate here makes x86 tsc_timer driver + * bypass TSC calibration and use the provided TSC frequency. + */ +static void tsc_init(void) +{ + struct sbl_performance_info *data; + const efi_guid_t guid = SBL_PERFORMANCE_INFO_GUID; + + if (!gd->arch.hob_list) + panic("hob list not found!"); + + gd->arch.tsc_base = rdtsc(); + debug("tsc_base=0x%llx\n", gd->arch.tsc_base); + + data = hob_get_guid_hob_data(gd->arch.hob_list, NULL, &guid); + if (!data) { + debug("performance info hob not found\n"); + return; + } + + /* frequency is in KHz, so to Hz */ + gd->arch.clock_rate = data->frequency * 1000; + debug("freq=0x%lx\n", gd->arch.clock_rate); +} + +int arch_cpu_init(void) +{ + tsc_init(); + + return x86_cpu_init_f(); +} + +int checkcpu(void) +{ + return 0; +} + +int print_cpuinfo(void) +{ + return default_print_cpuinfo(); +} |