diff options
Diffstat (limited to 'arch')
50 files changed, 5552 insertions, 136 deletions
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index e8968a7182b..01ed76042f7 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -11,6 +11,9 @@ choice config VENDOR_COREBOOT bool "coreboot" +config VENDOR_EFI + bool "efi" + config VENDOR_EMULATION bool "emulation" @@ -24,6 +27,7 @@ endchoice # board-specific options below source "board/coreboot/Kconfig" +source "board/efi/Kconfig" source "board/emulation/Kconfig" source "board/google/Kconfig" source "board/intel/Kconfig" @@ -190,6 +194,7 @@ config X86_RAMTEST config HAVE_FSP bool "Add an Firmware Support Package binary" + depends on !EFI help Select this option to add an Firmware Support Package binary to the resulting U-Boot image. It is a binary blob which U-Boot uses @@ -305,6 +310,7 @@ menu "System tables" config GENERATE_PIRQ_TABLE bool "Generate a PIRQ table" + depends on !EFI default n help Generate a PIRQ routing table for this board. The PIRQ routing table @@ -315,6 +321,7 @@ config GENERATE_PIRQ_TABLE config GENERATE_SFI_TABLE bool "Generate a SFI (Simple Firmware Interface) table" + depends on !EFI help The Simple Firmware Interface (SFI) provides a lightweight method for platform firmware to pass information to the operating system @@ -329,6 +336,7 @@ config GENERATE_SFI_TABLE config GENERATE_MP_TABLE bool "Generate an MP (Multi-Processor) table" + depends on !EFI default n help Generate an MP (Multi-Processor) table for this board. The MP table @@ -379,4 +387,6 @@ config PCIE_ECAM_SIZE so a default 0x10000000 size covers all of the 256 buses which is the maximum number of PCI buses as defined by the PCI specification. +source "arch/x86/lib/efi/Kconfig" + endmenu diff --git a/arch/x86/Makefile b/arch/x86/Makefile index 36a601822a2..d104a497301 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -2,7 +2,9 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifeq ($(CONFIG_EFI_APP),) head-y := arch/x86/cpu/start.o +endif ifeq ($(CONFIG_SPL_BUILD),y) head-y += arch/x86/cpu/start16.o head-y += arch/x86/cpu/resetvec.o diff --git a/arch/x86/config.mk b/arch/x86/config.mk index 999143e9df1..d7addd87286 100644 --- a/arch/x86/config.mk +++ b/arch/x86/config.mk @@ -8,19 +8,60 @@ CONFIG_STANDALONE_LOAD_ADDR ?= 0x40000 PLATFORM_CPPFLAGS += -fno-strict-aliasing -PLATFORM_CPPFLAGS += -mregparm=3 PLATFORM_CPPFLAGS += -fomit-frame-pointer PF_CPPFLAGS_X86 := $(call cc-option, -fno-toplevel-reorder, \ $(call cc-option, -fno-unit-at-a-time)) \ $(call cc-option, -mpreferred-stack-boundary=2) + PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_X86) PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm PLATFORM_CPPFLAGS += -march=i386 -m32 PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden -PLATFORM_LDFLAGS += --emit-relocs -Bsymbolic -Bsymbolic-functions -m elf_i386 +PLATFORM_LDFLAGS += -Bsymbolic -Bsymbolic-functions -m elf_i386 -LDFLAGS_FINAL += --gc-sections -pie LDFLAGS_FINAL += --wrap=__divdi3 --wrap=__udivdi3 LDFLAGS_FINAL += --wrap=__moddi3 --wrap=__umoddi3 + +# This is used in the top-level Makefile which does not include +# PLATFORM_LDFLAGS +LDFLAGS_EFI_PAYLOAD := -Bsymbolic -Bsymbolic-functions -shared --no-undefined + +OBJCOPYFLAGS_EFI := -j .text -j .sdata -j .data -j .dynamic -j .dynsym \ + -j .rel -j .rela -j .reloc + +CFLAGS_NON_EFI := -mregparm=3 +CFLAGS_EFI := -fpic -fshort-wchar + +ifeq ($(CONFIG_EFI_STUB_64BIT),) +CFLAGS_EFI += $(call cc-option, -mno-red-zone) +EFIARCH = ia32 +EFIPAYLOAD_BFDTARGET = elf32-i386 +else +EFIARCH = x86_64 +EFIPAYLOAD_BFDTARGET = elf64-x86-64 +endif + +EFIPAYLOAD_BFDARCH = i386 + +LDSCRIPT_EFI := $(srctree)/$(CPUDIR)/efi/elf_$(EFIARCH)_efi.lds +EFISTUB := crt0-efi-$(EFIARCH).o reloc_$(EFIARCH).o +OBJCOPYFLAGS_EFI += --target=efi-app-$(EFIARCH) + +CPPFLAGS_REMOVE_crt0-efi-$(EFIARCH).o += $(CFLAGS_NON_EFI) +CPPFLAGS_crt0-efi-$(EFIARCH).o += $(CFLAGS_EFI) + +ifeq ($(CONFIG_EFI_APP),y) + +PLATFORM_CPPFLAGS += $(CFLAGS_EFI) +LDFLAGS_FINAL += -znocombreloc -shared +LDSCRIPT := $(LDSCRIPT_EFI) + +else + +PLATFORM_CPPFLAGS += $(CFLAGS_NON_EFI) +PLATFORM_LDFLAGS += --emit-relocs +LDFLAGS_FINAL += --gc-sections -pie + +endif diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 8a8e63e1d3d..e7979254dbf 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -12,8 +12,15 @@ extra-y = start.o obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o obj-y += interrupts.o cpu.o cpu_x86.o call64.o +AFLAGS_REMOVE_call32.o := -mregparm=3 \ + $(if $(CONFIG_EFI_STUB_64BIT),-march=i386 -m32) +AFLAGS_call32.o := -fpic -fshort-wchar + +extra-y += call32.o + obj-$(CONFIG_INTEL_BAYTRAIL) += baytrail/ obj-$(CONFIG_SYS_COREBOOT) += coreboot/ +obj-$(CONFIG_EFI_APP) += efi/ obj-$(CONFIG_QEMU) += qemu/ obj-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += ivybridge/ obj-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += ivybridge/ diff --git a/arch/x86/cpu/baytrail/Kconfig b/arch/x86/cpu/baytrail/Kconfig index e86cc01115b..407feb214bf 100644 --- a/arch/x86/cpu/baytrail/Kconfig +++ b/arch/x86/cpu/baytrail/Kconfig @@ -6,4 +6,4 @@ config INTEL_BAYTRAIL bool - select HAVE_FSP + select HAVE_FSP if !EFI diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c index a0117308aeb..b1faf8ca326 100644 --- a/arch/x86/cpu/baytrail/cpu.c +++ b/arch/x86/cpu/baytrail/cpu.c @@ -45,6 +45,8 @@ static void set_max_freq(void) static int cpu_x86_baytrail_probe(struct udevice *dev) { + if (!ll_boot_init()) + return 0; debug("Init BayTrail core\n"); /* diff --git a/arch/x86/cpu/baytrail/valleyview.c b/arch/x86/cpu/baytrail/valleyview.c index 9915da5bd7d..610e9d9b1d8 100644 --- a/arch/x86/cpu/baytrail/valleyview.c +++ b/arch/x86/cpu/baytrail/valleyview.c @@ -7,6 +7,7 @@ #include <common.h> #include <mmc.h> #include <pci_ids.h> +#include <asm/irq.h> #include <asm/post.h> static struct pci_device_id mmc_supported[] = { @@ -20,6 +21,7 @@ int cpu_mmc_init(bd_t *bis) ARRAY_SIZE(mmc_supported)); } +#ifndef CONFIG_EFI_APP int arch_cpu_init(void) { int ret; @@ -35,3 +37,11 @@ int arch_cpu_init(void) return 0; } + +int arch_misc_init(void) +{ + pirq_init(); + + return 0; +} +#endif diff --git a/arch/x86/cpu/call32.S b/arch/x86/cpu/call32.S new file mode 100644 index 00000000000..c517e4a89f8 --- /dev/null +++ b/arch/x86/cpu/call32.S @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2015 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/global_data.h> +#include <asm/msr-index.h> +#include <asm/processor-flags.h> + + /* + * rdi - 32-bit code segment selector + * rsi - target address + * rdx - table address (0 if none) + */ +.code64 +.globl cpu_call32 +cpu_call32: + cli + + /* Save table pointer */ + mov %edx, %ebx + + /* + * Debugging option, this outputs characters to the console UART + * mov $0x3f8,%edx + * mov $'a',%al + * out %al,(%dx) + */ + + pushf + push %rdi /* 32-bit code segment */ + lea compat(%rip), %rax + push %rax + .byte 0x48 /* REX prefix to force 64-bit far return */ + retf +.code32 +compat: + /* + * We are now in compatibility mode with a default operand size of + * 32 bits. First disable paging. + */ + movl %cr0, %eax + andl $~X86_CR0_PG, %eax + movl %eax, %cr0 + + /* Invalidate TLB */ + xorl %eax, %eax + movl %eax, %cr3 + + /* Disable Long mode in EFER (Extended Feature Enable Register) */ + movl $MSR_EFER, %ecx + rdmsr + btr $_EFER_LME, %eax + wrmsr + + /* Set up table pointer for _x86boot_start */ + mov %ebx, %ecx + + /* Jump to the required target */ + pushl %edi /* 32-bit code segment */ + pushl %esi /* 32-bit target address */ + retf diff --git a/arch/x86/cpu/call64.S b/arch/x86/cpu/call64.S index 74dd5a89dce..08dc473d6af 100644 --- a/arch/x86/cpu/call64.S +++ b/arch/x86/cpu/call64.S @@ -82,8 +82,8 @@ lret_target: .data gdt: - .word gdt_end - gdt - .long gdt + .word gdt_end - gdt - 1 + .long gdt /* Fixed up by code above */ .word 0 .quad 0x0000000000000000 /* NULL descriptor */ .quad 0x00af9a000000ffff /* __KERNEL_CS */ diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index b9134cfef37..129777c7175 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -330,13 +330,15 @@ int x86_cpu_init_f(void) const u32 em_rst = ~X86_CR0_EM; const u32 mp_ne_set = X86_CR0_MP | X86_CR0_NE; - /* initialize FPU, reset EM, set MP and NE */ - asm ("fninit\n" \ - "movl %%cr0, %%eax\n" \ - "andl %0, %%eax\n" \ - "orl %1, %%eax\n" \ - "movl %%eax, %%cr0\n" \ - : : "i" (em_rst), "i" (mp_ne_set) : "eax"); + if (ll_boot_init()) { + /* initialize FPU, reset EM, set MP and NE */ + asm ("fninit\n" \ + "movl %%cr0, %%eax\n" \ + "andl %0, %%eax\n" \ + "orl %1, %%eax\n" \ + "movl %%eax, %%cr0\n" \ + : : "i" (em_rst), "i" (mp_ne_set) : "eax"); + } /* identify CPU via cpuid and store the decoded info into gd->arch */ if (has_cpuid()) { @@ -456,7 +458,7 @@ void x86_full_reset(void) int dcache_status(void) { - return !(read_cr0() & 0x40000000); + return !(read_cr0() & X86_CR0_CD); } /* Define these functions to allow ehch-hcd to function */ @@ -712,5 +714,8 @@ __weak int x86_init_cpus(void) int cpu_init_r(void) { - return x86_init_cpus(); + if (ll_boot_init()) + return x86_init_cpus(); + + return 0; } diff --git a/arch/x86/cpu/efi/Makefile b/arch/x86/cpu/efi/Makefile new file mode 100644 index 00000000000..e09163715da --- /dev/null +++ b/arch/x86/cpu/efi/Makefile @@ -0,0 +1,8 @@ +# +# Copyright (c) 2015 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += efi.o +obj-y += sdram.o diff --git a/arch/x86/cpu/efi/efi.c b/arch/x86/cpu/efi/efi.c new file mode 100644 index 00000000000..75ba0d4844a --- /dev/null +++ b/arch/x86/cpu/efi/efi.c @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <fdtdec.h> +#include <netdev.h> + +int arch_cpu_init(void) +{ +#ifdef CONFIG_SYS_X86_TSC_TIMER + timer_set_base(rdtsc()); +#endif + + return 0; +} + +int board_early_init_f(void) +{ + return 0; +} + +int print_cpuinfo(void) +{ + return default_print_cpuinfo(); +} + +void board_final_cleanup(void) +{ +} + +int misc_init_r(void) +{ + return 0; +} + +int arch_misc_init(void) +{ + return 0; +} diff --git a/arch/x86/cpu/efi/elf_ia32_efi.lds b/arch/x86/cpu/efi/elf_ia32_efi.lds new file mode 100644 index 00000000000..cd3b0a982da --- /dev/null +++ b/arch/x86/cpu/efi/elf_ia32_efi.lds @@ -0,0 +1,94 @@ +/* + * U-Boot EFI linker script + * + * SPDX-License-Identifier: BSD-2-Clause + * + * Modified from usr/lib32/elf_ia32_efi.lds in gnu-efi + */ + +#include <config.h> + +OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") +OUTPUT_ARCH(i386) +ENTRY(_start) +SECTIONS +{ + image_base = .; + .hash : { *(.hash) } /* this MUST come first, EFI expects it */ + . = ALIGN(4096); + .text : + { + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + } + . = ALIGN(4096); + .sdata : + { + *(.got.plt) + *(.got) + *(.srodata) + *(.sdata) + *(.sbss) + *(.scommon) + } + . = ALIGN(4096); + .data : + { + *(.rodata*) + *(.data) + *(.data1) + *(.data.*) + *(.sdata) + *(.got.plt) + *(.got) + /* + * the EFI loader doesn't seem to like a .bss section, so we + * stick it all into .data: + */ + *(.sbss) + *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + + /* U-Boot lists and device tree */ + . = ALIGN(8); + *(SORT(.u_boot_list*)); + . = ALIGN(8); + *(.dtb*); + } + + . = ALIGN(4096); + .dynamic : { *(.dynamic) } + . = ALIGN(4096); + .rel : + { + *(.rel.data) + *(.rel.data.*) + *(.rel.got) + *(.rel.stab) + *(.data.rel.ro.local) + *(.data.rel.local) + *(.data.rel.ro) + *(.data.rel*) + *(.rel.u_boot_list*) + } + . = ALIGN(4096); + .reloc : /* This is the PECOFF .reloc section! */ + { + *(.reloc) + } + . = ALIGN(4096); + .dynsym : { *(.dynsym) } + . = ALIGN(4096); + .dynstr : { *(.dynstr) } + . = ALIGN(4096); + /DISCARD/ : + { + *(.rel.reloc) + *(.eh_frame) + *(.note.GNU-stack) + } + .comment 0 : { *(.comment) } +} diff --git a/arch/x86/cpu/efi/elf_x86_64_efi.lds b/arch/x86/cpu/efi/elf_x86_64_efi.lds new file mode 100644 index 00000000000..9d9f05774a9 --- /dev/null +++ b/arch/x86/cpu/efi/elf_x86_64_efi.lds @@ -0,0 +1,83 @@ +/* + * U-Boot EFI linker script + * + * SPDX-License-Identifier: BSD-2-Clause + * + * Modified from usr/lib32/elf_x86_64_efi.lds in gnu-efi + */ + +#include <config.h> + +OUTPUT_FORMAT("elf64-x86-64", "elf64-x86-64", "elf64-x86-64") +OUTPUT_ARCH(i386:x86-64) +ENTRY(_start) +SECTIONS +{ + image_base = .; + .hash : { *(.hash) } /* this MUST come first, EFI expects it */ + . = ALIGN(4096); + .eh_frame : { + *(.eh_frame) + } + + . = ALIGN(4096); + + .text : { + *(.text) + *(.text.*) + *(.gnu.linkonce.t.*) + } + + . = ALIGN(4096); + + .reloc : { + *(.reloc) + } + + . = ALIGN(4096); + + .data : { + *(.rodata*) + *(.got.plt) + *(.got) + *(.data*) + *(.sdata) + /* the EFI loader doesn't seem to like a .bss section, so we stick + * it all into .data: */ + *(.sbss) + *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + *(.rel.local) + + /* U-Boot lists and device tree */ + . = ALIGN(8); + *(SORT(.u_boot_list*)); + . = ALIGN(8); + *(.dtb*); + } + + . = ALIGN(4096); + .dynamic : { *(.dynamic) } + . = ALIGN(4096); + + .rela : { + *(.rela.data*) + *(.rela.got) + *(.rela.stab) + } + + . = ALIGN(4096); + .dynsym : { *(.dynsym) } + . = ALIGN(4096); + .dynstr : { *(.dynstr) } + . = ALIGN(4096); + .ignored.reloc : { + *(.rela.reloc) + *(.eh_frame) + *(.note.GNU-stack) + } + + .comment 0 : { *(.comment) } +} diff --git a/arch/x86/cpu/efi/sdram.c b/arch/x86/cpu/efi/sdram.c new file mode 100644 index 00000000000..51599445ab1 --- /dev/null +++ b/arch/x86/cpu/efi/sdram.c @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <efi.h> +#include <asm/u-boot-x86.h> + +DECLARE_GLOBAL_DATA_PTR; + +ulong board_get_usable_ram_top(ulong total_size) +{ + return (ulong)efi_get_ram_base() + gd->ram_size; +} + +int dram_init(void) +{ + /* gd->ram_size is set as part of EFI init */ + + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = efi_get_ram_base(); + gd->bd->bi_dram[0].size = CONFIG_EFI_RAM_SIZE; +} diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c index 853c82f5a77..9217307e4ab 100644 --- a/arch/x86/cpu/interrupts.c +++ b/arch/x86/cpu/interrupts.c @@ -19,6 +19,7 @@ #include <asm/processor-flags.h> #include <linux/compiler.h> #include <asm/msr.h> +#include <asm/processor.h> #include <asm/u-boot-x86.h> #include <asm/i8259.h> @@ -46,7 +47,7 @@ static char *exceptions[] = { "Invalid TSS", "Segment Not Present", "Stack Segment Fault", - "Gerneral Protection", + "General Protection", "Page Fault", "Reserved", "x87 FPU Floating-Point Error", @@ -165,7 +166,6 @@ struct idt_entry { struct desc_ptr { unsigned short size; unsigned long address; - unsigned short segment; } __packed; struct idt_entry idt[256] __aligned(16); @@ -202,14 +202,13 @@ int cpu_init_interrupts(void) for (i = 0; i < 256; i++) { idt[i].access = 0x8e; idt[i].res = 0; - idt[i].selector = 0x10; + idt[i].selector = X86_GDT_ENTRY_32BIT_CS * X86_GDT_ENTRY_SIZE; set_vector(i, irq_entry); irq_entry += irq_entry_size; } - idt_ptr.size = 256 * 8; + idt_ptr.size = 256 * 8 - 1; idt_ptr.address = (unsigned long) idt; - idt_ptr.segment = 0x18; load_idt(&idt_ptr); @@ -243,6 +242,11 @@ int disable_interrupts(void) int interrupt_init(void) { + /* + * When running as an EFI application we are not in control of + * interrupts and should leave them alone. + */ +#ifndef CONFIG_EFI_APP /* Just in case... */ disable_interrupts(); @@ -254,8 +258,15 @@ int interrupt_init(void) /* Initialize core interrupt and exception functionality of CPU */ cpu_init_interrupts(); - /* It is now safe to enable interrupts */ - enable_interrupts(); + /* + * It is now safe to enable interrupts. + * + * TODO(sjg@chromium.org): But we don't handle these correctly when + * booted from EFI. + */ + if (ll_boot_init()) + enable_interrupts(); +#endif return 0; } diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c index e686b28c9ca..3294a50b760 100644 --- a/arch/x86/cpu/mp_init.c +++ b/arch/x86/cpu/mp_init.c @@ -24,6 +24,8 @@ #include <dm/uclass-internal.h> #include <linux/linkage.h> +DECLARE_GLOBAL_DATA_PTR; + /* Total CPUs include BSP */ static int num_cpus; diff --git a/arch/x86/cpu/qemu/Makefile b/arch/x86/cpu/qemu/Makefile index be79723a67b..9a66b166fe1 100644 --- a/arch/x86/cpu/qemu/Makefile +++ b/arch/x86/cpu/qemu/Makefile @@ -4,5 +4,8 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y += car.o dram.o qemu.o +ifndef CONFIG_EFI_STUB +obj-y += car.o dram.o +endif +obj-y += qemu.o obj-$(CONFIG_PCI) += pci.o diff --git a/arch/x86/cpu/qemu/qemu.c b/arch/x86/cpu/qemu/qemu.c index 930d2b6c9d1..64634a9229a 100644 --- a/arch/x86/cpu/qemu/qemu.c +++ b/arch/x86/cpu/qemu/qemu.c @@ -25,11 +25,13 @@ int arch_cpu_init(void) return 0; } +#ifndef CONFIG_EFI_STUB int print_cpuinfo(void) { post_code(POST_CPU_INFO); return default_print_cpuinfo(); } +#endif void reset_cpu(ulong addr) { diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S index 00e585e19bf..e5c1733e594 100644 --- a/arch/x86/cpu/start.S +++ b/arch/x86/cpu/start.S @@ -25,11 +25,11 @@ .globl _x86boot_start _x86boot_start: /* - * This is the fail safe 32-bit bootstrap entry point. The - * following code is not executed from a cold-reset (actually, a - * lot of it is, but from real-mode after cold reset. It is - * repeated here to put the board into a state as close to cold - * reset as necessary) + * This is the fail-safe 32-bit bootstrap entry point. + * + * This code is used when booting from another boot loader like + * coreboot or EFI. So we repeat some of the same init found in + * start16. */ cli cld @@ -41,19 +41,34 @@ _x86boot_start: wbinvd /* Tell 32-bit code it is being entered from an in-RAM copy */ - movw $GD_FLG_WARM_BOOT, %bx + movl $GD_FLG_WARM_BOOT, %ebx + + /* + * Zero the BIST (Built-In Self Test) value since we don't have it. + * It must be 0 or the previous loader would have reported an error. + */ + movl $0, %ebp + jmp 1f + + /* Add a way for tools to discover the _start entry point */ + .align 4 + .long 0x12345678 _start: /* - * This is the 32-bit cold-reset entry point. Initialize %bx to 0 - * in case we're preceeded by some sort of boot stub. + * This is the 32-bit cold-reset entry point, coming from start16. + * Set %ebx to GD_FLG_COLD_BOOT to indicate this. */ - movw $GD_FLG_COLD_BOOT, %bx -1: + movl $GD_FLG_COLD_BOOT, %ebx + /* Save BIST */ movl %eax, %ebp +1: + + /* Save table pointer */ + movl %ecx, %esi - /* Load the segement registes to match the gdt loaded in start16.S */ + /* Load the segement registers to match the GDT loaded in start16.S */ movl $(X86_GDT_ENTRY_32BIT_DS * X86_GDT_ENTRY_SIZE), %eax movw %ax, %fs movw %ax, %ds @@ -64,7 +79,11 @@ _start: /* Clear the interrupt vectors */ lidt blank_idt_ptr - /* Early platform init (setup gpio, etc ) */ + /* + * Critical early platform init - generally not used, we prefer init + * to happen later when we have a console, in case something goes + * wrong. + */ jmp early_board_init .globl early_board_init_ret early_board_init_ret: @@ -79,7 +98,7 @@ car_init_ret: * We now have CONFIG_SYS_CAR_SIZE bytes of Cache-As-RAM (or SRAM, * or fully initialised SDRAM - we really don't care which) * starting at CONFIG_SYS_CAR_ADDR to be used as a temporary stack - * and early malloc area. The MRC requires some space at the top. + * and early malloc() area. The MRC requires some space at the top. * * Stack grows down from top of CAR. We have: * @@ -97,7 +116,7 @@ car_init_ret: #endif #else /* - * When we get here after car_init, esp points to a temporary stack + * When we get here after car_init(), esp points to a temporary stack * and esi holds the HOB list address returned by the FSP. */ #endif @@ -125,7 +144,13 @@ car_init_ret: movl %esi, (%edx) skip_hob: +#else + /* Store table pointer */ + movl %esp, %edx + addl $GD_TABLE, %edx + movl %esi, (%edx) #endif + /* Setup first parameter to setup_gdt, pointer to global_data */ movl %esp, %eax @@ -137,17 +162,18 @@ skip_hob: movl %esp, %ecx #if defined(CONFIG_SYS_MALLOC_F_LEN) + /* Set up the pre-relocation malloc pool */ subl $CONFIG_SYS_MALLOC_F_LEN, %esp movl %eax, %edx addl $GD_MALLOC_BASE, %edx movl %esp, (%edx) #endif - /* Store BIST */ + /* Store BIST into global_data */ movl %eax, %edx addl $GD_BIST, %edx movl %ebp, (%edx) - /* Set second parameter to setup_gdt */ + /* Set second parameter to setup_gdt() */ movl %ecx, %edx /* Setup global descriptor table so gd->xyz works */ @@ -157,7 +183,7 @@ skip_hob: post_code(POST_START_DONE) xorl %eax, %eax - /* Enter, U-boot! */ + /* Enter, U-Boot! */ call board_init_f /* indicate (lack of) progress */ @@ -184,13 +210,13 @@ board_init_f_r_trampoline: /* Align global data to 16-byte boundary */ andl $0xfffffff0, %esp - /* Setup first parameter to memcpy (and setup_gdt) */ + /* Setup first parameter to memcpy() and setup_gdt() */ movl %esp, %eax - /* Setup second parameter to memcpy */ + /* Setup second parameter to memcpy() */ fs movl 0, %edx - /* Set third parameter to memcpy */ + /* Set third parameter to memcpy() */ movl $GENERATED_GBL_DATA_SIZE, %ecx /* Copy global data from CAR to SDRAM stack */ @@ -202,7 +228,7 @@ board_init_f_r_trampoline: /* Align global descriptor table to 16-byte boundary */ andl $0xfffffff0, %esp - /* Set second parameter to setup_gdt */ + /* Set second parameter to setup_gdt() */ movl %esp, %edx /* Setup global descriptor table so gd->xyz works */ @@ -216,7 +242,7 @@ board_init_f_r_trampoline: call car_uninit 1: - /* Re-enter U-Boot by calling board_init_f_r */ + /* Re-enter U-Boot by calling board_init_f_r() */ call board_init_f_r die: @@ -230,9 +256,10 @@ blank_idt_ptr: .p2align 2 /* force 4-byte alignment */ + /* Add a multiboot header so U-Boot can be loaded by GRUB2 */ multiboot_header: /* magic */ - .long 0x1BADB002 + .long 0x1badb002 /* flags */ .long (1 << 16) /* checksum */ diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index f86514ce839..71595c79fb7 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -1,6 +1,8 @@ -dtb-y += chromebook_link.dtb \ +dtb-y += bayleybay.dtb \ + chromebook_link.dtb \ chromebox_panther.dtb \ crownbay.dtb \ + efi.dtb \ galileo.dtb \ minnowmax.dtb \ qemu-x86_i440fx.dtb \ diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts new file mode 100644 index 00000000000..9f8fa70f967 --- /dev/null +++ b/arch/x86/dts/bayleybay.dts @@ -0,0 +1,197 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +#include <dt-bindings/gpio/x86-gpio.h> +#include <dt-bindings/interrupt-router/intel-irq.h> + +/include/ "skeleton.dtsi" +/include/ "serial.dtsi" +/include/ "rtc.dtsi" + +/ { + model = "Intel Bayley Bay"; + compatible = "intel,bayleybay", "intel,baytrail"; + + aliases { + serial0 = &serial; + spi0 = "/spi"; + }; + + config { + silent_console = <0>; + }; + + chosen { + stdout-path = "/serial"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu@0 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <0>; + intel,apic-id = <0>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <1>; + intel,apic-id = <2>; + }; + + cpu@2 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <2>; + intel,apic-id = <4>; + }; + + cpu@3 { + device_type = "cpu"; + compatible = "intel,baytrail-cpu"; + reg = <3>; + intel,apic-id = <6>; + }; + }; + + spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich-spi"; + spi-flash@0 { + reg = <0>; + compatible = "winbond,w25q64dw", "spi-flash"; + memory-map = <0xff800000 0x00800000>; + }; + }; + + gpioa { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0 0x20>; + bank-name = "A"; + }; + + gpiob { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x20 0x20>; + bank-name = "B"; + }; + + gpioc { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x40 0x20>; + bank-name = "C"; + }; + + gpiod { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x60 0x20>; + bank-name = "D"; + }; + + gpioe { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x80 0x20>; + bank-name = "E"; + }; + + gpiof { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0xA0 0x20>; + bank-name = "F"; + }; + + pci { + compatible = "pci-x86"; + #address-cells = <3>; + #size-cells = <2>; + u-boot,dm-pre-reloc; + ranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000 + 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000 + 0x01000000 0x0 0x2000 0x2000 0 0xe000>; + + irq-router@1f,0 { + reg = <0x0000f800 0 0 0 0>; + compatible = "intel,irq-router"; + intel,pirq-config = "ibase"; + intel,ibase-offset = <0x50>; + intel,pirq-link = <8 8>; + intel,pirq-mask = <0xdee0>; + intel,pirq-routing = < + /* BayTrail PCI devices */ + PCI_BDF(0, 2, 0) INTA PIRQA + PCI_BDF(0, 3, 0) INTA PIRQA + PCI_BDF(0, 16, 0) INTA PIRQA + PCI_BDF(0, 17, 0) INTA PIRQA + PCI_BDF(0, 18, 0) INTA PIRQA + PCI_BDF(0, 19, 0) INTA PIRQA + PCI_BDF(0, 20, 0) INTA PIRQA + PCI_BDF(0, 21, 0) INTA PIRQA + PCI_BDF(0, 22, 0) INTA PIRQA + PCI_BDF(0, 23, 0) INTA PIRQA + PCI_BDF(0, 24, 0) INTA PIRQA + PCI_BDF(0, 24, 1) INTC PIRQC + PCI_BDF(0, 24, 2) INTD PIRQD + PCI_BDF(0, 24, 3) INTB PIRQB + PCI_BDF(0, 24, 4) INTA PIRQA + PCI_BDF(0, 24, 5) INTC PIRQC + PCI_BDF(0, 24, 6) INTD PIRQD + PCI_BDF(0, 24, 7) INTB PIRQB + PCI_BDF(0, 26, 0) INTA PIRQA + PCI_BDF(0, 27, 0) INTA PIRQA + PCI_BDF(0, 28, 0) INTA PIRQA + PCI_BDF(0, 28, 1) INTB PIRQB + PCI_BDF(0, 28, 2) INTC PIRQC + PCI_BDF(0, 28, 3) INTD PIRQD + PCI_BDF(0, 29, 0) INTA PIRQA + PCI_BDF(0, 30, 0) INTA PIRQA + PCI_BDF(0, 30, 1) INTD PIRQD + PCI_BDF(0, 30, 2) INTB PIRQB + PCI_BDF(0, 30, 3) INTC PIRQC + PCI_BDF(0, 30, 4) INTD PIRQD + PCI_BDF(0, 30, 5) INTB PIRQB + PCI_BDF(0, 31, 3) INTB PIRQB + + /* PCIe root ports downstream interrupts */ + PCI_BDF(1, 0, 0) INTA PIRQA + PCI_BDF(1, 0, 0) INTB PIRQB + PCI_BDF(1, 0, 0) INTC PIRQC + PCI_BDF(1, 0, 0) INTD PIRQD + PCI_BDF(2, 0, 0) INTA PIRQB + PCI_BDF(2, 0, 0) INTB PIRQC + PCI_BDF(2, 0, 0) INTC PIRQD + PCI_BDF(2, 0, 0) INTD PIRQA + PCI_BDF(3, 0, 0) INTA PIRQC + PCI_BDF(3, 0, 0) INTB PIRQD + PCI_BDF(3, 0, 0) INTC PIRQA + PCI_BDF(3, 0, 0) INTD PIRQB + PCI_BDF(4, 0, 0) INTA PIRQD + PCI_BDF(4, 0, 0) INTB PIRQA + PCI_BDF(4, 0, 0) INTC PIRQB + PCI_BDF(4, 0, 0) INTD PIRQC + >; + }; + }; + + microcode { + update@0 { +#include "microcode/m0230671117.dtsi" + }; + }; + +}; diff --git a/arch/x86/dts/efi.dts b/arch/x86/dts/efi.dts new file mode 100644 index 00000000000..1f50428aa2e --- /dev/null +++ b/arch/x86/dts/efi.dts @@ -0,0 +1,22 @@ +/* + * Copyright (c) 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/dts-v1/; + +/include/ "skeleton.dtsi" + +/ { + model = "EFI"; + compatible = "efi,app"; + + chosen { + stdout-path = &serial; + }; + + serial: serial { + compatible = "efi,uart"; + }; +}; diff --git a/arch/x86/dts/microcode/m0230671117.dtsi b/arch/x86/dts/microcode/m0230671117.dtsi new file mode 100644 index 00000000000..439e84ae3d6 --- /dev/null +++ b/arch/x86/dts/microcode/m0230671117.dtsi @@ -0,0 +1,4244 @@ +/* + * --- + * This is a device tree fragment. Use #include to add these properties to a + * node. + * + * Date: + */ + +compatible = "intel,microcode"; +intel,header-version = <1>; +intel,update-revision = <0x117>; +intel,date-code = <0x4102013>; +intel,processor-signature = <0x30671>; +intel,checksum = <0x2abfd907>; +intel,loader-revision = <1>; +intel,processor-flags = <0x2>; + +/* The first 48-bytes are the public header which repeats the above data */ +data = < + 0x01000000 0x17010000 0x13201004 0x71060300 + 0x07d9bf2a 0x01000000 0x02000000 0xd0070100 + 0x00080100 0x00000000 0x00000000 0x00000000 + 0x00000000 0xa1000000 0x01000200 0x17010000 + 0x00000000 0x00000000 0x09041320 0x41410000 + 0x01000000 0x71060300 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000000 0xf4410000 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000 + 0x66cf0793 0x27bf71f6 0x80b10062 0x8ecb5c66 + 0x158f5c1e 0xea343126 0xc3f7f3a2 0xe4863e94 + 0xdb666815 0x5a17bfc4 0x4fca009d 0x099ae8b3 + 0x198e2c7d 0x7c665bbf 0xc07a1a7a 0x7dbcee26 + 0x867296b2 0xc885b6ce 0xe602baff 0x68544b14 + 0xc928c400 0x3add156d 0x531946f9 0x92a03216 + 0xda352322 0xd967ee1f 0x3c5170a7 0xf6de834e + 0x5a2ed8b3 0x9fb8f050 0x450de17f 0xfd5ef070 + 0x4954575f 0xa3a071ab 0xb56e2afb 0xe2b48302 + 0x6655a958 0x57c9a438 0x1b2f688a 0x09309bc4 + 0x0be95612 0x529c1633 0xc48515d9 0x29eb78df + 0x9933409f 0xda58dea9 0x58c805fd 0xbc110f5a + 0x40780ec0 0x6ad59bb3 0xc7387fb8 0x591c1490 + 0xf9335932 0x32130e0b 0xef4b3c96 0xacd903f2 + 0x5b362539 0xe7f85529 0xcb17c41f 0xe7e440d8 + 0xfaf7e925 0x969b76fb 0x5edab8c7 0xf00012e8 + 0x121c2971 0xe5b18959 0xadfd07c0 0x1f09c9d7 + 0x9781006a 0x39550073 0x6c438b6d 0x436f60bc + 0x11000000 0xe652e618 0x13c8666a 0x3b61e025 + 0xa07f9120 0x29d9f7bb 0x710dcff6 0x1e3c82e1 + 0x5757a634 0xafdc75ca 0xebd0b2cf 0x61f3ef48 + 0x1bc78714 0x1c5217e5 0x62cde08c 0x4b9de061 + 0x99425c27 0x3b8bbbcb 0xad68d252 0xdf3f7a9b + 0x4f20f8d4 0x295b2c1b 0xff10528f 0x8cc5052e + 0xdc9a1a30 0xbc2c6da4 0xc73c4031 0x767f5d70 + 0x7105731c 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0xa6496a45 0xdb24d8a8 0x3aa866c9 0x7d5b2401 + 0x73be59a9 0x980cc211 0x8478f5a2 0x68d84900 + 0xa96baa87 0x911b2970 0xaf373e15 0x81bc2e71 + 0x7c94ca27 0xc33d4795 0x73ba7ae9 0x29e6e73d + 0xfadc0054 0x07f98e87 0x162ede5c 0x59c3b6f2 + 0x683337dc 0x87dd64f5 0xf7856bb4 0xb6ce50dd + 0xa3c86db9 0x6100827b 0x7cc4de14 0x02c3f93e + 0x2f977a39 0xb043c1c0 0xb113decb 0xe4c554a6 + 0x7082d8ef 0x8ae434f7 0x3a14bc50 0x53aabb43 + 0xdf5ef188 0x1a2dd4d5 0xf5ac5687 0x11e4291b + 0x62e9883a 0xb3d923cd 0xc12858b1 0x710a5d69 + 0x7d70f45e 0xe18e9faa 0xc1603517 0x3ccdc05d + 0xc01e5418 0xb9747285 0x76c04eb9 0x2d5db847 + 0xa116adca 0x9ecaf1fe 0x0982d9e2 0xcb0f10de + 0x077d48ae 0xdbd7e114 0xb28cb0d8 0x0374ac9c + 0x3021be55 0xfb970aed 0x6e48792b 0x93aef002 + 0x072acf1b 0xae4e8c24 0xd4763e81 0x9e2c57b5 + 0xcdd91a44 0x459025bc 0x60b6fe21 0xb0c5e214 + 0x9fc40de3 0x58540754 0x323b25fd 0x60308baf + 0xaab5ffbd 0x4c6cea8c 0x56b1d95a 0x723fd96d + 0x8bd9aac3 0x436c3228 0x7b16f7e3 0xe2d50c54 + 0x61ab1d0d 0x2daf7b32 0xab3f19ae 0x94593302 + 0x6284d706 0x0846c148 0x72a30aad 0xad6091ae + 0x4ab48110 0x41946288 0xb5fbfc87 0x810e9d10 + 0x14d59f71 0x780a9242 0x13606651 0x7e3a608a + 0x7e66968b 0x1a273e42 0x37088eaf 0x06cf0ae3 + 0x474abea0 0xc3687382 0x4e9d0fc1 0xd9a60259 + 0x2799a0ca 0x7564ef87 0xeff4705a 0xa4f54561 + 0x33f80a5d 0xb5a49d64 0x53e38a7e 0x46b69062 + 0xf522bb74 0x9e3ae357 0xf589864e 0x2df83ddd + 0x0b53fa6d 0xafe7755f 0xd0a66571 0x630ac3d3 + 0x3e6317f6 0x69520a4e 0x117869ef 0x3d2881a1 + 0xfb05a373 0xcf3d6bf3 0x2d616ed8 0x597ed224 + 0x458f5db4 0x4e6833d2 0x7e673934 0x37cc067d + 0x3cd649a5 0x256fa294 0x4d4f9f5f 0xa35b0be5 + 0x881edd0e 0x34d280e7 0xb38a8892 0xb1c34db4 + 0x67742084 0x1cae3bc9 0xf7a84084 0xb5a54833 + 0x9e2c029b 0x5821a0d8 0x70703e03 0x149e48d4 + 0x338c1f36 0x21150844 0xe2ad4015 0x39b91fc9 + 0xb4399f34 0x88785b31 0x9ff09389 0x79219aa7 + 0xfbebe952 0x37784809 0xf2094ff7 0x4c06fb61 + 0x56692d3d 0x31679fe2 0xe468128f 0xb24053bf + 0x358eb887 0x98f817ad 0x7ae65ea3 0x438704d2 + 0x43f6aa4e 0x2d6fb5aa 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0xecc8cef7 0x8f8a43e2 0x204a30bf + 0x94339595 0xa61610d4 0x13fad76f 0xded761d3 + 0x16fbb3e1 0xec00076f 0x6c674e6f 0x203e4734 + 0x1b81be27 0xee803a89 0x2e054bdd 0x0ff3f125 + 0xa48e650d 0x7896b400 0xefe1a527 0x5b0deaea + 0x9eca85f3 0x6f2c121b 0x51d63bfb 0xf1384bd1 + 0x1c3fc01b 0xf72259b4 0xdb339714 0xa331d495 + 0x15bd7c51 0xab693bf3 0xde0f7743 0xd3dd3acf + 0x8c755ac1 0x67ebc6c0 0xaa3404d1 0x006a6b45 + 0x9e3d255d 0x20c4b946 0x3fd24a1f 0x41ed7231 + 0x59f2bb05 0x3ad0fb24 0xb6f610a8 0x9a254d64 + 0x0d5094b7 0xe01beae3 0x98a56a78 0x26c2da3b + 0xba4fd221 0xbe0f8666 0x61146fe5 0x1278a21e + 0x6dbcfa62 0xb46f9dc4 0x5e21fc7d 0x58c634f0 + >; diff --git a/arch/x86/dts/qemu-x86_i440fx.dts b/arch/x86/dts/qemu-x86_i440fx.dts index c26c71bcf73..fc74cd0f014 100644 --- a/arch/x86/dts/qemu-x86_i440fx.dts +++ b/arch/x86/dts/qemu-x86_i440fx.dts @@ -34,6 +34,13 @@ reg = <0>; intel,apic-id = <0>; }; + + cpu@1 { + device_type = "cpu"; + compatible = "cpu-x86"; + reg = <1>; + intel,apic-id = <1>; + }; }; pci { diff --git a/arch/x86/dts/qemu-x86_q35.dts b/arch/x86/dts/qemu-x86_q35.dts index 2e785fa4bf5..7f16971783b 100644 --- a/arch/x86/dts/qemu-x86_q35.dts +++ b/arch/x86/dts/qemu-x86_q35.dts @@ -45,6 +45,13 @@ reg = <0>; intel,apic-id = <0>; }; + + cpu@1 { + device_type = "cpu"; + compatible = "cpu-x86"; + reg = <1>; + intel,apic-id = <1>; + }; }; pci { diff --git a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h index 82862f626d3..eb0d5062164 100644 --- a/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h +++ b/arch/x86/include/asm/arch-baytrail/fsp/fsp_vpd.h @@ -75,7 +75,8 @@ struct __packed upd_region { uint8_t emmc45_ddr50_enabled; /* Offset 0x0051 */ uint8_t emmc45_hs200_enabled; /* Offset 0x0052 */ uint8_t emmc45_retune_timer_value; /* Offset 0x0053 */ - uint8_t unused_upd_space1[156]; /* Offset 0x0054 */ + uint8_t enable_igd; /* Offset 0x0054 */ + uint8_t unused_upd_space1[155]; /* Offset 0x0055 */ struct memory_down_data memory_params; /* Offset 0x00f0 */ uint16_t terminator; /* Offset 0x0100 */ }; diff --git a/arch/x86/include/asm/arch-efi/gpio.h b/arch/x86/include/asm/arch-efi/gpio.h new file mode 100644 index 00000000000..f044f075377 --- /dev/null +++ b/arch/x86/include/asm/arch-efi/gpio.h @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2015 Google, Inc. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _X86_ARCH_GPIO_H_ +#define _X86_ARCH_GPIO_H_ + +#endif /* _X86_ARCH_GPIO_H_ */ diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index 08284ee2953..c70183cceff 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -27,6 +27,24 @@ enum { X86_VENDOR_UNKNOWN = 0xff }; +/* Global descriptor table (GDT) bits */ +enum { + GDT_4KB = 1ULL << 55, + GDT_32BIT = 1ULL << 54, + GDT_LONG = 1ULL << 53, + GDT_PRESENT = 1ULL << 47, + GDT_NOTSYS = 1ULL << 44, + GDT_CODE = 1ULL << 43, + GDT_LIMIT_LOW_SHIFT = 0, + GDT_LIMIT_LOW_MASK = 0xffff, + GDT_LIMIT_HIGH_SHIFT = 48, + GDT_LIMIT_HIGH_MASK = 0xf, + GDT_BASE_LOW_SHIFT = 16, + GDT_BASE_LOW_MASK = 0xffff, + GDT_BASE_HIGH_SHIFT = 56, + GDT_BASE_HIGH_MASK = 0xf, +}; + struct cpuid_result { uint32_t eax; uint32_t ebx; @@ -212,6 +230,15 @@ char *cpu_get_name(char *name); void cpu_call64(ulong pgtable, ulong setup_base, ulong target); /** + * cpu_call32() - Jump to a 32-bit entry point + * + * @code_seg32: 32-bit code segment to use (GDT offset, e.g. 0x20) + * @target: Pointer to the start of the 32-bit U-Boot image/entry point + * @table: Pointer to start of info table to pass to U-Boot + */ +void cpu_call32(ulong code_seg32, ulong target, ulong table); + +/** * cpu_jump_to_64bit() - Jump to a 64-bit Linux kernel * * The kernel is uncompressed and the 64-bit entry point is expected to be diff --git a/arch/x86/include/asm/elf.h b/arch/x86/include/asm/elf.h new file mode 100644 index 00000000000..3bdcdfe70bd --- /dev/null +++ b/arch/x86/include/asm/elf.h @@ -0,0 +1,46 @@ +/* + * Brought in from Linux 4.1, removed things not useful to U-Boot. + * The definitions perhaps came from the GNU Library which is GPL. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_X86_ELF_H +#define _ASM_X86_ELF_H + +/* ELF register definitions */ +#define R_386_NONE 0 +#define R_386_32 1 +#define R_386_PC32 2 +#define R_386_GOT32 3 +#define R_386_PLT32 4 +#define R_386_COPY 5 +#define R_386_GLOB_DAT 6 +#define R_386_JMP_SLOT 7 +#define R_386_RELATIVE 8 +#define R_386_GOTOFF 9 +#define R_386_GOTPC 10 +#define R_386_NUM 11 + +/* x86-64 relocation types */ +#define R_X86_64_NONE 0 /* No reloc */ +#define R_X86_64_64 1 /* Direct 64 bit */ +#define R_X86_64_PC32 2 /* PC relative 32 bit signed */ +#define R_X86_64_GOT32 3 /* 32 bit GOT entry */ +#define R_X86_64_PLT32 4 /* 32 bit PLT address */ +#define R_X86_64_COPY 5 /* Copy symbol at runtime */ +#define R_X86_64_GLOB_DAT 6 /* Create GOT entry */ +#define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */ +#define R_X86_64_RELATIVE 8 /* Adjust by program base */ +/* 32 bit signed pc relative offset to GOT */ +#define R_X86_64_GOTPCREL 9 +#define R_X86_64_32 10 /* Direct 32 bit zero extended */ +#define R_X86_64_32S 11 /* Direct 32 bit sign extended */ +#define R_X86_64_16 12 /* Direct 16 bit zero extended */ +#define R_X86_64_PC16 13 /* 16 bit sign extended pc relative */ +#define R_X86_64_8 14 /* Direct 8 bit sign extended */ +#define R_X86_64_PC8 15 /* 8 bit sign extended pc relative */ + +#define R_X86_64_NUM 16 + +#endif diff --git a/arch/x86/include/asm/fsp/fsp_hob.h b/arch/x86/include/asm/fsp/fsp_hob.h index 6cca7f56541..3fb3546e27f 100644 --- a/arch/x86/include/asm/fsp/fsp_hob.h +++ b/arch/x86/include/asm/fsp/fsp_hob.h @@ -8,6 +8,8 @@ #ifndef __FSP_HOB_H__ #define __FSP_HOB_H__ +#include <efi.h> + /* Type of HOB Header */ #define HOB_TYPE_MEM_ALLOC 0x0002 #define HOB_TYPE_RES_DESC 0x0003 @@ -25,63 +27,6 @@ struct hob_header { u32 reserved; /* always zero */ }; -/* Enumeration of memory types introduced in UEFI */ -enum efi_mem_type { - EFI_RESERVED_MEMORY_TYPE, - /* - * The code portions of a loaded application. - * (Note that UEFI OS loaders are UEFI applications.) - */ - EFI_LOADER_CODE, - /* - * The data portions of a loaded application and - * the default data allocation type used by an application - * to allocate pool memory. - */ - EFI_LOADER_DATA, - /* The code portions of a loaded Boot Services Driver */ - EFI_BOOT_SERVICES_CODE, - /* - * The data portions of a loaded Boot Serves Driver and - * the default data allocation type used by a Boot Services - * Driver to allocate pool memory. - */ - EFI_BOOT_SERVICES_DATA, - /* The code portions of a loaded Runtime Services Driver */ - EFI_RUNTIME_SERVICES_CODE, - /* - * The data portions of a loaded Runtime Services Driver and - * the default data allocation type used by a Runtime Services - * Driver to allocate pool memory. - */ - EFI_RUNTIME_SERVICES_DATA, - /* Free (unallocated) memory */ - EFI_CONVENTIONAL_MEMORY, - /* Memory in which errors have been detected */ - EFI_UNUSABLE_MEMORY, - /* Memory that holds the ACPI tables */ - EFI_ACPI_RECLAIM_MEMORY, - /* Address space reserved for use by the firmware */ - EFI_ACPI_MEMORY_NVS, - /* - * Used by system firmware to request that a memory-mapped IO region - * be mapped by the OS to a virtual address so it can be accessed by - * EFI runtime services. - */ - EFI_MMAP_IO, - /* - * System memory-mapped IO region that is used to translate - * memory cycles to IO cycles by the processor. - */ - EFI_MMAP_IO_PORT, - /* - * Address space reserved by the firmware for code that is - * part of the processor. - */ - EFI_PAL_CODE, - EFI_MAX_MEMORY_TYPE -}; - /* * Describes all memory ranges used during the HOB producer phase that * exist outside the HOB list. This HOB type describes how memory is used, diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 4d9eac676ee..f7e3889df07 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -69,6 +69,7 @@ struct arch_global_data { char *mrc_output; unsigned int mrc_output_len; void *gdt; /* Global descriptor table */ + ulong table; /* Table pointer from previous loader */ }; #endif @@ -76,6 +77,12 @@ struct arch_global_data { #include <asm-generic/global_data.h> #ifndef __ASSEMBLY__ +# ifdef CONFIG_EFI_APP + +#define gd global_data_ptr + +#define DECLARE_GLOBAL_DATA_PTR extern struct global_data *global_data_ptr +# else static inline __attribute__((no_instrument_function)) gd_t *get_fs_gd_ptr(void) { gd_t *gd_ptr; @@ -87,14 +94,15 @@ static inline __attribute__((no_instrument_function)) gd_t *get_fs_gd_ptr(void) #define gd get_fs_gd_ptr() +#define DECLARE_GLOBAL_DATA_PTR +# endif + #endif /* * Our private Global Data Flags */ -#define GD_FLG_COLD_BOOT 0x00100 /* Cold Boot */ -#define GD_FLG_WARM_BOOT 0x00200 /* Warm Boot */ - -#define DECLARE_GLOBAL_DATA_PTR +#define GD_FLG_COLD_BOOT 0x10000 /* Cold Boot */ +#define GD_FLG_WARM_BOOT 0x20000 /* Warm Boot */ #endif /* __ASM_GBL_DATA_H */ diff --git a/arch/x86/include/asm/relocate.h b/arch/x86/include/asm/relocate.h index eb186b9fb89..cff3abc23a5 100644 --- a/arch/x86/include/asm/relocate.h +++ b/arch/x86/include/asm/relocate.h @@ -11,7 +11,6 @@ #include <common.h> int copy_uboot_to_ram(void); -int copy_fdt_to_ram(void); int clear_bss(void); int do_elf_reloc_fixups(void); diff --git a/arch/x86/include/asm/types.h b/arch/x86/include/asm/types.h index e272c90eb7f..766617f9aa3 100644 --- a/arch/x86/include/asm/types.h +++ b/arch/x86/include/asm/types.h @@ -44,8 +44,11 @@ typedef __INT64_TYPE__ s64; typedef __UINT64_TYPE__ u64; #endif +#ifdef CONFIG_EFI_STUB_64BIT +#define BITS_PER_LONG 64 +#else #define BITS_PER_LONG 32 - +#endif /* Dma addresses are 32-bits wide. */ typedef u32 dma_addr_t; diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 43489fdc1f8..dcfe9ee85c5 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -11,6 +11,7 @@ obj-y += bios_interrupts.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-y += cmd_boot.o obj-$(CONFIG_HAVE_FSP) += cmd_hob.o +obj-$(CONFIG_EFI) += efi/ obj-y += gcc.o obj-y += init_helpers.o obj-y += interrupts.o @@ -34,7 +35,7 @@ obj-$(CONFIG_SYS_X86_TSC_TIMER) += tsc_timer.o obj-$(CONFIG_CMD_ZBOOT) += zimage.o obj-$(CONFIG_HAVE_FSP) += fsp/ -extra-$(CONFIG_USE_PRIVATE_LIBGCC) := lib.a +extra-$(CONFIG_USE_PRIVATE_LIBGCC) += lib.a NORMAL_LIBGCC = $(shell $(CC) $(PLATFORM_CPPFLAGS) -print-libgcc-file-name) OBJCOPYFLAGS := --prefix-symbols=__normal_ diff --git a/arch/x86/lib/asm-offsets.c b/arch/x86/lib/asm-offsets.c index 70ccf1b0b04..9da04dd8759 100644 --- a/arch/x86/lib/asm-offsets.c +++ b/arch/x86/lib/asm-offsets.c @@ -21,5 +21,6 @@ int main(void) #ifdef CONFIG_HAVE_FSP DEFINE(GD_HOB_LIST, offsetof(gd_t, arch.hob_list)); #endif + DEFINE(GD_TABLE, offsetof(gd_t, arch.table)); return 0; } diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c index 86030cf52aa..f441c84df56 100644 --- a/arch/x86/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -22,6 +22,8 @@ #include <asm/arch/timestamp.h> #endif +DECLARE_GLOBAL_DATA_PTR; + #define COMMAND_LINE_OFFSET 0x9000 /* @@ -162,7 +164,11 @@ int boot_linux_kernel(ulong setup_base, ulong load_address, bool image_64bit) * the data segments are 0x18, 4GB flat, and read/write. * U-boot is setting them up that way for itself in * arch/i386/cpu/cpu.c. + * + * Note that we cannot currently boot a kernel while running as + * an EFI application. Please use the payload option for that. */ +#ifndef CONFIG_EFI_APP __asm__ __volatile__ ( "movl $0, %%ebp\n" "cli\n" @@ -171,6 +177,7 @@ int boot_linux_kernel(ulong setup_base, ulong load_address, bool image_64bit) [boot_params] "S"(setup_base), "b"(0), "D"(0) ); +#endif } /* We can't get to here */ diff --git a/arch/x86/lib/efi/Kconfig b/arch/x86/lib/efi/Kconfig new file mode 100644 index 00000000000..e0975d34d36 --- /dev/null +++ b/arch/x86/lib/efi/Kconfig @@ -0,0 +1,11 @@ +if EFI + +config SYS_CAR_ADDR + hex + default 0x100000 + +config SYS_CAR_SIZE + hex + default 0x20000 + +endif diff --git a/arch/x86/lib/efi/Makefile b/arch/x86/lib/efi/Makefile new file mode 100644 index 00000000000..af4503e1c22 --- /dev/null +++ b/arch/x86/lib/efi/Makefile @@ -0,0 +1,27 @@ +# +# (C) Copyright 2002-2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_EFI_STUB) += car.o +obj-$(CONFIG_EFI_STUB) += efi.o + +obj-$(CONFIG_EFI_APP) += crt0-efi-ia32.o reloc_ia32.o + +ifneq ($(CONFIG_EFI_STUB),) + +CFLAGS_REMOVE_reloc_ia32.o += -mregparm=3 +CFLAGS_reloc_ia32.o += -fpic -fshort-wchar + +# When building for 64-bit we must remove the i386-specific flags +CFLAGS_REMOVE_reloc_x86_64.o += -mregparm=3 -march=i386 -m32 +CFLAGS_reloc_x86_64.o += -fpic -fshort-wchar + +AFLAGS_REMOVE_crt0-efi-x86_64.o += -mregparm=3 -march=i386 -m32 +AFLAGS_crt0-efi-x86_64.o += -fpic -fshort-wchar + +extra-$(CONFIG_EFI_STUB_32BIT) += crt0-efi-ia32.o reloc_ia32.o +extra-$(CONFIG_EFI_STUB_64BIT) += crt0-efi-x86_64.o reloc_x86_64.o +endif diff --git a/arch/x86/lib/efi/car.S b/arch/x86/lib/efi/car.S new file mode 100644 index 00000000000..613af9ac8ac --- /dev/null +++ b/arch/x86/lib/efi/car.S @@ -0,0 +1,10 @@ +/* + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.globl car_init +car_init: + jmp car_init_ret diff --git a/arch/x86/lib/efi/crt0-efi-ia32.S b/arch/x86/lib/efi/crt0-efi-ia32.S new file mode 100644 index 00000000000..30e5eb0c1a3 --- /dev/null +++ b/arch/x86/lib/efi/crt0-efi-ia32.S @@ -0,0 +1,52 @@ +/* + * crt0-efi-ia32.S - x86 EFI startup code. + * + * Copyright (C) 1999 Hewlett-Packard Co. + * Contributed by David Mosberger <davidm@hpl.hp.com>. + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + + .text + .align 4 + + .globl _start +_start: + pushl %ebp + movl %esp,%ebp + + pushl 12(%ebp) # copy "image" argument + pushl 8(%ebp) # copy "systab" argument + + call 0f +0: popl %eax + movl %eax,%ebx + + addl $image_base-0b,%eax # %eax = ldbase + addl $_DYNAMIC-0b,%ebx # %ebx = _DYNAMIC + + pushl %ebx # pass _DYNAMIC as second argument + pushl %eax # pass ldbase as first argument + call _relocate + popl %ebx + popl %ebx + testl %eax,%eax + jne .exit + call efi_main # call app with "image" and "systab" argument + +.exit: leave + ret + + /* + * hand-craft a dummy .reloc section so EFI knows it's a relocatable + * executable: + */ + .data +dummy: .long 0 + +#define IMAGE_REL_ABSOLUTE 0 + .section .reloc + .long dummy /* Page RVA */ + .long 10 /* Block Size (2*4+2) */ + .word (IMAGE_REL_ABSOLUTE << 12) + 0 /* reloc for dummy */ diff --git a/arch/x86/lib/efi/crt0-efi-x86_64.S b/arch/x86/lib/efi/crt0-efi-x86_64.S new file mode 100644 index 00000000000..c5cbf4108b3 --- /dev/null +++ b/arch/x86/lib/efi/crt0-efi-x86_64.S @@ -0,0 +1,51 @@ +/* + * crt0-efi-x86_64.S - x86_64 EFI startup code. + * Copyright (C) 1999 Hewlett-Packard Co. + * Contributed by David Mosberger <davidm@hpl.hp.com>. + * Copyright (C) 2005 Intel Co. + * Contributed by Fenghua Yu <fenghua.yu@intel.com>. + * + * All rights reserved. + * SPDX-License-Identifier: BSD-3-Clause + */ + .text + .align 4 + + .globl _start +_start: + subq $8, %rsp + pushq %rcx + pushq %rdx + +0: + lea image_base(%rip), %rdi + lea _DYNAMIC(%rip), %rsi + + popq %rcx + popq %rdx + pushq %rcx + pushq %rdx + call _relocate + + popq %rdi + popq %rsi + + call efi_main + addq $8, %rsp + +.exit: + ret + + /* + * hand-craft a dummy .reloc section so EFI knows it's a relocatable + * executable: + */ + .data +dummy: .long 0 + +#define IMAGE_REL_ABSOLUTE 0 + .section .reloc, "a" +label1: + .long dummy-label1 /* Page RVA */ + .long 10 /* Block Size (2*4+2) */ + .word (IMAGE_REL_ABSOLUTE << 12) + 0 /* reloc for dummy */ diff --git a/arch/x86/lib/efi/efi.c b/arch/x86/lib/efi/efi.c new file mode 100644 index 00000000000..ede5d5676bd --- /dev/null +++ b/arch/x86/lib/efi/efi.c @@ -0,0 +1,151 @@ +/* + * Copyright (c) 2015 Google, Inc + * Written by Simon Glass <sjg@chromium.org> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <debug_uart.h> +#include <efi.h> +#include <errno.h> +#include <linux/err.h> +#include <linux/types.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * This function looks for the highest region of memory lower than 4GB which + * has enough space for U-Boot where U-Boot is aligned on a page boundary. + * It overrides the default implementation found elsewhere which simply + * picks the end of ram, wherever that may be. The location of the stack, + * the relocation address, and how far U-Boot is moved by relocation are + * set in the global data structure. + */ +ulong board_get_usable_ram_top(ulong total_size) +{ + struct efi_mem_desc *desc, *end; + struct efi_entry_memmap *map; + int ret, size; + uintptr_t dest_addr = 0; + struct efi_mem_desc *largest = NULL; + + /* + * Find largest area of memory below 4GB. We could + * call efi_build_mem_table() for a more accurate picture since it + * merges areas together where possible. But that function uses more + * pre-relocation memory, and it's not critical that we find the + * absolute largest region. + */ + ret = efi_info_get(EFIET_MEMORY_MAP, (void **)&map, &size); + if (ret) { + /* We should have stopped in dram_init(), something is wrong */ + debug("%s: Missing memory map\n", __func__); + goto err; + } + + end = (struct efi_mem_desc *)((ulong)map + size); + desc = map->desc; + for (; desc < end; desc = efi_get_next_mem_desc(map, desc)) { + if (desc->type != EFI_CONVENTIONAL_MEMORY || + desc->physical_start >= 1ULL << 32) + continue; + if (!largest || desc->num_pages > largest->num_pages) + largest = desc; + } + + /* If no suitable area was found, return an error. */ + assert(largest); + if (!largest || (largest->num_pages << EFI_PAGE_SHIFT) < (2 << 20)) + goto err; + + dest_addr = largest->physical_start + (largest->num_pages << + EFI_PAGE_SHIFT); + + return (ulong)dest_addr; +err: + panic("No available memory found for relocation"); + return 0; +} + +int dram_init(void) +{ + struct efi_mem_desc *desc, *end; + struct efi_entry_memmap *map; + int size, ret; + + ret = efi_info_get(EFIET_MEMORY_MAP, (void **)&map, &size); + if (ret) { + printf("Cannot find EFI memory map tables, ret=%d\n", ret); + + return -ENODEV; + } + + end = (struct efi_mem_desc *)((ulong)map + size); + gd->ram_size = 0; + desc = map->desc; + for (; desc < end; desc = efi_get_next_mem_desc(map, desc)) { + if (desc->type < EFI_MMAP_IO) + gd->ram_size += desc->num_pages << EFI_PAGE_SHIFT; + } + + return 0; +} + +void dram_init_banksize(void) +{ + struct efi_mem_desc *desc, *end; + struct efi_entry_memmap *map; + int ret, size; + int num_banks; + + ret = efi_info_get(EFIET_MEMORY_MAP, (void **)&map, &size); + if (ret) { + /* We should have stopped in dram_init(), something is wrong */ + debug("%s: Missing memory map\n", __func__); + return; + } + end = (struct efi_mem_desc *)((ulong)map + size); + desc = map->desc; + for (num_banks = 0; + desc < end && num_banks < CONFIG_NR_DRAM_BANKS; + desc = efi_get_next_mem_desc(map, desc)) { + /* + * We only use conventional memory below 4GB, and ignore + * anything less than 1MB. + */ + if (desc->type != EFI_CONVENTIONAL_MEMORY || + desc->physical_start >= 1ULL << 32 || + (desc->num_pages << EFI_PAGE_SHIFT) < 1 << 20) + continue; + gd->bd->bi_dram[num_banks].start = desc->physical_start; + gd->bd->bi_dram[num_banks].size = desc->num_pages << + EFI_PAGE_SHIFT; + num_banks++; + } +} + +int print_cpuinfo(void) +{ + return default_print_cpuinfo(); +} + +/* Find any available tables and copy them to a safe place */ +int reserve_arch(void) +{ + struct efi_info_hdr *hdr; + + debug("table=%lx\n", gd->arch.table); + if (!gd->arch.table) + return 0; + + hdr = (struct efi_info_hdr *)gd->arch.table; + + gd->start_addr_sp -= hdr->total_size; + memcpy((void *)gd->start_addr_sp, hdr, hdr->total_size); + debug("Stashing EFI table at %lx to %lx, size %x\n", + gd->arch.table, gd->start_addr_sp, hdr->total_size); + gd->arch.table = gd->start_addr_sp; + + return 0; +} diff --git a/arch/x86/lib/efi/reloc_ia32.c b/arch/x86/lib/efi/reloc_ia32.c new file mode 100644 index 00000000000..4d6825515d1 --- /dev/null +++ b/arch/x86/lib/efi/reloc_ia32.c @@ -0,0 +1,72 @@ +/* + * reloc_ia32.c - position independent x86 ELF shared object relocator + * Copyright (C) 1999 Hewlett-Packard Co. + * Contributed by David Mosberger <davidm@hpl.hp.com>. + * + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common.h> +#include <efi.h> +#include <elf.h> +#include <asm/elf.h> + +efi_status_t _relocate(long ldbase, Elf32_Dyn *dyn, efi_handle_t image, + struct efi_system_table *systab) +{ + long relsz = 0, relent = 0; + Elf32_Rel *rel = 0; + unsigned long *addr; + int i; + + for (i = 0; dyn[i].d_tag != DT_NULL; ++i) { + switch (dyn[i].d_tag) { + case DT_REL: + rel = (Elf32_Rel *)((unsigned long)dyn[i].d_un.d_ptr + + ldbase); + break; + + case DT_RELSZ: + relsz = dyn[i].d_un.d_val; + break; + + case DT_RELENT: + relent = dyn[i].d_un.d_val; + break; + + case DT_RELA: + break; + + default: + break; + } + } + + if (!rel && relent == 0) + return EFI_SUCCESS; + + if (!rel || relent == 0) + return EFI_LOAD_ERROR; + + while (relsz > 0) { + /* apply the relocs */ + switch (ELF32_R_TYPE(rel->r_info)) { + case R_386_NONE: + break; + + case R_386_RELATIVE: + addr = (unsigned long *)(ldbase + rel->r_offset); + *addr += ldbase; + break; + + default: + break; + } + rel = (Elf32_Rel *)((char *)rel + relent); + relsz -= relent; + } + + return EFI_SUCCESS; +} diff --git a/arch/x86/lib/efi/reloc_x86_64.c b/arch/x86/lib/efi/reloc_x86_64.c new file mode 100644 index 00000000000..5f71f2ac8a3 --- /dev/null +++ b/arch/x86/lib/efi/reloc_x86_64.c @@ -0,0 +1,66 @@ +/* + * reloc_x86_64.c - position independent x86_64 ELF shared object relocator + * Copyright (C) 1999 Hewlett-Packard Co. + * Contributed by David Mosberger <davidm@hpl.hp.com>. + * Copyright (C) 2005 Intel Co. + * Contributed by Fenghua Yu <fenghua.yu@intel.com>. + * + * All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#include <common.h> +#include <efi.h> +#include <elf.h> +#include <asm/elf.h> + +efi_status_t _relocate(long ldbase, Elf64_Dyn *dyn, efi_handle_t image, + struct efi_system_table *systab) +{ + long relsz = 0, relent = 0; + Elf64_Rel *rel = 0; + unsigned long *addr; + int i; + + for (i = 0; dyn[i].d_tag != DT_NULL; ++i) { + switch (dyn[i].d_tag) { + case DT_RELA: + rel = (Elf64_Rel *) + ((unsigned long)dyn[i].d_un.d_ptr + ldbase); + break; + case DT_RELASZ: + relsz = dyn[i].d_un.d_val; + break; + case DT_RELAENT: + relent = dyn[i].d_un.d_val; + break; + default: + break; + } + } + + if (!rel && relent == 0) + return EFI_SUCCESS; + + if (!rel || relent == 0) + return EFI_LOAD_ERROR; + + while (relsz > 0) { + /* apply the relocs */ + switch (ELF64_R_TYPE(rel->r_info)) { + case R_X86_64_NONE: + break; + case R_X86_64_RELATIVE: + addr = (unsigned long *)(ldbase + rel->r_offset); + *addr += ldbase; + break; + default: + break; + } + rel = (Elf64_Rel *)((char *)rel + relent); + relsz -= relent; + } + + return EFI_SUCCESS; +} diff --git a/arch/x86/lib/fsp/fsp_common.c b/arch/x86/lib/fsp/fsp_common.c index 5b256324e17..c585710824c 100644 --- a/arch/x86/lib/fsp/fsp_common.c +++ b/arch/x86/lib/fsp/fsp_common.c @@ -11,6 +11,8 @@ #include <asm/processor.h> #include <asm/fsp/fsp_support.h> +DECLARE_GLOBAL_DATA_PTR; + int print_cpuinfo(void) { post_code(POST_CPU_INFO); diff --git a/arch/x86/lib/lpc-uclass.c b/arch/x86/lib/lpc-uclass.c index 6aeb4d461a9..c6e8f73d225 100644 --- a/arch/x86/lib/lpc-uclass.c +++ b/arch/x86/lib/lpc-uclass.c @@ -9,6 +9,8 @@ #include <dm.h> #include <dm/root.h> +DECLARE_GLOBAL_DATA_PTR; + static int lpc_uclass_post_bind(struct udevice *bus) { /* diff --git a/arch/x86/lib/pch-uclass.c b/arch/x86/lib/pch-uclass.c index d1082e1a475..20dfa815d20 100644 --- a/arch/x86/lib/pch-uclass.c +++ b/arch/x86/lib/pch-uclass.c @@ -9,6 +9,8 @@ #include <dm.h> #include <dm/root.h> +DECLARE_GLOBAL_DATA_PTR; + static int pch_uclass_post_bind(struct udevice *bus) { /* diff --git a/arch/x86/lib/relocate.c b/arch/x86/lib/relocate.c index b33586b54c0..0d683bfc122 100644 --- a/arch/x86/lib/relocate.c +++ b/arch/x86/lib/relocate.c @@ -17,8 +17,6 @@ #include <common.h> #include <inttypes.h> -#include <libfdt.h> -#include <malloc.h> #include <asm/u-boot-x86.h> #include <asm/relocate.h> #include <asm/sections.h> @@ -30,32 +28,20 @@ int copy_uboot_to_ram(void) { size_t len = (size_t)&__data_end - (size_t)&__text_start; + if (gd->flags & GD_FLG_SKIP_RELOC) + return 0; memcpy((void *)gd->relocaddr, (void *)&__text_start, len); return 0; } -int copy_fdt_to_ram(void) -{ - if (gd->new_fdt) { - ulong fdt_size; - - fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32); - - memcpy(gd->new_fdt, gd->fdt_blob, fdt_size); - debug("Relocated fdt from %p to %p, size %lx\n", - gd->fdt_blob, gd->new_fdt, fdt_size); - gd->fdt_blob = gd->new_fdt; - } - - return 0; -} - int clear_bss(void) { ulong dst_addr = (ulong)&__bss_start + gd->reloc_off; size_t len = (size_t)&__bss_end - (size_t)&__bss_start; + if (gd->flags & GD_FLG_SKIP_RELOC) + return 0; memset((void *)dst_addr, 0x00, len); return 0; @@ -72,36 +58,43 @@ int do_elf_reloc_fixups(void) Elf32_Addr *offset_ptr_rom, *last_offset = NULL; Elf32_Addr *offset_ptr_ram; + unsigned int text_base = 0; /* The size of the region of u-boot that runs out of RAM. */ uintptr_t size = (uintptr_t)&__bss_end - (uintptr_t)&__text_start; + if (gd->flags & GD_FLG_SKIP_RELOC) + return 0; if (re_src == re_end) panic("No relocation data"); +#ifdef CONFIG_SYS_TEXT_BASE + text_base = CONFIG_SYS_TEXT_BASE; +#else + panic("No CONFIG_SYS_TEXT_BASE"); +#endif do { /* Get the location from the relocation entry */ offset_ptr_rom = (Elf32_Addr *)re_src->r_offset; /* Check that the location of the relocation is in .text */ - if (offset_ptr_rom >= (Elf32_Addr *)CONFIG_SYS_TEXT_BASE && - offset_ptr_rom > last_offset) { + if (offset_ptr_rom >= (Elf32_Addr *)text_base && + offset_ptr_rom > last_offset) { /* Switch to the in-RAM version */ offset_ptr_ram = (Elf32_Addr *)((ulong)offset_ptr_rom + gd->reloc_off); /* Check that the target points into .text */ - if (*offset_ptr_ram >= CONFIG_SYS_TEXT_BASE && - *offset_ptr_ram <= - (CONFIG_SYS_TEXT_BASE + size)) { + if (*offset_ptr_ram >= text_base && + *offset_ptr_ram <= text_base + size) { *offset_ptr_ram += gd->reloc_off; } else { debug(" %p: rom reloc %x, ram %p, value %x," " limit %" PRIXPTR "\n", re_src, re_src->r_offset, offset_ptr_ram, *offset_ptr_ram, - CONFIG_SYS_TEXT_BASE + size); + text_base + size); } } else { debug(" %p: rom reloc %x, last %p\n", re_src, diff --git a/arch/x86/lib/tsc_timer.c b/arch/x86/lib/tsc_timer.c index 7f5ba2ca6f1..0df1af238c1 100644 --- a/arch/x86/lib/tsc_timer.c +++ b/arch/x86/lib/tsc_timer.c @@ -355,7 +355,15 @@ void __udelay(unsigned long usec) stop = now + usec * get_tbclk_mhz(); while ((int64_t)(stop - get_ticks()) > 0) +#if defined(CONFIG_QEMU) && defined(CONFIG_SMP) + /* + * Add a 'pause' instruction on qemu target, + * to give other VCPUs a chance to run. + */ + asm volatile("pause"); +#else ; +#endif } int timer_init(void) |