diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arc/dts/axs10x_mb.dtsi | 28 | ||||
| -rw-r--r-- | arch/arc/dts/hsdk.dts | 26 |
2 files changed, 54 insertions, 0 deletions
diff --git a/arch/arc/dts/axs10x_mb.dtsi b/arch/arc/dts/axs10x_mb.dtsi index b5aacd5170e..6d97de9fd8c 100644 --- a/arch/arc/dts/axs10x_mb.dtsi +++ b/arch/arc/dts/axs10x_mb.dtsi @@ -31,6 +31,25 @@ #clock-cells = <0>; u-boot,dm-pre-reloc; }; + + mmcclk_ciu: mmcclk-ciu { + compatible = "fixed-clock"; + /* + * DW sdio controller has external ciu clock divider + * controlled via register in SDIO IP. It divides + * sdio_ref_clk (which comes from CGU) by 16 for + * default. So default mmcclk clock (which comes + * to sdk_in) is 25000000 Hz. + */ + clock-frequency = <25000000>; + #clock-cells = <0>; + }; + + mmcclk_biu: mmcclk-biu { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + #clock-cells = <0>; + }; }; ethernet@18000 { @@ -53,6 +72,15 @@ reg = < 0x60000 0x100 >; }; + mmc: mmc@15000 { + compatible = "snps,dw-mshc"; + reg = <0x15000 0x400>; + bus-width = <4>; + clocks = <&mmcclk_biu>, <&mmcclk_ciu>; + clock-names = "biu", "ciu"; + max-frequency = <25000000>; + }; + uart0: serial0@22000 { compatible = "snps,dw-apb-uart"; reg = <0x22000 0x100>; diff --git a/arch/arc/dts/hsdk.dts b/arch/arc/dts/hsdk.dts index 5e9ba054a4c..7028050447b 100644 --- a/arch/arc/dts/hsdk.dts +++ b/arch/arc/dts/hsdk.dts @@ -86,6 +86,32 @@ reg = <0xf0060000 0x100>; }; + mmcclk_ciu: mmcclk-ciu { + compatible = "fixed-clock"; + /* + * DW sdio controller has external ciu clock divider + * controlled via register in SDIO IP. Due to its + * unexpected default value (it should divide by 1 + * but it divides by 8) SDIO IP uses wrong clock and + * works unstable (see STAR 9001204800) + * We switched to the minimum possible value of the + * divisor (div-by-2) in HSDK platform code. + * So default mmcclk ciu clock is 50000000 Hz. + */ + clock-frequency = <50000000>; + #clock-cells = <0>; + }; + + mmc: mmc0@f000a000 { + compatible = "snps,dw-mshc"; + reg = <0xf000a000 0x400>; + bus-width = <4>; + fifo-depth = <256>; + clocks = <&cgu_clk CLK_SYS_SDIO>, <&mmcclk_ciu>; + clock-names = "biu", "ciu"; + max-frequency = <25000000>; + }; + spi0: spi@f0020000 { compatible = "snps,dw-apb-ssi"; reg = <0xf0020000 0x1000>; |