diff options
Diffstat (limited to 'arch')
38 files changed, 1182 insertions, 13 deletions
diff --git a/arch/Kconfig b/arch/Kconfig index 70232239278..dd1ff9d963f 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -162,6 +162,8 @@ config SANDBOX imply CMD_CLONE imply SILENT_CONSOLE imply BOOTARGS_SUBST + imply PHY_FIXED + imply DM_DSA config SH bool "SuperH architecture" diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 01b5ba58deb..b39b043efe3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1463,6 +1463,24 @@ config TARGET_LS1021ATWR select DM_SPI_FLASH if FSL_DSPI || FSL_QSPI imply SCSI +config TARGET_PG_WCOM_SELI8 + bool "Support Hitachi-Powergrids SELI8 service unit card" + select ARCH_LS1021A + select ARCH_SUPPORT_PSCI + select BOARD_EARLY_INIT_F + select BOARD_LATE_INIT + select CPU_V7A + select CPU_V7_HAS_NONSEC + select CPU_V7_HAS_VIRT + select SYS_FSL_DDR + select FSL_DDR_INTERACTIVE + select VENDOR_KM + imply SCSI + help + Support for Hitachi-Powergrids SELI8 service unit card. + SELI8 is a QorIQ LS1021a based service unit card used + in XMC20 and FOX615 product families. + config TARGET_LS1021ATSN bool "Support ls1021atsn" select ARCH_LS1021A @@ -1587,6 +1605,26 @@ config TARGET_SL28 select ARMV8_MULTIENTRY select SUPPORT_SPL select BINMAN + select DM + select DM_GPIO + select DM_I2C + select DM_MMC + select DM_SPI_FLASH + select DM_ETH + select DM_MDIO + select DM_PCI + select DM_RNG + select DM_RTC + select DM_SCSI + select DM_SERIAL + select DM_SPI + select DM_USB + select SPL_DM if SPL + select SPL_DM_SPI if SPL + select SPL_DM_SPI_FLASH if SPL + select SPL_DM_I2C if SPL + select SPL_DM_MMC if SPL + select SPL_DM_SERIAL if SPL help Support for Kontron SMARC-sAL28 board. @@ -1972,6 +2010,7 @@ source "board/variscite/dart_6ul/Kconfig" source "board/vscom/baltos/Kconfig" source "board/phytium/durian/Kconfig" source "board/xen/xenguest_arm64/Kconfig" +source "board/keymile/Kconfig" source "arch/arm/Kconfig.debug" diff --git a/arch/arm/cpu/armv8/fsl-layerscape/spl.c b/arch/arm/cpu/armv8/fsl-layerscape/spl.c index d5131bcf4b3..01dd6a30e87 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/spl.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/spl.c @@ -6,7 +6,9 @@ #include <common.h> #include <clock_legacy.h> #include <cpu_func.h> +#include <debug_uart.h> #include <env.h> +#include <hang.h> #include <image.h> #include <init.h> #include <log.h> @@ -67,10 +69,19 @@ void spl_board_init(void) void board_init_f(ulong dummy) { + int ret; + icache_enable(); /* Clear global data */ memset((void *)gd, 0, sizeof(gd_t)); + if (IS_ENABLED(CONFIG_DEBUG_UART)) + debug_uart_init(); board_early_init_f(); + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } timer_init(); #ifdef CONFIG_ARCH_LS2080A env_init(); diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index b58f8414726..1dd6c4b2e8a 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -398,6 +398,8 @@ dtb-$(CONFIG_ARCH_LS1021A) += ls1021a-qds-duart.dtb \ ls1021a-qds-lpuart.dtb \ ls1021a-twr-duart.dtb ls1021a-twr-lpuart.dtb \ ls1021a-iot-duart.dtb ls1021a-tsn.dtb +dtb-$(CONFIG_TARGET_PG_WCOM_SELI8) += ls1021a-pg-wcom-seli8.dtb + dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \ fsl-ls2080a-qds-42-x.dtb \ fsl-ls2080a-rdb.dtb \ diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi index 240178ab4e7..b3861ed98cf 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi @@ -133,6 +133,14 @@ }; }; +#ifdef CONFIG_SL28_ENABLE_SER0_CONSOLE +/ { + chosen { + stdout-path = "serial2:115200n8"; + }; +}; +#endif + #ifdef CONFIG_SL28_SPL_LOADS_ATF_BL31 &binman { fit { @@ -250,6 +258,10 @@ u-boot,dm-pre-reloc; }; +&lpuart1 { + u-boot,dm-pre-reloc; +}; + &serial0 { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi new file mode 100644 index 00000000000..23816da8eeb --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1028A-QDS device tree fragment for RCW 1xxx + * + * Copyright 2019-2021 NXP Semiconductors + */ + +/* + * This setup is using a SCH-30842 card with AQR112 PHY in slot 1 for ENETC + * port 0 USXGMII. + */ +&slot1 { + #include "fsl-sch-30842.dtsi" +}; + +&enetc0 { + status = "okay"; + phy-mode = "usxgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi new file mode 100644 index 00000000000..c6558ae2e07 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1028A-QDS device tree fragment for RCW 6xxx + * + * Copyright 2019-2021 NXP Semiconductors + */ + +/* + * This setup is using SCH-30842 cards with AQR112 PHY. + */ +&slot1 { + #include "fsl-sch-30842.dtsi" +}; + +&enetc0 { + status = "okay"; + phy-mode = "sgmii-2500"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi new file mode 100644 index 00000000000..fb1836a8aef --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1028A-QDS device tree fragment for RCW 7777 + * + * Copyright 2019-2021 NXP Semiconductors + */ + +/* + * This setup is using a SCH-30841 card with AQR412 10G quad PHY. + * + * Switch ports are mapped 1:1 to AQR412 card ports seated in slot 1. + * Bottom port is port 0. + * Note that this is only usable for: + * - QDS boards WITHOUT lane B rework, + * - AQR412 card WITHOUT lane A -> lane C rework + * + * The following DTS assumes DIP SW5[1-3] = 000b. + */ +&slot1 { +#include "fsl-sch-30841.dtsi" +}; + +&mscc_felix { + status = "okay"; +}; + +&mscc_felix_port0 { + status = "okay"; + phy-mode = "sgmii-2500"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@00}>; +}; + +&mscc_felix_port1 { + status = "okay"; + phy-mode = "sgmii-2500"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@01}>; +}; + +&mscc_felix_port2 { + status = "okay"; + phy-mode = "sgmii-2500"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; +}; + +&mscc_felix_port3 { + status = "okay"; + phy-mode = "sgmii-2500"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi new file mode 100644 index 00000000000..1d02a3e11de --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1028A-QDS device tree fragment for RCW 7xx7 + * + * Copyright 2019-2021 NXP Semiconductors + */ + +&slot1 { +#include "fsl-sch-30841.dtsi" +}; + +&mscc_felix { + status = "okay"; +}; + +&mscc_felix_port0 { + status = "okay"; + phy-mode = "sgmii-2500"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; +}; + +&mscc_felix_port3 { + status = "okay"; + phy-mode = "sgmii-2500"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi b/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi new file mode 100644 index 00000000000..7d4702e4ff2 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1028A-QDS device tree fragment for RCW 8xxx + * + * Copyright 2019-2021 NXP Semiconductors + */ + +/* + * This setup is using SCH-24801 cards with VSC8234 quad SGMII PHY in slot 1. + */ +&slot1 { + #include "fsl-sch-24801.dtsi" +}; + +&enetc0 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi new file mode 100644 index 00000000000..c92dd1bd2e9 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi @@ -0,0 +1,63 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1028A-QDS device tree fragment for RCW 9999 + * + * Copyright 2019-2021 NXP Semiconductors + */ + +/* + * This setup is using SCH-24801 cards with VSC8234 quad SGMII PHY. + * LS1028A QDS boards with lane B rework require two cards for the 4 switch + * ports, QDS boards without the lane B rework only require one card. + * + * Switch ports are routed as follows: + * Port 0 goes to 1st port of VSC8234 quad card in slot 1, + * Port 1: + * - if the QDS has had lane B rework, it is 1st port in slot 2, + * - otherwise it is 2nd port in slot 1. + * Port 2: + * - if DIP SW5[1] = 0 it is 3rd port in slot 1, + * - otherwise it is 1st port in slot 3. + * Port 3: + * - if DIP SW5[2-3] = 00b it is 4th port in slot 1, + * - if DIP SW5[2-3] = 01b it is 2nd port in slot 3, + * - if DIP SW5[2-3] = 11b it is 1st port in slot 4. + * + * The following DTS assumes QDS lane B rework and DIP SW5[1-3] = 000b. Two + * SCH-24801 cards are required in slots 1 and 2. + */ +&slot1 { + #include "fsl-sch-24801.dtsi" +}; + +&slot2 { + #include "fsl-sch-24801.dtsi" +}; + +&mscc_felix { + status = "okay"; +}; + +&mscc_felix_port0 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>; +}; + +&mscc_felix_port1 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@1c}>; +}; + +&mscc_felix_port2 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>; +}; + +&mscc_felix_port3 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi new file mode 100644 index 00000000000..941f7472eb0 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1028A-QDS device tree fragment for RCW 9999 + * + * Copyright 2019-2021 NXP Semiconductors + * + */ + +/* + * This set-up is using SCH-24801 cards with VSC8234 quad SGMII PHY. + * + * Switch ports are mapped 1:1 to VSC8234 card ports seated in slot 1. + * Top port is port 0. + * + * The following DTS assumes DIP SW5[1-3] = 000b. + */ + +&slot1 { + #include "fsl-sch-24801.dtsi" +}; + +&mscc_felix { + status = "okay"; +}; + +&mscc_felix_port0 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>; +}; + +&mscc_felix_port1 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1d}>; +}; + +&mscc_felix_port2 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>; +}; + +&mscc_felix_port3 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi new file mode 100644 index 00000000000..7e483e656e2 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1028A-QDS device tree fragment for RCW x3xx + * + * Copyright 2019-2021 NXP Semiconductors + */ + +/* + * This setup is using a SCH-30841-R card with AQR412 quad PHY in slot 2. This + * is used for the 4 integrated ethernet switch in a multiplexes USXGMII set-up. + * + * We're including the normal .dsti file, not the reworked card .dtsi + * intentionally. We are using multiplexing of the 4 interfaces on a single + * lane and the rework doesn't actually disable any port. The rework is in fact + * needed, otherwise the PHY won't work with the default wiring on the QDS/PHY + * card. + */ +&slot2 { +#include "fsl-sch-30841.dtsi" +}; + +&mscc_felix { + status = "okay"; +}; + +&mscc_felix_port0 { + status = "okay"; + phy-mode = "usxgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@00}>; +}; + +&mscc_felix_port1 { + status = "okay"; + phy-mode = "usxgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@01}>; +}; + +&mscc_felix_port2 { + status = "okay"; + phy-mode = "usxgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>; +}; + +&mscc_felix_port3 { + status = "okay"; + phy-mode = "usxgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@03}>; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi new file mode 100644 index 00000000000..49fffdb9cb2 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1028A-QDS device tree fragment for RCW x5xx + * + * Copyright 2019-2021 NXP Semiconductors + */ + +/* + * This setup is using SCH-28021 cards with VSC8514 QSGMII PHY in slot 2. + * This is only available on LS1028A QDS boards with lane B rework. + */ +&slot2 { + #include "fsl-sch-28021.dtsi" +}; + +&mscc_felix { + status = "okay"; +}; + +&mscc_felix_port0 { + status = "okay"; + phy-mode = "qsgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@08}>; +}; + +&mscc_felix_port1 { + status = "okay"; + phy-mode = "qsgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@09}>; +}; + +&mscc_felix_port2 { + status = "okay"; + phy-mode = "qsgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0a}>; +}; + +&mscc_felix_port3 { + status = "okay"; + phy-mode = "qsgmii"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0b}>; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi new file mode 100644 index 00000000000..8347462f4cb --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1028A-QDS device tree fragment for RCW 7777 + * + * Copyright 2019-2021 NXP Semiconductors + */ + +&slot2 { +#include "fsl-sch-30842.dtsi" +}; + +&mscc_felix { + status = "okay"; +}; + +&mscc_felix_port1 { + status = "okay"; + phy-mode = "sgmii-2500"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi new file mode 100644 index 00000000000..6be3b5094c8 --- /dev/null +++ b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * NXP LS1028A-QDS device tree fragment for RCW 7777 + * + * Copyright 2019-2021 NXP Semiconductors + */ + +&slot3 { +#include "fsl-sch-30842.dtsi" +}; + +&mscc_felix { + status = "okay"; +}; + +&mscc_felix_port2 { + status = "okay"; + phy-mode = "sgmii-2500"; + phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@60/phy@02}>; +}; diff --git a/arch/arm/dts/fsl-ls1028a-qds.dtsi b/arch/arm/dts/fsl-ls1028a-qds.dtsi index 6cdcce1b92f..da89ff96e98 100644 --- a/arch/arm/dts/fsl-ls1028a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds.dtsi @@ -258,3 +258,6 @@ &mdio0 { status = "okay"; }; + +#include "fsl-ls1028a-qds-8xxx-sch-24801.dtsi" +#include "fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi" diff --git a/arch/arm/dts/fsl-sch-24801.dtsi b/arch/arm/dts/fsl-sch-24801.dtsi new file mode 100644 index 00000000000..304afdabc59 --- /dev/null +++ b/arch/arm/dts/fsl-sch-24801.dtsi @@ -0,0 +1,28 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Device tree fragment for RCW SCH-24801 card + * + * Copyright 2019-2021 NXP Semiconductors + */ + +/* + * SCH-24801 is a 4xSGMII add-on card used with various FSL QDS boards. + * It integrates a VSC8234 quad PHY which supports 4 SGMII interfaces. + * PHY addresses are 0x1c - 0x1f. + * On the card the first port is the top port (farthest from PEX connector). + */ +phy@1c { + reg = <0x1c>; +}; + +phy@1d { + reg = <0x1d>; +}; + +phy@1e { + reg = <0x1e>; +}; + +phy@1f { + reg = <0x1f>; +}; diff --git a/arch/arm/dts/fsl-sch-28021.dtsi b/arch/arm/dts/fsl-sch-28021.dtsi new file mode 100644 index 00000000000..584f3fa68cd --- /dev/null +++ b/arch/arm/dts/fsl-sch-28021.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Device tree fragment for RCW SCH-28021 card + * + * Copyright 2019-2021 NXP Semiconductors + */ + +/* + * SCH-28021 is a QSGMII add-on card used with various FSL QDS boards. + * It integrates a VSC8514 quad PHY which supports 4 interfaces muxed on a + * single QSGMII lane. + * PHY addresses are 0x08 - 0x0b. + * On the card the first port is the top port (farthest from PEX connector). + */ +phy@08 { + reg = <0x08>; +}; + +phy@09 { + reg = <0x09>; +}; + +phy@0a { + reg = <0x0a>; +}; + +phy@0b { + reg = <0x0b>; +}; diff --git a/arch/arm/dts/fsl-sch-30841.dtsi b/arch/arm/dts/fsl-sch-30841.dtsi new file mode 100644 index 00000000000..ca437d17828 --- /dev/null +++ b/arch/arm/dts/fsl-sch-30841.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Device tree fragment for RCW SCH-30841 card + * + * Copyright 2019-2021 NXP Semiconductors + */ + +/* + * SCH-30841 is a 4 port add-on card used with various FSL QDS boards. + * It integrates a AQR412C quad PHY which supports 4 interfaces either muxed + * together on a single lane or mapped 1:1 to serdes lanes. + * It supports several protocols - SGMII, SGMII-2500, USXGMII, M-USX, XFI. + * PHY addresses are 0x00 - 0x03. + * On the card the first port is the bottom port (closest to PEX connector). + */ +phy@00 { + reg = <0x00>; + mdi-reversal = <1>; + smb-addr = <0x25>; +}; + +phy@01 { + reg = <0x01>; + mdi-reversal = <1>; + smb-addr = <0x26>; +}; + +phy@02 { + reg = <0x02>; + mdi-reversal = <1>; + smb-addr = <0x27>; +}; + +phy@03 { + reg = <0x03>; + mdi-reversal = <1>; + smb-addr = <0x28>; +}; diff --git a/arch/arm/dts/fsl-sch-30842.dtsi b/arch/arm/dts/fsl-sch-30842.dtsi new file mode 100644 index 00000000000..fa0f2cdb109 --- /dev/null +++ b/arch/arm/dts/fsl-sch-30842.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0+ OR X11 +/* + * Device tree fragment for RCW SCH-30842 card + * + * Copyright 2019-2021 NXP Semiconductors + */ + +/* + * SCH-30842 is a single port add-on card used with various FSL QDS boards. + * It integrates a AQR112 PHY, which supports several protocols - SGMII, + * SGMII-2500, USXGMII, XFI. + * PHY address is 0x02. + */ +phy@02 { + reg = <0x02>; + mdi-reversal = <1>; + smb-addr = <0x25>; +}; diff --git a/arch/arm/dts/ls1021a-pg-wcom-seli8.dts b/arch/arm/dts/ls1021a-pg-wcom-seli8.dts new file mode 100644 index 00000000000..e335188bc6f --- /dev/null +++ b/arch/arm/dts/ls1021a-pg-wcom-seli8.dts @@ -0,0 +1,111 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2013-2015 Freescale Semiconductor, Inc. + * Copyright 2020 Hitachi Power Grids. All rights reserved. + */ + +/dts-v1/; +#include "ls1021a.dtsi" + +/ { + model = "Hitachi-Powergrids SELI8 Service Unit for XMC and FOX"; + + chosen { + stdout-path = &uart0; + }; +}; + +&enet0 { + status = "okay"; + tbi-handle = <&tbi0>; + phy-connection-type = "sgmii"; + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&enet1 { + status = "okay"; + tbi-handle = <&tbi1>; + phy-connection-type = "sgmii"; + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&enet2 { + phy-handle = <&debug_phy>; + phy-connection-type = "rgmii-id"; + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&ifc { + #address-cells = <2>; + #size-cells = <1>; + /* NOR Flash on board */ + ranges = <0x0 0x0 0x60000000 0x04000000>; + status = "okay"; + + nor@0,0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "cfi-flash"; + reg = <0x0 0x0 0x4000000>; + bank-width = <2>; + device-width = <1>; + + partition@0 { + label = "rcw"; + reg = <0x0 0x20000>; + read-only; + }; + partition@20000 { + label = "qe"; + reg = <0x20000 0x20000>; + }; + partition@40000 { + label = "envred"; + reg = <0x40000 0x20000>; + }; + partition@60000 { + label = "env"; + reg = <0x60000 0x20000>; + }; + partition@100000 { + label = "u-boot"; + reg = <0x100000 0x100000>; + }; + partition@200000 { + label = "ubi0"; + reg = <0x200000 0x3E00000>; + }; + }; +}; + +&mdio0 { + debug_phy: ethernet-phy@11 { + reg = <0x11>; + }; + + tbi0: tbi-phy@0xb { + reg = <0xb>; + device_type = "tbi-phy"; + }; +}; + +&mdio1 { + tbi1: tbi-phy@0xd { + reg = <0xd>; + device_type = "tbi-phy"; + }; +}; + +&uart0 { + status = "okay"; +}; diff --git a/arch/powerpc/dts/qoriq-fman3-1-10g-0.dtsi b/arch/powerpc/dts/qoriq-fman3-1-10g-0.dtsi index 889c8d450e0..65bb8a4b0b6 100644 --- a/arch/powerpc/dts/qoriq-fman3-1-10g-0.dtsi +++ b/arch/powerpc/dts/qoriq-fman3-1-10g-0.dtsi @@ -30,7 +30,7 @@ fman@500000 { pcsphy-handle = <&pcsphy14>; }; - mdio@f1000 { + mdio@5f1000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; diff --git a/arch/powerpc/dts/qoriq-fman3-1-10g-1.dtsi b/arch/powerpc/dts/qoriq-fman3-1-10g-1.dtsi index 2e456983372..eb39d29b39f 100644 --- a/arch/powerpc/dts/qoriq-fman3-1-10g-1.dtsi +++ b/arch/powerpc/dts/qoriq-fman3-1-10g-1.dtsi @@ -30,7 +30,7 @@ fman@500000 { pcsphy-handle = <&pcsphy15>; }; - mdio@f3000 { + mdio@5f3000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; diff --git a/arch/powerpc/dts/qoriq-fman3-1-1g-0.dtsi b/arch/powerpc/dts/qoriq-fman3-1-1g-0.dtsi index b4ff19bf495..2f2209dbc9b 100644 --- a/arch/powerpc/dts/qoriq-fman3-1-1g-0.dtsi +++ b/arch/powerpc/dts/qoriq-fman3-1-1g-0.dtsi @@ -29,7 +29,7 @@ fman@500000 { pcsphy-handle = <&pcsphy8>; }; - mdio@e1000 { + mdio@5e1000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; diff --git a/arch/powerpc/dts/qoriq-fman3-1-1g-1.dtsi b/arch/powerpc/dts/qoriq-fman3-1-1g-1.dtsi index 239c56ad1f6..11653c58b5f 100644 --- a/arch/powerpc/dts/qoriq-fman3-1-1g-1.dtsi +++ b/arch/powerpc/dts/qoriq-fman3-1-1g-1.dtsi @@ -29,7 +29,7 @@ fman@500000 { pcsphy-handle = <&pcsphy9>; }; - mdio@e3000 { + mdio@5e3000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; diff --git a/arch/powerpc/dts/qoriq-fman3-1-1g-2.dtsi b/arch/powerpc/dts/qoriq-fman3-1-1g-2.dtsi index 6e2bb009d9a..ae27c7bc6df 100644 --- a/arch/powerpc/dts/qoriq-fman3-1-1g-2.dtsi +++ b/arch/powerpc/dts/qoriq-fman3-1-1g-2.dtsi @@ -29,7 +29,7 @@ fman@500000 { pcsphy-handle = <&pcsphy10>; }; - mdio@e5000 { + mdio@5e5000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; diff --git a/arch/powerpc/dts/qoriq-fman3-1-1g-3.dtsi b/arch/powerpc/dts/qoriq-fman3-1-1g-3.dtsi index 29dd94ba749..55ae5499176 100644 --- a/arch/powerpc/dts/qoriq-fman3-1-1g-3.dtsi +++ b/arch/powerpc/dts/qoriq-fman3-1-1g-3.dtsi @@ -29,7 +29,7 @@ fman@500000 { pcsphy-handle = <&pcsphy11>; }; - mdio@e7000 { + mdio@5e7000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; diff --git a/arch/powerpc/dts/qoriq-fman3-1-1g-4.dtsi b/arch/powerpc/dts/qoriq-fman3-1-1g-4.dtsi index a5b49358270..833cf3e23d8 100644 --- a/arch/powerpc/dts/qoriq-fman3-1-1g-4.dtsi +++ b/arch/powerpc/dts/qoriq-fman3-1-1g-4.dtsi @@ -29,7 +29,7 @@ fman@500000 { pcsphy-handle = <&pcsphy12>; }; - mdio@e9000 { + mdio@5e9000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; diff --git a/arch/powerpc/dts/qoriq-fman3-1-1g-5.dtsi b/arch/powerpc/dts/qoriq-fman3-1-1g-5.dtsi index 486c84bf981..81da55dfbe2 100644 --- a/arch/powerpc/dts/qoriq-fman3-1-1g-5.dtsi +++ b/arch/powerpc/dts/qoriq-fman3-1-1g-5.dtsi @@ -29,7 +29,7 @@ fman@500000 { pcsphy-handle = <&pcsphy13>; }; - mdio@eb000 { + mdio@5eb000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; diff --git a/arch/powerpc/dts/qoriq-fman3-1.dtsi b/arch/powerpc/dts/qoriq-fman3-1.dtsi index d8609c3ecfd..9efcf26c4ab 100644 --- a/arch/powerpc/dts/qoriq-fman3-1.dtsi +++ b/arch/powerpc/dts/qoriq-fman3-1.dtsi @@ -61,14 +61,14 @@ fman1: fman@500000 { reg = <0x87000 0x1000>; }; - mdio1: mdio@fc000 { + mdio1: mdio@5fc000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; reg = <0xfc000 0x1000>; }; - mdio@fd000 { + mdio@5fd000 { #address-cells = <1>; #size-cells = <0>; compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; diff --git a/arch/powerpc/dts/t1042d4rdb.dts b/arch/powerpc/dts/t1042d4rdb.dts index 3584c06aa8d..5e9fab7a105 100644 --- a/arch/powerpc/dts/t1042d4rdb.dts +++ b/arch/powerpc/dts/t1042d4rdb.dts @@ -3,7 +3,7 @@ * T1042D4RDB Device Tree Source * * Copyright 2013 - 2015 Freescale Semiconductor Inc. - * Copyright 2019 NXP + * Copyright 2019-2021 NXP */ /include/ "t104x.dtsi" @@ -20,6 +20,57 @@ }; }; +&soc { + fman0: fman@400000 { + ethernet@e0000 { + phy-handle = <&phy_sgmii_0>; + phy-connection-type = "sgmii"; + }; + + ethernet@e2000 { + phy-handle = <&phy_sgmii_1>; + phy-connection-type = "sgmii"; + }; + + ethernet@e4000 { + phy-handle = <&phy_sgmii_2>; + phy-connection-type = "sgmii"; + }; + + ethernet@e6000 { + phy-handle = <&phy_rgmii_0>; + phy-connection-type = "rgmii"; + }; + + ethernet@e8000 { + phy-handle = <&phy_rgmii_1>; + phy-connection-type = "rgmii"; + }; + + mdio0: mdio@fc000 { + phy_sgmii_0: ethernet-phy@2 { + reg = <0x02>; + }; + + phy_sgmii_1: ethernet-phy@3 { + reg = <0x03>; + }; + + phy_sgmii_2: ethernet-phy@1 { + reg = <0x01>; + }; + + phy_rgmii_0: ethernet-phy@4 { + reg = <0x04>; + }; + + phy_rgmii_1: ethernet-phy@5 { + reg = <0x05>; + }; + }; + }; +}; + &espi0 { status = "okay"; flash@0 { @@ -30,3 +81,5 @@ spi-max-frequency = <10000000>; /* input clock */ }; }; + +/include/ "t1042si-post.dtsi" diff --git a/arch/powerpc/dts/t1042si-post.dtsi b/arch/powerpc/dts/t1042si-post.dtsi new file mode 100644 index 00000000000..5c60944e607 --- /dev/null +++ b/arch/powerpc/dts/t1042si-post.dtsi @@ -0,0 +1,46 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * T1042 Silicon/SoC Device Tree Source (post include) + * + * Copyright 2013 - 2014 Freescale Semiconductor Inc. + * Copyright 2021 NXP + * + */ +&soc { +/include/ "qoriq-clockgen2.dtsi" +/include/ "qoriq-gpio-0.dtsi" +/include/ "qoriq-gpio-1.dtsi" +/include/ "qoriq-gpio-2.dtsi" +/include/ "qoriq-gpio-3.dtsi" + +/include/ "qoriq-fman3l-0.dtsi" +/include/ "qoriq-fman3-0-1g-0.dtsi" +/include/ "qoriq-fman3-0-1g-1.dtsi" +/include/ "qoriq-fman3-0-1g-2.dtsi" +/include/ "qoriq-fman3-0-1g-3.dtsi" +/include/ "qoriq-fman3-0-1g-4.dtsi" + fman@400000 { + enet0: ethernet@e0000 { + }; + + enet1: ethernet@e2000 { + }; + + enet2: ethernet@e4000 { + }; + + enet3: ethernet@e6000 { + }; + + enet4: ethernet@e8000 { + }; + + mdio@fc000 { + interrupts = <100 1 0 0>; + }; + + mdio@fd000 { + status = "disabled"; + }; + }; +}; diff --git a/arch/powerpc/dts/t2080rdb.dts b/arch/powerpc/dts/t2080rdb.dts index 74bbb20e2a1..25f8c978c6d 100644 --- a/arch/powerpc/dts/t2080rdb.dts +++ b/arch/powerpc/dts/t2080rdb.dts @@ -3,7 +3,7 @@ * T2080RDB Device Tree Source * * Copyright 2013 - 2015 Freescale Semiconductor Inc. - * Copyright 2019 NXP + * Copyright 2019-2021 NXP */ /include/ "t2080.dtsi" @@ -20,6 +20,71 @@ }; }; +&soc { + fman@400000 { + ethernet@e0000 { + phy-handle = <&xg_aq1202_phy3>; + phy-connection-type = "xgmii"; + }; + + ethernet@e2000 { + phy-handle = <&xg_aq1202_phy4>; + phy-connection-type = "xgmii"; + }; + + ethernet@e4000 { + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii"; + }; + + ethernet@e6000 { + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii"; + }; + + ethernet@f0000 { + phy-handle = <&xg_cs4315_phy2>; + phy-connection-type = "xgmii"; + }; + + ethernet@f2000 { + phy-handle = <&xg_cs4315_phy1>; + phy-connection-type = "xgmii"; + }; + + mdio@fc000 { + rgmii_phy1: ethernet-phy@1 { + reg = <0x1>; + }; + rgmii_phy2: ethernet-phy@2 { + reg = <0x2>; + }; + }; + + mdio@fd000 { + xg_cs4315_phy1: ethernet-phy@c { + compatible = "ethernet-phy-id13e5.1002"; + reg = <0xc>; + }; + + xg_cs4315_phy2: ethernet-phy@d { + compatible = "ethernet-phy-id13e5.1002"; + reg = <0xd>; + }; + + xg_aq1202_phy3: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x0>; + }; + + xg_aq1202_phy4: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <0x1>; + }; + }; + }; +}; + &espi0 { status = "okay"; flash@0 { @@ -38,3 +103,5 @@ reg = <0x68>; }; }; + +/include/ "t2080si-post.dtsi" diff --git a/arch/powerpc/dts/t2080si-post.dtsi b/arch/powerpc/dts/t2080si-post.dtsi new file mode 100644 index 00000000000..d8ef579cb7c --- /dev/null +++ b/arch/powerpc/dts/t2080si-post.dtsi @@ -0,0 +1,51 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * T2080 Silicon/SoC Device Tree Source (post include) + * + * Copyright 2013 Freescale Semiconductor Inc. + * Copyright 2021 NXP + * + */ +&soc { + +/include/ "qoriq-clockgen2.dtsi" +/include/ "qoriq-gpio-0.dtsi" +/include/ "qoriq-gpio-1.dtsi" +/include/ "qoriq-gpio-2.dtsi" +/include/ "qoriq-gpio-3.dtsi" + +/include/ "qoriq-fman3-0.dtsi" +/include/ "qoriq-fman3-0-10g-0-best-effort.dtsi" +/include/ "qoriq-fman3-0-10g-1-best-effort.dtsi" +/include/ "qoriq-fman3-0-1g-2.dtsi" +/include/ "qoriq-fman3-0-1g-3.dtsi" +/include/ "qoriq-fman3-0-10g-0.dtsi" +/include/ "qoriq-fman3-0-10g-1.dtsi" + fman@400000 { + enet0: ethernet@e0000 { + }; + + enet1: ethernet@e2000 { + }; + + enet2: ethernet@e4000 { + }; + + enet3: ethernet@e6000 { + }; + + enet6: ethernet@f0000 { + }; + + enet7: ethernet@f2000 { + }; + + mdio@fc000 { + interrupts = <100 1 0 0>; + }; + + mdio@fd000 { + interrupts = <101 1 0 0>; + }; + }; +}; diff --git a/arch/powerpc/dts/t4240rdb.dts b/arch/powerpc/dts/t4240rdb.dts index 635065a0368..b3251e330de 100644 --- a/arch/powerpc/dts/t4240rdb.dts +++ b/arch/powerpc/dts/t4240rdb.dts @@ -3,7 +3,7 @@ * T4240RDB Device Tree Source * * Copyright 2013 - 2015 Freescale Semiconductor Inc. - * Copyright 2019 NXP + * Copyright 2019-2021 NXP */ /include/ "t4240.dtsi" @@ -20,6 +20,144 @@ }; }; +&soc { + fman@400000 { + ethernet@e0000 { + phy-handle = <&sgmiiphy21>; + phy-connection-type = "sgmii"; + }; + + ethernet@e2000 { + phy-handle = <&sgmiiphy22>; + phy-connection-type = "sgmii"; + }; + + ethernet@e4000 { + phy-handle = <&sgmiiphy23>; + phy-connection-type = "sgmii"; + }; + + ethernet@e6000 { + phy-handle = <&sgmiiphy24>; + phy-connection-type = "sgmii"; + }; + + ethernet@e8000 { + status = "disabled"; + }; + + ethernet@ea000 { + status = "disabled"; + }; + + ethernet@f0000 { + phy-handle = <&xfiphy1>; + phy-connection-type = "xgmii"; + }; + + ethernet@f2000 { + phy-handle = <&xfiphy2>; + phy-connection-type = "xgmii"; + }; + }; + + fman@500000 { + ethernet@e0000 { + phy-handle = <&sgmiiphy41>; + phy-connection-type = "sgmii"; + }; + + ethernet@e2000 { + phy-handle = <&sgmiiphy42>; + phy-connection-type = "sgmii"; + }; + + ethernet@e4000 { + phy-handle = <&sgmiiphy43>; + phy-connection-type = "sgmii"; + }; + + ethernet@e6000 { + phy-handle = <&sgmiiphy44>; + phy-connection-type = "sgmii"; + }; + + ethernet@e8000 { + status = "disabled"; + }; + + ethernet@ea000 { + status = "disabled"; + }; + + ethernet@f0000 { + phy-handle = <&xfiphy3>; + phy-connection-type = "xgmii"; + }; + + ethernet@f2000 { + phy-handle = <&xfiphy4>; + phy-connection-type = "xgmii"; + }; + + mdio@5fc000 { + sgmiiphy21: ethernet-phy@0 { + reg = <0x0>; + }; + + sgmiiphy22: ethernet-phy@1 { + reg = <0x1>; + }; + + sgmiiphy23: ethernet-phy@2 { + reg = <0x2>; + }; + + sgmiiphy24: ethernet-phy@3 { + reg = <0x3>; + }; + + sgmiiphy41: ethernet-phy@4 { + reg = <0x4>; + }; + + sgmiiphy42: ethernet-phy@5 { + reg = <0x5>; + }; + + sgmiiphy43: ethernet-phy@6 { + reg = <0x6>; + }; + + sgmiiphy44: ethernet-phy@7 { + reg = <0x7>; + }; + }; + + mdio@5fd000 { + xfiphy1: ethernet-phy@10 { + compatible = "ethernet-phy-id13e5.1002"; + reg = <0x10>; + }; + + xfiphy2: ethernet-phy@11 { + compatible = "ethernet-phy-id13e5.1002"; + reg = <0x11>; + }; + + xfiphy3: ethernet-phy@13 { + compatible = "ethernet-phy-id13e5.1002"; + reg = <0x13>; + }; + + xfiphy4: ethernet-phy@12 { + compatible = "ethernet-phy-id13e5.1002"; + reg = <0x12>; + }; + }; + }; +}; + &espi0 { status = "okay"; flash@0 { @@ -30,3 +168,5 @@ spi-max-frequency = <10000000>; /* input clock */ }; }; + +/include/ "t4240si-post.dtsi" diff --git a/arch/powerpc/dts/t4240si-post.dtsi b/arch/powerpc/dts/t4240si-post.dtsi new file mode 100644 index 00000000000..a596f48b54f --- /dev/null +++ b/arch/powerpc/dts/t4240si-post.dtsi @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * T4240 Silicon/SoC Device Tree Source (post include) + * + * Copyright 2012 - 2015 Freescale Semiconductor Inc. + * Copyright 2021 NXP + * + */ +&soc { +/include/ "qoriq-clockgen2.dtsi" +/include/ "qoriq-gpio-0.dtsi" +/include/ "qoriq-gpio-1.dtsi" +/include/ "qoriq-gpio-2.dtsi" +/include/ "qoriq-gpio-3.dtsi" + +/include/ "qoriq-fman3-0.dtsi" +/include/ "qoriq-fman3-0-1g-0.dtsi" +/include/ "qoriq-fman3-0-1g-1.dtsi" +/include/ "qoriq-fman3-0-1g-2.dtsi" +/include/ "qoriq-fman3-0-1g-3.dtsi" +/include/ "qoriq-fman3-0-1g-4.dtsi" +/include/ "qoriq-fman3-0-1g-5.dtsi" +/include/ "qoriq-fman3-0-10g-0.dtsi" +/include/ "qoriq-fman3-0-10g-1.dtsi" + fman@400000 { + enet0: ethernet@e0000 { + }; + + enet1: ethernet@e2000 { + }; + + enet2: ethernet@e4000 { + }; + + enet3: ethernet@e6000 { + }; + + enet4: ethernet@e8000 { + }; + + enet5: ethernet@ea000 { + }; + + enet6: ethernet@f0000 { + }; + + enet7: ethernet@f2000 { + }; + + mdio@fc000 { + status = "disabled"; + }; + + mdio@fd000 { + status = "disabled"; + }; + }; + +/include/ "qoriq-fman3-1.dtsi" +/include/ "qoriq-fman3-1-1g-0.dtsi" +/include/ "qoriq-fman3-1-1g-1.dtsi" +/include/ "qoriq-fman3-1-1g-2.dtsi" +/include/ "qoriq-fman3-1-1g-3.dtsi" +/include/ "qoriq-fman3-1-1g-4.dtsi" +/include/ "qoriq-fman3-1-1g-5.dtsi" +/include/ "qoriq-fman3-1-10g-0.dtsi" +/include/ "qoriq-fman3-1-10g-1.dtsi" + fman@500000 { + enet8: ethernet@e0000 { + }; + + enet9: ethernet@e2000 { + }; + + enet10: ethernet@e4000 { + }; + + enet11: ethernet@e6000 { + }; + + enet12: ethernet@e8000 { + }; + + enet13: ethernet@ea000 { + }; + + enet14: ethernet@f0000 { + }; + + enet15: ethernet@f2000 { + }; + + mdio@5fc000 { + interrupts = <100 1 0 0>; + }; + + mdio@5fd000 { + interrupts = <101 1 0 0>; + }; + }; +}; diff --git a/arch/sandbox/dts/test.dts b/arch/sandbox/dts/test.dts index 8c4c2bfddd9..dde4efb9334 100644 --- a/arch/sandbox/dts/test.dts +++ b/arch/sandbox/dts/test.dts @@ -15,7 +15,9 @@ aliases { console = &uart0; eth0 = "/eth@10002000"; + eth2 = &swp_0; eth3 = ð_3; + eth4 = &dsa_eth0; eth5 = ð_5; gpio1 = &gpio_a; gpio2 = &gpio_b; @@ -478,6 +480,48 @@ fake-host-hwaddr = [00 00 66 44 22 22]; }; + dsa_eth0: dsa-test-eth { + compatible = "sandbox,eth"; + reg = <0x10006000 0x1000>; + fake-host-hwaddr = [00 00 66 44 22 66]; + }; + + dsa-test { + compatible = "sandbox,dsa"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + swp_0: port@0 { + reg = <0>; + label = "lan0"; + phy-mode = "rgmii-rxid"; + + fixed-link { + speed = <100>; + full-duplex; + }; + }; + + swp_1: port@1 { + reg = <1>; + label = "lan1"; + phy-mode = "rgmii-txid"; + fixed-link = <0 1 100 0 0>; + }; + + port@2 { + reg = <2>; + ethernet = <&dsa_eth0>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + firmware { sandbox_firmware: sandbox-firmware { compatible = "sandbox,firmware"; |