diff options
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/riscv/cpu/andesv5/Kconfig | 1 | ||||
| -rw-r--r-- | arch/riscv/cpu/fu540/spl.c | 2 | ||||
| -rw-r--r-- | arch/riscv/cpu/fu740/spl.c | 2 | ||||
| -rw-r--r-- | arch/riscv/cpu/jh7110/spl.c | 2 | ||||
| -rw-r--r-- | arch/riscv/dts/cv1800b-milkv-duo.dts | 18 | ||||
| -rw-r--r-- | arch/riscv/dts/cv18xx.dtsi | 40 | ||||
| -rw-r--r-- | arch/riscv/include/asm/arch-fu540/spl.h | 2 | ||||
| -rw-r--r-- | arch/riscv/include/asm/arch-fu740/spl.h | 2 | ||||
| -rw-r--r-- | arch/riscv/include/asm/arch-jh7110/spl.h | 2 | ||||
| -rw-r--r-- | arch/riscv/include/asm/sbi.h | 1 |
10 files changed, 66 insertions, 6 deletions
diff --git a/arch/riscv/cpu/andesv5/Kconfig b/arch/riscv/cpu/andesv5/Kconfig index f311291aedb..e3efb0de8f0 100644 --- a/arch/riscv/cpu/andesv5/Kconfig +++ b/arch/riscv/cpu/andesv5/Kconfig @@ -1,6 +1,7 @@ config RISCV_NDS bool select ARCH_EARLY_INIT_R + select SYS_CACHE_SHIFT_6 imply CPU imply CPU_RISCV imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE) diff --git a/arch/riscv/cpu/fu540/spl.c b/arch/riscv/cpu/fu540/spl.c index 45657b79096..cedb70b66a2 100644 --- a/arch/riscv/cpu/fu540/spl.c +++ b/arch/riscv/cpu/fu540/spl.c @@ -7,7 +7,7 @@ #include <dm.h> #include <log.h> -int spl_soc_init(void) +int spl_dram_init(void) { int ret; struct udevice *dev; diff --git a/arch/riscv/cpu/fu740/spl.c b/arch/riscv/cpu/fu740/spl.c index c6816e9ed4c..16b307f0361 100644 --- a/arch/riscv/cpu/fu740/spl.c +++ b/arch/riscv/cpu/fu740/spl.c @@ -10,7 +10,7 @@ #define CSR_U74_FEATURE_DISABLE 0x7c1 -int spl_soc_init(void) +int spl_dram_init(void) { int ret; struct udevice *dev; diff --git a/arch/riscv/cpu/jh7110/spl.c b/arch/riscv/cpu/jh7110/spl.c index 6bdf8b9c72f..87aaf865246 100644 --- a/arch/riscv/cpu/jh7110/spl.c +++ b/arch/riscv/cpu/jh7110/spl.c @@ -28,7 +28,7 @@ static bool check_ddr_size(phys_size_t size) } } -int spl_soc_init(void) +int spl_dram_init(void) { int ret; struct udevice *dev; diff --git a/arch/riscv/dts/cv1800b-milkv-duo.dts b/arch/riscv/dts/cv1800b-milkv-duo.dts index 94e64ddce8f..e7cc0e8bd14 100644 --- a/arch/riscv/dts/cv1800b-milkv-duo.dts +++ b/arch/riscv/dts/cv1800b-milkv-duo.dts @@ -29,6 +29,11 @@ }; }; +ðernet0 { + status = "okay"; + phy-mode = "rmii"; +}; + &osc { clock-frequency = <25000000>; }; @@ -41,6 +46,19 @@ no-sdio; }; +&spif { + status = "okay"; + + spiflash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <75000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + m25p,fast-read; + }; +}; + &uart0 { status = "okay"; }; diff --git a/arch/riscv/dts/cv18xx.dtsi b/arch/riscv/dts/cv18xx.dtsi index ec99c4deeb6..4b0143450e8 100644 --- a/arch/riscv/dts/cv18xx.dtsi +++ b/arch/riscv/dts/cv18xx.dtsi @@ -52,6 +52,27 @@ #clock-cells = <0>; }; + eth_csrclk: eth-csrclk { + compatible = "fixed-clock"; + clock-frequency = <250000000>; + clock-output-names = "eth_csrclk"; + #clock-cells = <0x0>; + }; + + eth_ptpclk: eth-ptpclk { + compatible = "fixed-clock"; + clock-frequency = <50000000>; + clock-output-names = "eth_ptpclk"; + #clock-cells = <0x0>; + }; + + spif_clk: spi-flash-clock { + compatible = "fixed-clock"; + clock-frequency = <300000000>; + clock-output-names = "spif_clk"; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&plic>; @@ -138,6 +159,15 @@ }; }; + ethernet0: ethernet@4070000 { + compatible = "sophgo,cv1800b-dwmac"; + reg = <0x04070000 0x10000>; + interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; + clocks = <ð_csrclk>, <ð_ptpclk>; + clock-names = "stmmaceth", "ptp_ref"; + status = "disabled"; + }; + uart0: serial@4140000 { compatible = "snps,dw-apb-uart"; reg = <0x04140000 0x100>; @@ -197,6 +227,16 @@ status = "disabled"; }; + spif: spi-nor@10000000 { + compatible = "sophgo,cv1800b-spif"; + reg = <0x10000000 0x10000000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&spif_clk>; + interrupts = <95 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; + plic: interrupt-controller@70000000 { reg = <0x70000000 0x4000000>; interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; diff --git a/arch/riscv/include/asm/arch-fu540/spl.h b/arch/riscv/include/asm/arch-fu540/spl.h index 4697279f438..519e7eb210f 100644 --- a/arch/riscv/include/asm/arch-fu540/spl.h +++ b/arch/riscv/include/asm/arch-fu540/spl.h @@ -9,6 +9,6 @@ #ifndef _SPL_SIFIVE_H #define _SPL_SIFIVE_H -int spl_soc_init(void); +int spl_dram_init(void); #endif /* _SPL_SIFIVE_H */ diff --git a/arch/riscv/include/asm/arch-fu740/spl.h b/arch/riscv/include/asm/arch-fu740/spl.h index 15ad9e7c8b7..b327ac50361 100644 --- a/arch/riscv/include/asm/arch-fu740/spl.h +++ b/arch/riscv/include/asm/arch-fu740/spl.h @@ -9,6 +9,6 @@ #ifndef _SPL_SIFIVE_H #define _SPL_SIFIVE_H -int spl_soc_init(void); +int spl_dram_init(void); #endif /* _SPL_SIFIVE_H */ diff --git a/arch/riscv/include/asm/arch-jh7110/spl.h b/arch/riscv/include/asm/arch-jh7110/spl.h index 23ce8871b3a..d73355bf35d 100644 --- a/arch/riscv/include/asm/arch-jh7110/spl.h +++ b/arch/riscv/include/asm/arch-jh7110/spl.h @@ -7,6 +7,6 @@ #ifndef _SPL_STARFIVE_H #define _SPL_STARFIVE_H -int spl_soc_init(void); +int spl_dram_init(void); #endif /* _SPL_STARFIVE_H */ diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index d1113f3d703..ad32dedb589 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -34,6 +34,7 @@ enum sbi_ext_id { SBI_EXT_NACL = 0x4E41434C, SBI_EXT_STA = 0x535441, SBI_EXT_DBTR = 0x44425452, + SBI_EXT_SSE = 0x535345, }; enum sbi_ext_base_fid { |