diff options
Diffstat (limited to 'arch')
61 files changed, 148 insertions, 148 deletions
diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c index 4c696cb53a4..d97a5787424 100644 --- a/arch/arc/lib/cache.c +++ b/arch/arc/lib/cache.c @@ -476,9 +476,9 @@ static void __slc_rgn_op(unsigned long paddr, unsigned long sz, const int op) static void arc_ioc_setup(void) { /* IOC Aperture start is equal to DDR start */ - unsigned int ap_base = CONFIG_SYS_SDRAM_BASE; + unsigned int ap_base = CFG_SYS_SDRAM_BASE; /* IOC Aperture size is equal to DDR size */ - long ap_size = CONFIG_SYS_SDRAM_SIZE; + long ap_size = CFG_SYS_SDRAM_SIZE; /* Unsupported configuration. See [ NOTE 2 ] for more details. */ if (!slc_exists()) diff --git a/arch/arc/lib/cpu.c b/arch/arc/lib/cpu.c index 6b215206a27..15678579618 100644 --- a/arch/arc/lib/cpu.c +++ b/arch/arc/lib/cpu.c @@ -20,7 +20,7 @@ int arch_cpu_init(void) timer_init(); gd->cpu_clk = get_board_sys_clk(); - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; cache_init(); diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c index b4d113dc1e0..954fa5f8b45 100644 --- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c @@ -29,7 +29,7 @@ */ static void __secure ls1_save_ddr_head(void) { - const char *src = (const char *)CONFIG_SYS_SDRAM_BASE; + const char *src = (const char *)CFG_SYS_SDRAM_BASE; char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN); struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR; int i; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index ef71e2cf2bc..bbaa91f0e10 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -1441,7 +1441,7 @@ int dram_init_banksize(void) } #endif - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; if (gd->ram_size > CONFIG_SYS_DDR_BLOCK1_SIZE) { gd->bd->bi_dram[0].size = CONFIG_SYS_DDR_BLOCK1_SIZE; gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE; @@ -1571,7 +1571,7 @@ void update_early_mmu_table(void) if (gd->ram_size <= CONFIG_SYS_FSL_DRAM_SIZE1) { mmu_change_region_attr( - CONFIG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_BASE, gd->ram_size, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | @@ -1579,7 +1579,7 @@ void update_early_mmu_table(void) PTE_TYPE_VALID); } else { mmu_change_region_attr( - CONFIG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_BASE, CONFIG_SYS_DDR_BLOCK1_SIZE, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | diff --git a/arch/arm/dts/rockchip-optee.dtsi b/arch/arm/dts/rockchip-optee.dtsi index 328ba908450..d84c10cf436 100644 --- a/arch/arm/dts/rockchip-optee.dtsi +++ b/arch/arm/dts/rockchip-optee.dtsi @@ -32,8 +32,8 @@ arch = "arm"; os = "tee"; compression = "none"; - load = <(CONFIG_SYS_SDRAM_BASE + 0x8400000)>; - entry = <(CONFIG_SYS_SDRAM_BASE + 0x8400000)>; + load = <(CFG_SYS_SDRAM_BASE + 0x8400000)>; + entry = <(CFG_SYS_SDRAM_BASE + 0x8400000)>; blob-ext { filename = "tee.bin"; diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 35424345bf0..2141a4581c7 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -583,7 +583,7 @@ (DMM_SDRC_MAP_EMIF1_AND_EMIF2 << EMIF_SDRC_MAP_SHIFT) |\ (DMM_SDRC_ADDR_SPC_SDRAM << EMIF_SDRC_ADDRSPC_SHIFT) |\ (DMM_SDRC_INTL_128B << EMIF_SDRC_INTL_SHIFT) |\ - (CONFIG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT)) + (CFG_SYS_SDRAM_BASE << EMIF_SYS_ADDR_SHIFT)) #define DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL (\ (DMM_SDRC_MAP_EMIF1_ONLY << EMIF_SDRC_MAP_SHIFT)|\ diff --git a/arch/arm/include/asm/iproc-common/configs.h b/arch/arm/include/asm/iproc-common/configs.h index 4733c0793c3..c63c27dac7e 100644 --- a/arch/arm/include/asm/iproc-common/configs.h +++ b/arch/arm/include/asm/iproc-common/configs.h @@ -12,6 +12,6 @@ #define CONFIG_IPROC /* Memory Info */ -#define CONFIG_SYS_SDRAM_BASE 0x61000000 +#define CFG_SYS_SDRAM_BASE 0x61000000 #endif /* __IPROC_COMMON_CONFIGS_H */ diff --git a/arch/arm/mach-aspeed/ast2500/board_common.c b/arch/arm/mach-aspeed/ast2500/board_common.c index aca20022312..bae10271844 100644 --- a/arch/arm/mach-aspeed/ast2500/board_common.c +++ b/arch/arm/mach-aspeed/ast2500/board_common.c @@ -31,7 +31,7 @@ DECLARE_GLOBAL_DATA_PTR; int board_init(void) { - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/arch/arm/mach-aspeed/ast2600/board_common.c b/arch/arm/mach-aspeed/ast2600/board_common.c index 82ff21908f2..dc6cdc35d15 100644 --- a/arch/arm/mach-aspeed/ast2600/board_common.c +++ b/arch/arm/mach-aspeed/ast2600/board_common.c @@ -54,7 +54,7 @@ int board_init(void) int i = 0, rc; struct udevice *dev; - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; while (1) { rc = uclass_get_device(UCLASS_MISC, i++, &dev); diff --git a/arch/arm/mach-at91/arm920t/lowlevel_init.S b/arch/arm/mach-at91/arm920t/lowlevel_init.S index 57e51c81059..3b91a0cba33 100644 --- a/arch/arm/mach-at91/arm920t/lowlevel_init.S +++ b/arch/arm/mach-at91/arm920t/lowlevel_init.S @@ -114,38 +114,38 @@ SMRDATA1: .word CONFIG_SYS_SDRC_CR_VAL .word AT91_ASM_MC_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL .word AT91_ASM_MC_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL1 - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL .word AT91_ASM_MC_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL2 - .word CONFIG_SYS_SDRAM1 - .word CONFIG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM1 + .word CFG_SYS_SDRAM_VAL .word AT91_ASM_MC_SDRAMC_TR .word CONFIG_SYS_SDRC_TR_VAL - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL .word AT91_ASM_MC_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL3 - .word CONFIG_SYS_SDRAM - .word CONFIG_SYS_SDRAM_VAL + .word CFG_SYS_SDRAM + .word CFG_SYS_SDRAM_VAL SMRDATA1E: /* SMRDATA1 is 176 bytes long */ #endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */ diff --git a/arch/arm/mach-at91/arm926ejs/lowlevel_init.S b/arch/arm/mach-at91/arm926ejs/lowlevel_init.S index c51eee2f17e..ecfe589e455 100644 --- a/arch/arm/mach-at91/arm926ejs/lowlevel_init.S +++ b/arch/arm/mach-at91/arm926ejs/lowlevel_init.S @@ -201,38 +201,38 @@ SMRDATA1: .word CONFIG_SYS_SDRC_MDR_VAL .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL2 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL1 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL1 .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL3 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL2 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL3 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL4 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL5 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL6 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL7 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL8 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL9 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL2 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL3 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL4 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL5 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL6 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL7 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL8 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL9 .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL4 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL10 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL10 .word AT91_ASM_SDRAMC_MR .word CONFIG_SYS_SDRC_MR_VAL5 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL11 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL11 .word AT91_ASM_SDRAMC_TR .word CONFIG_SYS_SDRC_TR_VAL2 - .word CONFIG_SYS_SDRAM_BASE - .word CONFIG_SYS_SDRAM_VAL12 + .word CFG_SYS_SDRAM_BASE + .word CFG_SYS_SDRAM_VAL12 /* User reset enable*/ .word AT91_ASM_RSTC_MR .word CONFIG_SYS_RSTC_RMR_VAL diff --git a/arch/arm/mach-davinci/misc.c b/arch/arm/mach-davinci/misc.c index 73fdd1f2432..42078b39f8a 100644 --- a/arch/arm/mach-davinci/misc.c +++ b/arch/arm/mach-davinci/misc.c @@ -26,14 +26,14 @@ int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, + (void *)CFG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); return 0; } int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size; return 0; diff --git a/arch/arm/mach-exynos/dmc_init_ddr3.c b/arch/arm/mach-exynos/dmc_init_ddr3.c index fa867f27f30..cad8ccc5315 100644 --- a/arch/arm/mach-exynos/dmc_init_ddr3.c +++ b/arch/arm/mach-exynos/dmc_init_ddr3.c @@ -236,7 +236,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) * better have similar timings, since there's only a single adjustment that is * shared by both chips). */ -const unsigned int test_addr = CONFIG_SYS_SDRAM_BASE; +const unsigned int test_addr = CFG_SYS_SDRAM_BASE; /* Test pattern with which RAM will be tested */ static const unsigned int test_pattern[] = { diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index a4863281e36..8050406613d 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -178,7 +178,7 @@ static unsigned int imx8m_find_dram_entry_in_mem_map(void) int i; for (i = 0; i < ARRAY_SIZE(imx8m_mem_map); i++) - if (imx8m_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE) + if (imx8m_mem_map[i].phys == CFG_SYS_SDRAM_BASE) return i; hang(); /* Entry not found, this must never happen. */ diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index 802cb0e2ba8..5d95fb89a61 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -373,7 +373,7 @@ static unsigned int imx8ulp_find_dram_entry_in_mem_map(void) int i; for (i = 0; i < ARRAY_SIZE(imx8ulp_arm64_mem_map); i++) - if (imx8ulp_arm64_mem_map[i].phys == CONFIG_SYS_SDRAM_BASE) + if (imx8ulp_arm64_mem_map[i].phys == CFG_SYS_SDRAM_BASE) return i; hang(); /* Entry not found, this must never happen. */ diff --git a/arch/arm/mach-imx/mx6/litesom.c b/arch/arm/mach-imx/mx6/litesom.c index 699a3dc317f..2ba3245e226 100644 --- a/arch/arm/mach-imx/mx6/litesom.c +++ b/arch/arm/mach-imx/mx6/litesom.c @@ -172,7 +172,7 @@ static void spl_dram_init(void) * Get actual RAM size, so we can adjust DDR row size for <512M * memories */ - ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_512M); + ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_512M); if (ram_size < SZ_512M) { mem_ddr.rowaddr = 14; mx6_dram_cfg(&ddr_sysinfo, &mx6_mmcd_calib, &mem_ddr); diff --git a/arch/arm/mach-imx/mx6/opos6ul.c b/arch/arm/mach-imx/mx6/opos6ul.c index e9d78740a15..38ead8ace20 100644 --- a/arch/arm/mach-imx/mx6/opos6ul.c +++ b/arch/arm/mach-imx/mx6/opos6ul.c @@ -44,7 +44,7 @@ static int setup_fec(void) int board_init(void) { /* Address of boot parameters */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; #ifdef CONFIG_FEC_MXC setup_fec(); diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c index 6b8f4115c4e..cb9801b7a13 100644 --- a/arch/arm/mach-imx/spl.c +++ b/arch/arm/mach-imx/spl.c @@ -349,7 +349,7 @@ void *board_spl_fit_buffer_addr(ulong fit_size, int sectors, int bl_len) #if defined(CONFIG_MX6) && defined(CONFIG_SPL_OS_BOOT) int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = imx_ddr_size(); return 0; diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 227706e8dca..d5e1f8e2e78 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -561,7 +561,7 @@ void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size) void spl_enable_dcache(void) { #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) - phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE; + phys_addr_t ram_top = CFG_SYS_SDRAM_BASE; dram_init(); diff --git a/arch/arm/mach-k3/r5_mpu.c b/arch/arm/mach-k3/r5_mpu.c index 3d2ff6775a3..2aec96277e6 100644 --- a/arch/arm/mach-k3/r5_mpu.c +++ b/arch/arm/mach-k3/r5_mpu.c @@ -24,7 +24,7 @@ struct mpu_region_config k3_mpu_regions[16] = { O_I_WB_RD_WR_ALLOC, REGION_8MB}, /* U-Boot's code area marking it as WB and Write allocate */ - {CONFIG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW, + {CFG_SYS_SDRAM_BASE, REGION_2, XN_DIS, PRIV_RW_USR_RW, O_I_WB_RD_WR_ALLOC, REGION_2GB}, /* mcu_r5fss0_core0 BTCM area marking it as WB and Write allocate. */ {0x41010000, 3, XN_DIS, PRIV_RW_USR_RW, O_I_WB_RD_WR_ALLOC, diff --git a/arch/arm/mach-keystone/ddr3.c b/arch/arm/mach-keystone/ddr3.c index 53117c2695c..ea7d0b903cf 100644 --- a/arch/arm/mach-keystone/ddr3.c +++ b/arch/arm/mach-keystone/ddr3.c @@ -318,7 +318,7 @@ void ddr3_init_ecc(u32 base, u32 ddr3_size) } ddr3_ecc_init_range(base); - ddr3_reset_data(CONFIG_SYS_SDRAM_BASE, ddr3_size); + ddr3_reset_data(CFG_SYS_SDRAM_BASE, ddr3_size); /* mapping DDR3 ECC system interrupt from CIC2 to GIC */ #if defined(CONFIG_SOC_K2HK) || defined(CONFIG_SOC_K2L) diff --git a/arch/arm/mach-mediatek/mt7623/init.c b/arch/arm/mach-mediatek/mt7623/init.c index 5d837e05971..988b057e598 100644 --- a/arch/arm/mach-mediatek/mt7623/init.c +++ b/arch/arm/mach-mediatek/mt7623/init.c @@ -25,7 +25,7 @@ int dram_init(void) { u32 i; - if (((size_t)preloader_param >= CONFIG_SYS_SDRAM_BASE) && + if (((size_t)preloader_param >= CFG_SYS_SDRAM_BASE) && ((size_t)preloader_param % sizeof(size_t) == 0) && preloader_param->magic == BOOT_ARGUMENT_MAGIC && preloader_param->dram_rank_num <= @@ -35,7 +35,7 @@ int dram_init(void) for (i = 0; i < preloader_param->dram_rank_num; i++) gd->ram_size += preloader_param->dram_rank_size[i]; } else { - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, SZ_2G); } diff --git a/arch/arm/mach-mediatek/mt7981/init.c b/arch/arm/mach-mediatek/mt7981/init.c index a8955064e03..d8b10f03580 100644 --- a/arch/arm/mach-mediatek/mt7981/init.c +++ b/arch/arm/mach-mediatek/mt7981/init.c @@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G); return 0; } diff --git a/arch/arm/mach-mediatek/mt7986/init.c b/arch/arm/mach-mediatek/mt7986/init.c index cf89e63e80a..fb74b2f34d7 100644 --- a/arch/arm/mach-mediatek/mt7986/init.c +++ b/arch/arm/mach-mediatek/mt7986/init.c @@ -14,7 +14,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, SZ_2G); + gd->ram_size = get_ram_size((void *)CFG_SYS_SDRAM_BASE, SZ_2G); return 0; } diff --git a/arch/arm/mach-mvebu/alleycat5/cpu.c b/arch/arm/mach-mvebu/alleycat5/cpu.c index cc7f9794c54..8204d962751 100644 --- a/arch/arm/mach-mvebu/alleycat5/cpu.c +++ b/arch/arm/mach-mvebu/alleycat5/cpu.c @@ -21,8 +21,8 @@ DECLARE_GLOBAL_DATA_PTR; static struct mm_region ac5_mem_map[] = { { /* RAM */ - .phys = CONFIG_SYS_SDRAM_BASE, - .virt = CONFIG_SYS_SDRAM_BASE, + .phys = CFG_SYS_SDRAM_BASE, + .virt = CFG_SYS_SDRAM_BASE, .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE }, @@ -102,7 +102,7 @@ int alleycat5_dram_init_banksize(void) /* * Config single DRAM bank */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size; return 0; diff --git a/arch/arm/mach-mvebu/arm64-common.c b/arch/arm/mach-mvebu/arm64-common.c index e3098a7ca87..2c94f899f37 100644 --- a/arch/arm/mach-mvebu/arm64-common.c +++ b/arch/arm/mach-mvebu/arm64-common.c @@ -32,7 +32,7 @@ DECLARE_GLOBAL_DATA_PTR; phys_size_t board_get_usable_ram_top(phys_size_t total_size) { - unsigned long top = CONFIG_SYS_SDRAM_BASE + min(gd->ram_size, USABLE_RAM_SIZE); + unsigned long top = CFG_SYS_SDRAM_BASE + min(gd->ram_size, USABLE_RAM_SIZE); return (gd->ram_top > top) ? top : gd->ram_top; } diff --git a/arch/arm/mach-mvebu/armada8k/dram.c b/arch/arm/mach-mvebu/armada8k/dram.c index bab375e18ac..6c801bfa1db 100644 --- a/arch/arm/mach-mvebu/armada8k/dram.c +++ b/arch/arm/mach-mvebu/armada8k/dram.c @@ -38,7 +38,7 @@ int a8k_dram_init_banksize(void) */ phys_size_t max_bank0_size = SZ_4G - SZ_1G; - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; if (gd->ram_size <= max_bank0_size) { gd->bd->bi_dram[0].size = gd->ram_size; return 0; diff --git a/arch/arm/mach-omap2/am33xx/board.c b/arch/arm/mach-omap2/am33xx/board.c index 44d5214a3df..86755d6d954 100644 --- a/arch/arm/mach-omap2/am33xx/board.c +++ b/arch/arm/mach-omap2/am33xx/board.c @@ -72,14 +72,14 @@ int dram_init(void) /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, + (void *)CFG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); return 0; } int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size; return 0; @@ -520,7 +520,7 @@ void board_init_f(ulong dummy) sdram_init(); /* dram_init must store complete ramsize in gd->ram_size */ gd->ram_size = get_ram_size( - (void *)CONFIG_SYS_SDRAM_BASE, + (void *)CFG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); } #endif diff --git a/arch/arm/mach-omap2/emif-common.c b/arch/arm/mach-omap2/emif-common.c index 312f868fbc7..a6a97af37d7 100644 --- a/arch/arm/mach-omap2/emif-common.c +++ b/arch/arm/mach-omap2/emif-common.c @@ -389,7 +389,7 @@ static void dra7_enable_ecc(u32 base, const struct emif_regs *regs) /* Set region1 memory with 0 */ rgn_start = (regs->emif_ecc_address_range_1 & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16; - rgn = rgn_start + CONFIG_SYS_SDRAM_BASE; + rgn = rgn_start + CFG_SYS_SDRAM_BASE; size = (regs->emif_ecc_address_range_1 & EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start; @@ -400,7 +400,7 @@ static void dra7_enable_ecc(u32 base, const struct emif_regs *regs) /* Set region2 memory with 0 */ rgn_start = (regs->emif_ecc_address_range_2 & EMIF_ECC_REG_ECC_START_ADDR_MASK) << 16; - rgn = rgn_start + CONFIG_SYS_SDRAM_BASE; + rgn = rgn_start + CFG_SYS_SDRAM_BASE; size = (regs->emif_ecc_address_range_2 & EMIF_ECC_REG_ECC_END_ADDR_MASK) + 0x10000 - rgn_start; @@ -1340,7 +1340,7 @@ void dmm_init(u32 base) mapped_size = 0; section_cnt = 3; - sys_addr = CONFIG_SYS_SDRAM_BASE; + sys_addr = CFG_SYS_SDRAM_BASE; emif1_size = get_emif_mem_size(EMIF1_BASE); emif2_size = get_emif_mem_size(EMIF2_BASE); debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size); @@ -1568,7 +1568,7 @@ void sdram_init(void) size_prog = log_2_n_round_down(size_prog); size_prog = (1 << size_prog); - size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + size_detect = get_ram_size((long *)CFG_SYS_SDRAM_BASE, size_prog); /* Compare with the size programmed */ if (size_detect != size_prog) { diff --git a/arch/arm/mach-omap2/sec-common.c b/arch/arm/mach-omap2/sec-common.c index 0551bc125e8..0f9b915ea3d 100644 --- a/arch/arm/mach-omap2/sec-common.c +++ b/arch/arm/mach-omap2/sec-common.c @@ -198,11 +198,11 @@ u32 get_sec_mem_start(void) */ if (sec_mem_start == 0) sec_mem_start = - (CONFIG_SYS_SDRAM_BASE + ( + (CFG_SYS_SDRAM_BASE + ( #if defined(CONFIG_OMAP54XX) omap_sdram_size() #else - get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + get_ram_size((void *)CFG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE) #endif - sec_mem_size)); diff --git a/arch/arm/mach-owl/soc.c b/arch/arm/mach-owl/soc.c index 4baef2eed3e..f0f46f2dcb7 100644 --- a/arch/arm/mach-owl/soc.c +++ b/arch/arm/mach-owl/soc.c @@ -50,7 +50,7 @@ int dram_init(void) /* This is called after dram_init() so use get_ram_size result */ int dram_init_banksize(void) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = gd->ram_size; return 0; diff --git a/arch/arm/mach-rockchip/sdram.c b/arch/arm/mach-rockchip/sdram.c index 12f1d7ee563..e086c47f3c0 100644 --- a/arch/arm/mach-rockchip/sdram.c +++ b/arch/arm/mach-rockchip/sdram.c @@ -37,7 +37,7 @@ struct tos_parameter_t { int dram_init_banksize(void) { - size_t top = min((unsigned long)(gd->ram_size + CONFIG_SYS_SDRAM_BASE), + size_t top = min((unsigned long)(gd->ram_size + CFG_SYS_SDRAM_BASE), (unsigned long)(gd->ram_top)); #ifdef CONFIG_ARM64 @@ -48,26 +48,26 @@ int dram_init_banksize(void) #ifdef CONFIG_SPL_OPTEE_IMAGE struct tos_parameter_t *tos_parameter; - tos_parameter = (struct tos_parameter_t *)(CONFIG_SYS_SDRAM_BASE + + tos_parameter = (struct tos_parameter_t *)(CFG_SYS_SDRAM_BASE + TRUST_PARAMETER_OFFSET); if (tos_parameter->tee_mem.flags == 1) { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = tos_parameter->tee_mem.phy_addr - - CONFIG_SYS_SDRAM_BASE; + - CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[1].start = tos_parameter->tee_mem.phy_addr + tos_parameter->tee_mem.size; gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start; } else { - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = 0x8400000; /* Reserve 32M for OPTEE with TA */ - gd->bd->bi_dram[1].start = CONFIG_SYS_SDRAM_BASE + gd->bd->bi_dram[1].start = CFG_SYS_SDRAM_BASE + gd->bd->bi_dram[0].size + 0x2000000; gd->bd->bi_dram[1].size = top - gd->bd->bi_dram[1].start; } #else - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = top - gd->bd->bi_dram[0].start; #endif #endif @@ -207,7 +207,7 @@ int dram_init(void) phys_size_t board_get_usable_ram_top(phys_size_t total_size) { - unsigned long top = CONFIG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE; + unsigned long top = CFG_SYS_SDRAM_BASE + SDRAM_MAX_SIZE; return (gd->ram_top > top) ? top : gd->ram_top; } diff --git a/arch/arm/mach-socfpga/board.c b/arch/arm/mach-socfpga/board.c index b49006c6c8a..09e09192fba 100644 --- a/arch/arm/mach-socfpga/board.c +++ b/arch/arm/mach-socfpga/board.c @@ -46,7 +46,7 @@ void s_init(void) { int board_init(void) { /* Address of boot parameters for ATAG (if ATAG is used) */ - gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + gd->bd->bi_boot_params = CFG_SYS_SDRAM_BASE + 0x100; return 0; } diff --git a/arch/arm/mach-sunxi/dram_helpers.c b/arch/arm/mach-sunxi/dram_helpers.c index 2c873192e60..cdf2750f1c5 100644 --- a/arch/arm/mach-sunxi/dram_helpers.c +++ b/arch/arm/mach-sunxi/dram_helpers.c @@ -33,11 +33,11 @@ void mctl_await_completion(u32 *reg, u32 mask, u32 val) bool mctl_mem_matches(u32 offset) { /* Try to write different values to RAM at two addresses */ - writel(0, CONFIG_SYS_SDRAM_BASE); - writel(0xaa55aa55, (ulong)CONFIG_SYS_SDRAM_BASE + offset); + writel(0, CFG_SYS_SDRAM_BASE); + writel(0xaa55aa55, (ulong)CFG_SYS_SDRAM_BASE + offset); dsb(); /* Check if the same value is actually observed when reading back */ - return readl(CONFIG_SYS_SDRAM_BASE) == - readl((ulong)CONFIG_SYS_SDRAM_BASE + offset); + return readl(CFG_SYS_SDRAM_BASE) == + readl((ulong)CFG_SYS_SDRAM_BASE + offset); } #endif diff --git a/arch/arm/mach-sunxi/dram_suniv.c b/arch/arm/mach-sunxi/dram_suniv.c index 56c2d557ff1..3aa3ce76272 100644 --- a/arch/arm/mach-sunxi/dram_suniv.c +++ b/arch/arm/mach-sunxi/dram_suniv.c @@ -175,9 +175,9 @@ static int sdr_readpipe_scan(void) u32 k = 0; for (k = 0; k < 32; k++) - writel(k, CONFIG_SYS_SDRAM_BASE + 4 * k); + writel(k, CFG_SYS_SDRAM_BASE + 4 * k); for (k = 0; k < 32; k++) { - if (readl(CONFIG_SYS_SDRAM_BASE + 4 * k) != k) + if (readl(CFG_SYS_SDRAM_BASE + 4 * k) != k) return 0; } return 1; @@ -266,11 +266,11 @@ static u32 dram_get_dram_size(struct dram_para *para) dram_para_setup(para); dram_scan_readpipe(para); for (i = 0; i < 32; i++) { - *((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x200 + i)) = 0x11; - *((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x600 + i)) = 0x22; + *((u8 *)(CFG_SYS_SDRAM_BASE + 0x200 + i)) = 0x11; + *((u8 *)(CFG_SYS_SDRAM_BASE + 0x600 + i)) = 0x22; } for (i = 0; i < 32; i++) { - val1 = *((u8 *)(CONFIG_SYS_SDRAM_BASE + 0x200 + i)); + val1 = *((u8 *)(CFG_SYS_SDRAM_BASE + 0x200 + i)); if (val1 == 0x22) count++; } @@ -283,11 +283,11 @@ static u32 dram_get_dram_size(struct dram_para *para) para->row_width = rowflag; dram_para_setup(para); if (colflag == 10) { - addr1 = CONFIG_SYS_SDRAM_BASE + 0x400000; - addr2 = CONFIG_SYS_SDRAM_BASE + 0xc00000; + addr1 = CFG_SYS_SDRAM_BASE + 0x400000; + addr2 = CFG_SYS_SDRAM_BASE + 0xc00000; } else { - addr1 = CONFIG_SYS_SDRAM_BASE + 0x200000; - addr2 = CONFIG_SYS_SDRAM_BASE + 0x600000; + addr1 = CFG_SYS_SDRAM_BASE + 0x200000; + addr2 = CFG_SYS_SDRAM_BASE + 0x600000; } for (i = 0; i < 32; i++) { *((u8 *)(addr1 + i)) = 0x33; @@ -319,7 +319,7 @@ static u32 dram_get_dram_size(struct dram_para *para) static void simple_dram_check(void) { - volatile u32 *dram = (u32 *)CONFIG_SYS_SDRAM_BASE; + volatile u32 *dram = (u32 *)CFG_SYS_SDRAM_BASE; int i; for (i = 0; i < 0x40; i++) diff --git a/arch/arm/mach-sunxi/dram_sunxi_dw.c b/arch/arm/mach-sunxi/dram_sunxi_dw.c index 9107b114df5..4af5922f334 100644 --- a/arch/arm/mach-sunxi/dram_sunxi_dw.c +++ b/arch/arm/mach-sunxi/dram_sunxi_dw.c @@ -711,7 +711,7 @@ static unsigned long mctl_calc_rank_size(struct rank_para *rank) */ static void mctl_r40_detect_rank_count(struct dram_para *para) { - ulong rank1_base = (ulong) CONFIG_SYS_SDRAM_BASE + + ulong rank1_base = (ulong) CFG_SYS_SDRAM_BASE + mctl_calc_rank_size(¶->ranks[0]); struct sunxi_mctl_ctl_reg * const mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; @@ -744,10 +744,10 @@ static void mctl_r40_detect_rank_count(struct dram_para *para) static void mctl_auto_detect_dram_size(uint16_t socid, struct dram_para *para) { - mctl_auto_detect_dram_size_rank(socid, para, (ulong)CONFIG_SYS_SDRAM_BASE, ¶->ranks[0]); + mctl_auto_detect_dram_size_rank(socid, para, (ulong)CFG_SYS_SDRAM_BASE, ¶->ranks[0]); if ((socid == SOCID_A64 || socid == SOCID_R40) && para->dual_rank) { - mctl_auto_detect_dram_size_rank(socid, para, (ulong)CONFIG_SYS_SDRAM_BASE + mctl_calc_rank_size(¶->ranks[0]), ¶->ranks[1]); + mctl_auto_detect_dram_size_rank(socid, para, (ulong)CFG_SYS_SDRAM_BASE + mctl_calc_rank_size(¶->ranks[0]), ¶->ranks[1]); } } diff --git a/arch/arm/mach-tegra/board2.c b/arch/arm/mach-tegra/board2.c index 82d3d335028..54bbd8a776e 100644 --- a/arch/arm/mach-tegra/board2.c +++ b/arch/arm/mach-tegra/board2.c @@ -370,7 +370,7 @@ int dram_init_banksize(void) /* fall back to default DRAM bank size computation */ - gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; gd->bd->bi_dram[0].size = usable_ram_size_below_4g(); #ifdef CONFIG_PCI @@ -412,5 +412,5 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size) /* fall back to default usable RAM computation */ - return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g(); + return CFG_SYS_SDRAM_BASE + usable_ram_size_below_4g(); } diff --git a/arch/arm/mach-zynq/cpu.c b/arch/arm/mach-zynq/cpu.c index ac595ee0a27..3b6518c71c9 100644 --- a/arch/arm/mach-zynq/cpu.c +++ b/arch/arm/mach-zynq/cpu.c @@ -54,7 +54,7 @@ int arch_cpu_init(void) writel(0x757BDF0D, &devcfg_base->unlock); writel(0xFFFFFFFF, &devcfg_base->rom_shadow); -#if (CONFIG_SYS_SDRAM_BASE == 0) +#if (CFG_SYS_SDRAM_BASE == 0) /* remap DDR to zero, FILTERSTART */ writel(0, &scu_base->filter_start); diff --git a/arch/m68k/cpu/mcf532x/speed.c b/arch/m68k/cpu/mcf532x/speed.c index e2985792d96..dac2229f72e 100644 --- a/arch/m68k/cpu/mcf532x/speed.c +++ b/arch/m68k/cpu/mcf532x/speed.c @@ -239,7 +239,7 @@ int clock_pll(int fsys, int flags) * software workaround for SDRAM opeartion after exiting LIMP * mode errata */ - out_be32(sdram_workaround, CONFIG_SYS_SDRAM_BASE); + out_be32(sdram_workaround, CFG_SYS_SDRAM_BASE); #endif /* wait for DQS logic to relock */ diff --git a/arch/m68k/include/asm/immap.h b/arch/m68k/include/asm/immap.h index f2eb6fcb463..672aa0bb14e 100644 --- a/arch/m68k/include/asm/immap.h +++ b/arch/m68k/include/asm/immap.h @@ -338,9 +338,9 @@ #ifdef CONFIG_PCI #define CFG_SYS_PCI_BAR0 (0x40000000) -#define CFG_SYS_PCI_BAR1 (CONFIG_SYS_SDRAM_BASE) +#define CFG_SYS_PCI_BAR1 (CFG_SYS_SDRAM_BASE) #define CFG_SYS_PCI_TBATR0 (CONFIG_SYS_MBAR) -#define CFG_SYS_PCI_TBATR1 (CONFIG_SYS_SDRAM_BASE) +#define CFG_SYS_PCI_TBATR1 (CFG_SYS_SDRAM_BASE) #endif #endif /* CONFIG_M547x */ diff --git a/arch/m68k/lib/traps.c b/arch/m68k/lib/traps.c index 0c2c1a99655..28fe803928e 100644 --- a/arch/m68k/lib/traps.c +++ b/arch/m68k/lib/traps.c @@ -62,7 +62,7 @@ static void trap_init(ulong value) { int arch_initr_trap(void) { - trap_init(CONFIG_SYS_SDRAM_BASE); + trap_init(CFG_SYS_SDRAM_BASE); return 0; } diff --git a/arch/mips/lib/traps.c b/arch/mips/lib/traps.c index 7577fdd25d7..7a682f256a6 100644 --- a/arch/mips/lib/traps.c +++ b/arch/mips/lib/traps.c @@ -135,7 +135,7 @@ void trap_restore(void) int arch_initr_trap(void) { - trap_init(CONFIG_SYS_SDRAM_BASE); + trap_init(CFG_SYS_SDRAM_BASE); return 0; } diff --git a/arch/mips/mach-jz47xx/jz4780/jz4780.c b/arch/mips/mach-jz47xx/jz4780/jz4780.c index cff98b0a770..15d1eff2ba7 100644 --- a/arch/mips/mach-jz47xx/jz4780/jz4780.c +++ b/arch/mips/mach-jz47xx/jz4780/jz4780.c @@ -78,7 +78,7 @@ void board_init_f(ulong dummy) phys_size_t board_get_usable_ram_top(phys_size_t total_size) { - return CONFIG_SYS_SDRAM_BASE + (256 * 1024 * 1024); + return CFG_SYS_SDRAM_BASE + (256 * 1024 * 1024); } int print_cpuinfo(void) diff --git a/arch/mips/mach-mscc/cpu.c b/arch/mips/mach-mscc/cpu.c index 5bc31006aa1..d484eb92c41 100644 --- a/arch/mips/mach-mscc/cpu.c +++ b/arch/mips/mach-mscc/cpu.c @@ -17,16 +17,16 @@ DECLARE_GLOBAL_DATA_PTR; -#if CONFIG_SYS_SDRAM_SIZE <= SZ_64M +#if CFG_SYS_SDRAM_SIZE <= SZ_64M #define MSCC_RAM_TLB_SIZE SZ_64M #define MSCC_ATTRIB2 MMU_REGIO_INVAL -#elif CONFIG_SYS_SDRAM_SIZE <= SZ_128M +#elif CFG_SYS_SDRAM_SIZE <= SZ_128M #define MSCC_RAM_TLB_SIZE SZ_64M #define MSCC_ATTRIB2 MMU_REGIO_RW -#elif CONFIG_SYS_SDRAM_SIZE <= SZ_256M +#elif CFG_SYS_SDRAM_SIZE <= SZ_256M #define MSCC_RAM_TLB_SIZE SZ_256M #define MSCC_ATTRIB2 MMU_REGIO_INVAL -#elif CONFIG_SYS_SDRAM_SIZE <= SZ_512M +#elif CFG_SYS_SDRAM_SIZE <= SZ_512M #define MSCC_RAM_TLB_SIZE SZ_256M #define MSCC_ATTRIB2 MMU_REGIO_RW #else diff --git a/arch/mips/mach-mscc/dram.c b/arch/mips/mach-mscc/dram.c index c53a4202e0d..f7fbd33cc4b 100644 --- a/arch/mips/mach-mscc/dram.c +++ b/arch/mips/mach-mscc/dram.c @@ -67,6 +67,6 @@ int print_cpuinfo(void) int dram_init(void) { - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; return 0; } diff --git a/arch/mips/mach-mscc/include/mach/ddr.h b/arch/mips/mach-mscc/include/mach/ddr.h index d52eabbd2b1..75fb3ca00d2 100644 --- a/arch/mips/mach-mscc/include/mach/ddr.h +++ b/arch/mips/mach-mscc/include/mach/ddr.h @@ -13,7 +13,7 @@ #include <mach/common.h> #define MIPS_VCOREIII_MEMORY_DDR3 -#define MIPS_VCOREIII_DDR_SIZE CONFIG_SYS_SDRAM_SIZE +#define MIPS_VCOREIII_DDR_SIZE CFG_SYS_SDRAM_SIZE #if defined(CONFIG_DDRTYPE_H5TQ1G63BFA) /* Serval1 Refboard */ diff --git a/arch/mips/mach-mtmips/mt7621/spl/start.S b/arch/mips/mach-mtmips/mt7621/spl/start.S index 3cad3567e72..6b9f253952a 100644 --- a/arch/mips/mach-mtmips/mt7621/spl/start.S +++ b/arch/mips/mach-mtmips/mt7621/spl/start.S @@ -18,7 +18,7 @@ #include "dram.h" #ifndef CONFIG_SYS_INIT_SP_ADDR -#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \ +#define CONFIG_SYS_INIT_SP_ADDR (CFG_SYS_SDRAM_BASE + \ CONFIG_SYS_INIT_SP_OFFSET) #endif diff --git a/arch/mips/mach-octeon/dram.c b/arch/mips/mach-octeon/dram.c index 9c5789b1c8e..85cb084c13f 100644 --- a/arch/mips/mach-octeon/dram.c +++ b/arch/mips/mach-octeon/dram.c @@ -81,7 +81,7 @@ phys_size_t board_get_usable_ram_top(phys_size_t total_size) { if (IS_ENABLED(CONFIG_RAM_OCTEON)) { /* Map a maximum of 256MiB - return not size but address */ - return CONFIG_SYS_SDRAM_BASE + min(gd->ram_size, + return CFG_SYS_SDRAM_BASE + min(gd->ram_size, UBOOT_RAM_SIZE_MAX); } else { return gd->ram_top; diff --git a/arch/nios2/cpu/cpu.c b/arch/nios2/cpu/cpu.c index 4dd9c10faa5..85544503a5e 100644 --- a/arch/nios2/cpu/cpu.c +++ b/arch/nios2/cpu/cpu.c @@ -73,7 +73,7 @@ static int nios_cpu_setup(void *ctx, struct event *event) if (ret) return ret; - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; #ifndef CONFIG_ROM_STUBS copy_exception_trampoline(); #endif diff --git a/arch/powerpc/cpu/mpc83xx/spd_sdram.c b/arch/powerpc/cpu/mpc83xx/spd_sdram.c index e12043b2609..6d1c6b055c6 100644 --- a/arch/powerpc/cpu/mpc83xx/spd_sdram.c +++ b/arch/powerpc/cpu/mpc83xx/spd_sdram.c @@ -288,7 +288,7 @@ long int spd_sdram() /* * Set up LAWBAR for all of DDR. */ - ecm->bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000; + ecm->bar = CFG_SYS_SDRAM_BASE & 0xfffff000; ecm->ar = (LAWAR_EN | LAWAR_TRGT_IF_DDR | (LAWAR_SIZE & law_size)); debug("DDR:bar=0x%08x\n", ecm->bar); debug("DDR:ar=0x%08x\n", ecm->ar); diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index b0363c9c102..6acd31d2847 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -424,7 +424,7 @@ int dram_init(void) defined(CONFIG_ARCH_QEMU_E500) gd->ram_size = fsl_ddr_sdram_size(); #else - gd->ram_size = (phys_size_t)CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + gd->ram_size = (phys_size_t)CFG_SYS_SDRAM_SIZE * 1024 * 1024; #endif return 0; diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index f109ecb9ff7..44f8ed8a19a 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -195,7 +195,7 @@ u32 determine_mp_bootpg(unsigned int *pagesize) /* use last 4K of mapped memory */ bootpg = ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ? CONFIG_MAX_MEM_MAPPED : gd->ram_size) + - CONFIG_SYS_SDRAM_BASE - 4096; + CFG_SYS_SDRAM_BASE - 4096; if (pagesize) *pagesize = 4096; diff --git a/arch/powerpc/cpu/mpc8xxx/pamu_table.c b/arch/powerpc/cpu/mpc8xxx/pamu_table.c index d917e9dfb62..71496ab294d 100644 --- a/arch/powerpc/cpu/mpc8xxx/pamu_table.c +++ b/arch/powerpc/cpu/mpc8xxx/pamu_table.c @@ -16,7 +16,7 @@ void construct_pamu_addr_table(struct pamu_addr_tbl *tbl, int *num_entries) int j; tbl->start_addr[i] = - (uint64_t)virt_to_phys((void *)CONFIG_SYS_SDRAM_BASE); + (uint64_t)virt_to_phys((void *)CFG_SYS_SDRAM_BASE); tbl->size[i] = (phys_size_t)(min(gd->ram_size, CONFIG_MAX_MEM_MAPPED)); tbl->end_addr[i] = tbl->start_addr[i] + tbl->size[i] - 1; diff --git a/arch/powerpc/lib/bootm.c b/arch/powerpc/lib/bootm.c index 8ae8d8a3e7d..1df0822e9d7 100644 --- a/arch/powerpc/lib/bootm.c +++ b/arch/powerpc/lib/bootm.c @@ -126,7 +126,7 @@ void arch_lmb_reserve(struct lmb *lmb) #ifdef DEBUG if (((u64)bootmap_base + bootm_size) > - (CONFIG_SYS_SDRAM_BASE + (u64)gd->ram_size)) + (CFG_SYS_SDRAM_BASE + (u64)gd->ram_size)) puts("WARNING: bootm_low + bootm_size exceed total memory\n"); if ((bootmap_base + bootm_size) > get_effective_memsize()) puts("WARNING: bootm_low + bootm_size exceed eff. memory\n"); diff --git a/arch/sandbox/cpu/state.c b/arch/sandbox/cpu/state.c index a681e472ab6..dd7978cfced 100644 --- a/arch/sandbox/cpu/state.c +++ b/arch/sandbox/cpu/state.c @@ -448,7 +448,7 @@ int state_init(void) { state = &main_state; - state->ram_size = CONFIG_SYS_SDRAM_SIZE; + state->ram_size = CFG_SYS_SDRAM_SIZE; state->ram_buf = os_malloc(state->ram_size); if (!state->ram_buf) { printf("Out of memory\n"); diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts index 2051207f0ba..88b57bfb7e5 100644 --- a/arch/sandbox/dts/sandbox.dts +++ b/arch/sandbox/dts/sandbox.dts @@ -25,7 +25,7 @@ }; memory { - reg = <0 CONFIG_SYS_SDRAM_SIZE>; + reg = <0 CFG_SYS_SDRAM_SIZE>; }; reserved-memory { diff --git a/arch/sandbox/dts/sandbox64.dts b/arch/sandbox/dts/sandbox64.dts index 3eb04570891..a9cd7908f83 100644 --- a/arch/sandbox/dts/sandbox64.dts +++ b/arch/sandbox/dts/sandbox64.dts @@ -21,7 +21,7 @@ }; memory { - reg = /bits/ 64 <0 CONFIG_SYS_SDRAM_SIZE>; + reg = /bits/ 64 <0 CFG_SYS_SDRAM_SIZE>; }; reserved-memory { diff --git a/arch/sh/cpu/u-boot.lds b/arch/sh/cpu/u-boot.lds index 85ee547b4aa..d360eea7eba 100644 --- a/arch/sh/cpu/u-boot.lds +++ b/arch/sh/cpu/u-boot.lds @@ -18,7 +18,7 @@ OUTPUT_ARCH(sh) MEMORY { - ram : ORIGIN = CONFIG_SYS_SDRAM_BASE, LENGTH = CONFIG_SYS_SDRAM_SIZE + ram : ORIGIN = CFG_SYS_SDRAM_BASE, LENGTH = CFG_SYS_SDRAM_SIZE } ENTRY(_start) diff --git a/arch/sh/lib/board.c b/arch/sh/lib/board.c index 3fa093a02ea..b31fa6d7031 100644 --- a/arch/sh/lib/board.c +++ b/arch/sh/lib/board.c @@ -11,8 +11,8 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, - CONFIG_SYS_SDRAM_SIZE); + gd->ram_size = get_ram_size((long *)CFG_SYS_SDRAM_BASE, + CFG_SYS_SDRAM_SIZE); return 0; } diff --git a/arch/sh/lib/bootm.c b/arch/sh/lib/bootm.c index a5fad6c46c7..b205e5e3db1 100644 --- a/arch/sh/lib/bootm.c +++ b/arch/sh/lib/bootm.c @@ -88,7 +88,7 @@ int do_bootm_linux(int flag, int argc, char *const argv[], set_sh_linux_param((unsigned long)param + ORIG_ROOT_DEV, 0x0200); set_sh_linux_param((unsigned long)param + LOADER_TYPE, 0x0001); set_sh_linux_param((unsigned long)param + INITRD_START, - GET_INITRD_START(images->rd_start, CONFIG_SYS_SDRAM_BASE)); + GET_INITRD_START(images->rd_start, CFG_SYS_SDRAM_BASE)); set_sh_linux_param((unsigned long)param + INITRD_SIZE, images->rd_end - images->rd_start); } diff --git a/arch/xtensa/cpu/cpu.c b/arch/xtensa/cpu/cpu.c index a09e103fc1d..98d9753b7e3 100644 --- a/arch/xtensa/cpu/cpu.c +++ b/arch/xtensa/cpu/cpu.c @@ -45,7 +45,7 @@ int print_cpuinfo(void) int arch_cpu_init(void) { - gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + gd->ram_size = CFG_SYS_SDRAM_SIZE; return 0; } |