2 files changed, 119 insertions, 1 deletions
diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts
index 85b4815b2ed..3432fca3526 100644
--- a/arch/arm/dts/fsl-ls1028a-rdb.dts
+++ b/arch/arm/dts/fsl-ls1028a-rdb.dts
@@ -15,6 +15,12 @@
 	compatible = "fsl,ls1028a-rdb", "fsl,ls1028a";
 	aliases {
 		spi0 = &fspi;
+		eth0 = &enetc0;
+		eth1 = &enetc2;
+		eth2 = &mscc_felix_port0;
+		eth3 = &mscc_felix_port1;
+		eth4 = &mscc_felix_port2;
+		eth5 = &mscc_felix_port3;
 	};
 };
 
@@ -131,9 +137,67 @@
 	phy-handle = <&rdb_phy0>;
 };
 
+&enetc2 {
+	status = "okay";
+};
+
+&mscc_felix {
+	status = "okay";
+};
+
+&mscc_felix_port0 {
+	label = "swp0";
+	phy-handle = <&sw_phy0>;
+	phy-mode = "qsgmii";
+	status = "okay";
+};
+
+&mscc_felix_port1 {
+	label = "swp1";
+	phy-handle = <&sw_phy1>;
+	phy-mode = "qsgmii";
+	status = "okay";
+};
+
+&mscc_felix_port2 {
+	label = "swp2";
+	phy-handle = <&sw_phy2>;
+	phy-mode = "qsgmii";
+	status = "okay";
+};
+
+&mscc_felix_port3 {
+	label = "swp3";
+	phy-handle = <&sw_phy3>;
+	phy-mode = "qsgmii";
+	status = "okay";
+};
+
+&mscc_felix_port4 {
+	ethernet = <&enetc2>;
+	status = "okay";
+};
+
 &mdio0 {
 	status = "okay";
 	rdb_phy0: phy@2 {
 		reg = <2>;
 	};
+
+	/* VSC8514 QSGMII PHY */
+	sw_phy0: phy@10 {
+		reg = <0x10>;
+	};
+
+	sw_phy1: phy@11 {
+		reg = <0x11>;
+	};
+
+	sw_phy2: phy@12 {
+		reg = <0x12>;
+	};
+
+	sw_phy3: phy@13 {
+		reg = <0x13>;
+	};
 };
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi
index 5171bf28c79..c7c725a4fc8 100644
--- a/arch/arm/dts/fsl-ls1028a.dtsi
+++ b/arch/arm/dts/fsl-ls1028a.dtsi
@@ -151,9 +151,63 @@
 			reg = <0x000300 0 0 0 0>;
 			status = "disabled";
 		};
+
+		mscc_felix: pci@0,5 {
+			reg = <0x000500 0 0 0 0>;
+			status = "disabled";
+
+			ports {
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				mscc_felix_port0: port@0 {
+					reg = <0>;
+					status = "disabled";
+				};
+
+				mscc_felix_port1: port@1 {
+					reg = <1>;
+					status = "disabled";
+				};
+
+				mscc_felix_port2: port@2 {
+					reg = <2>;
+					status = "disabled";
+				};
+
+				mscc_felix_port3: port@3 {
+					reg = <3>;
+					status = "disabled";
+				};
+
+				mscc_felix_port4: port@4 {
+					reg = <4>;
+					phy-mode = "internal";
+					status = "disabled";
+
+					fixed-link {
+						speed = <2500>;
+						full-duplex;
+					};
+				};
+
+				mscc_felix_port5: port@5 {
+					reg = <5>;
+					phy-mode = "internal";
+					status = "disabled";
+
+					fixed-link {
+						speed = <1000>;
+						full-duplex;
+					};
+
+				};
+			};
+		};
+
 		enetc6: pci@0,6 {
 			reg = <0x000600 0 0 0 0>;
-			status = "okay";
+			status = "disabled";
 			phy-mode = "internal";
 		};
 	};