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-rw-r--r--arch/arm/cpu/armv8/cache_v8.c4
-rw-r--r--arch/arm/dts/Makefile1
-rw-r--r--arch/arm/dts/nuvoton-common-npcm8xx.dtsi170
-rw-r--r--arch/arm/dts/nuvoton-npcm845-evb.dts30
-rw-r--r--arch/arm/dts/nuvoton-npcm845.dtsi77
-rw-r--r--arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi136
-rw-r--r--arch/arm/include/asm/arch-npcm8xx/gcr.h140
-rw-r--r--arch/arm/include/asm/arch-npcm8xx/rst.h26
-rw-r--r--arch/arm/lib/bdinfo.c12
-rw-r--r--arch/arm/mach-npcm/Kconfig8
-rw-r--r--arch/arm/mach-npcm/Makefile1
-rw-r--r--arch/arm/mach-npcm/npcm8xx/Kconfig18
-rw-r--r--arch/arm/mach-npcm/npcm8xx/Makefile1
-rw-r--r--arch/arm/mach-npcm/npcm8xx/cpu.c135
-rw-r--r--arch/arm/mach-npcm/npcm8xx/reset.c37
-rw-r--r--arch/powerpc/include/asm/global_data.h6
-rw-r--r--arch/powerpc/lib/stack.c17
17 files changed, 813 insertions, 6 deletions
diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index e4736e56436..2a226fd0633 100644
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -503,6 +503,10 @@ void dcache_enable(void)
mmu_setup();
}
+ /* Set up page tables only once (it is done also by mmu_setup()) */
+ if (!gd->arch.tlb_fillptr)
+ setup_all_pgtables();
+
set_sctlr(get_sctlr() | CR_C);
}
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 9374b3cdabf..9b00b645091 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -1252,6 +1252,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \
mt8518-ap1-emmc.dtb
dtb-$(CONFIG_ARCH_NPCM7xx) += nuvoton-npcm750-evb.dtb
+dtb-$(CONFIG_ARCH_NPCM8XX) += nuvoton-npcm845-evb.dtb
dtb-$(CONFIG_XEN) += xenguest-arm64.dtb
dtb-$(CONFIG_ARCH_OCTEONTX) += octeontx.dtb
diff --git a/arch/arm/dts/nuvoton-common-npcm8xx.dtsi b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi
new file mode 100644
index 00000000000..aa7aac8c377
--- /dev/null
+++ b/arch/arm/dts/nuvoton-common-npcm8xx.dtsi
@@ -0,0 +1,170 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com
+
+#include <dt-bindings/clock/nuvoton,npcm845-clk.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ interrupt-parent = <&gic>;
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ gcr: system-controller@f0800000 {
+ compatible = "nuvoton,npcm845-gcr", "syscon";
+ reg = <0x0 0xf0800000 0x0 0x1000>;
+ };
+
+ gic: interrupt-controller@dfff9000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0xdfff9000 0x0 0x1000>,
+ <0x0 0xdfffa000 0x0 0x2000>,
+ <0x0 0xdfffc000 0x0 0x2000>,
+ <0x0 0xdfffe000 0x0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ #address-cells = <0>;
+ ppi-partitions {
+ ppi_cluster0: interrupt-partition-0 {
+ affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
+ };
+ };
+ };
+ };
+
+ ahb {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges;
+
+ rstc: reset-controller@f0801000 {
+ compatible = "nuvoton,npcm845-reset";
+ reg = <0x0 0xf0801000 0x0 0x78>;
+ #reset-cells = <2>;
+ nuvoton,sysgcr = <&gcr>;
+ };
+
+ clk: clock-controller@f0801000 {
+ compatible = "nuvoton,npcm845-clk";
+ #clock-cells = <1>;
+ reg = <0x0 0xf0801000 0x0 0x1000>;
+ };
+
+ apb {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+ ranges = <0x0 0x0 0xf0000000 0x00300000>,
+ <0xfff00000 0x0 0xfff00000 0x00016000>;
+
+ timer0: timer@8000 {
+ compatible = "nuvoton,npcm845-timer";
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x8000 0x1C>;
+ clocks = <&clk NPCM8XX_CLK_REFCLK>;
+ clock-names = "refclk";
+ };
+
+ serial0: serial@0 {
+ compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
+ reg = <0x0 0x1000>;
+ clocks = <&clk NPCM8XX_CLK_UART>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ serial1: serial@1000 {
+ compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
+ reg = <0x1000 0x1000>;
+ clocks = <&clk NPCM8XX_CLK_UART>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ serial2: serial@2000 {
+ compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
+ reg = <0x2000 0x1000>;
+ clocks = <&clk NPCM8XX_CLK_UART>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ serial3: serial@3000 {
+ compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
+ reg = <0x3000 0x1000>;
+ clocks = <&clk NPCM8XX_CLK_UART>;
+ interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ serial4: serial@4000 {
+ compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
+ reg = <0x4000 0x1000>;
+ clocks = <&clk NPCM8XX_CLK_UART>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ serial5: serial@5000 {
+ compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
+ reg = <0x5000 0x1000>;
+ clocks = <&clk NPCM8XX_CLK_UART>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ serial6: serial@6000 {
+ compatible = "nuvoton,npcm845-uart", "nuvoton,npcm750-uart";
+ reg = <0x6000 0x1000>;
+ clocks = <&clk NPCM8XX_CLK_UART>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
+ reg-shift = <2>;
+ status = "disabled";
+ };
+
+ watchdog0: watchdog@801c {
+ compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x801c 0x4>;
+ status = "disabled";
+ clocks = <&clk NPCM8XX_CLK_REFCLK>;
+ syscon = <&gcr>;
+ };
+
+ watchdog1: watchdog@901c {
+ compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x901c 0x4>;
+ status = "disabled";
+ clocks = <&clk NPCM8XX_CLK_REFCLK>;
+ syscon = <&gcr>;
+ };
+
+ watchdog2: watchdog@a01c {
+ compatible = "nuvoton,npcm845-wdt", "nuvoton,npcm750-wdt";
+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0xa01c 0x4>;
+ status = "disabled";
+ clocks = <&clk NPCM8XX_CLK_REFCLK>;
+ syscon = <&gcr>;
+ };
+ };
+ };
+};
diff --git a/arch/arm/dts/nuvoton-npcm845-evb.dts b/arch/arm/dts/nuvoton-npcm845-evb.dts
new file mode 100644
index 00000000000..a5ab2bc0f83
--- /dev/null
+++ b/arch/arm/dts/nuvoton-npcm845-evb.dts
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com
+
+/dts-v1/;
+#include "nuvoton-npcm845.dtsi"
+
+/ {
+ model = "Nuvoton npcm845 Development Board (Device Tree)";
+ compatible = "nuvoton,npcm845-evb", "nuvoton,npcm845";
+
+ aliases {
+ serial0 = &serial0;
+ };
+
+ chosen {
+ stdout-path = &serial0;
+ };
+
+ memory {
+ reg = <0x0 0x0 0x0 0x40000000>;
+ };
+};
+
+&serial0 {
+ status = "okay";
+};
+
+&watchdog1 {
+ status = "okay";
+};
diff --git a/arch/arm/dts/nuvoton-npcm845.dtsi b/arch/arm/dts/nuvoton-npcm845.dtsi
new file mode 100644
index 00000000000..6ce03f34cf8
--- /dev/null
+++ b/arch/arm/dts/nuvoton-npcm845.dtsi
@@ -0,0 +1,77 @@
+// SPDX-License-Identifier: GPL-2.0
+// Copyright (c) 2021 Nuvoton Technology tomer.maimon@nuvoton.com
+
+#include "nuvoton-common-npcm8xx.dtsi"
+#include "nuvoton-npcm8xx-u-boot.dtsi"
+
+/ {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <2>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ clocks = <&clk NPCM8XX_CLK_CPU>;
+ reg = <0x0 0x0>;
+ next-level-cache = <&l2>;
+ enable-method = "psci";
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ clocks = <&clk NPCM8XX_CLK_CPU>;
+ reg = <0x0 0x1>;
+ next-level-cache = <&l2>;
+ enable-method = "psci";
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ clocks = <&clk NPCM8XX_CLK_CPU>;
+ reg = <0x0 0x2>;
+ next-level-cache = <&l2>;
+ enable-method = "psci";
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a35";
+ clocks = <&clk NPCM8XX_CLK_CPU>;
+ reg = <0x0 0x3>;
+ next-level-cache = <&l2>;
+ enable-method = "psci";
+ };
+
+ l2: l2-cache {
+ compatible = "cache";
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a35-pmu";
+ interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+};
diff --git a/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi b/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi
new file mode 100644
index 00000000000..f5f1ce669bd
--- /dev/null
+++ b/arch/arm/dts/nuvoton-npcm8xx-u-boot.dtsi
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/reset/nuvoton,npcm8xx-reset.h>
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+
+ /* external reference clock */
+ clk_refclk: clk-refclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <25000000>;
+ clock-output-names = "refclk";
+ };
+
+ ahb {
+ rstc: reset-controller@f0801000 {
+ compatible = "nuvoton,npcm845-reset", "syscon",
+ "simple-mfd";
+ reg = <0x0 0xf0801000 0x0 0xC4>;
+ rstc1: reset-controller1 {
+ compatible = "syscon-reset";
+ #reset-cells = <1>;
+ regmap = <&rstc>;
+ offset = <NPCM8XX_RESET_IPSRST1>;
+ mask = <0xFFFFFFFF>;
+ };
+ rstc2: reset-controller2 {
+ compatible = "syscon-reset";
+ #reset-cells = <1>;
+ regmap = <&rstc>;
+ offset = <NPCM8XX_RESET_IPSRST2>;
+ mask = <0xFFFFFFFF>;
+ };
+ rstc3: reset-controller3 {
+ compatible = "syscon-reset";
+ #reset-cells = <1>;
+ regmap = <&rstc>;
+ offset = <NPCM8XX_RESET_IPSRST3>;
+ mask = <0xFFFFFFFF>;
+ };
+ rstc4: reset-controller4 {
+ compatible = "syscon-reset";
+ #reset-cells = <1>;
+ regmap = <&rstc>;
+ offset = <NPCM8XX_RESET_IPSRST4>;
+ mask = <0xFFFFFFFF>;
+ };
+ };
+
+ clk: clock-controller@f0801000 {
+ compatible = "nuvoton,npcm845-clk", "syscon";
+ #clock-cells = <1>;
+ clock-controller;
+ reg = <0x0 0xf0801000 0x0 0x1000>;
+ clock-names = "refclk";
+ clocks = <&clk_refclk>;
+ };
+
+ apb {
+ serial0: serial@0 {
+ compatible = "nuvoton,npcm845-uart";
+ reg = <0x0 0x1000>;
+ clocks = <&clk NPCM8XX_CLK_UART>, <&clk NPCM8XX_CLK_PLL2DIV2>;
+ clock-frequency = <24000000>;
+ status = "disabled";
+ };
+
+ gpio0: gpio0@10000 {
+ compatible = "nuvoton,npcm-gpio";
+ reg = <0x10000 0xB0>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-bank-name = "gpio0";
+ };
+
+ gpio1: gpio1@11000 {
+ compatible = "nuvoton,npcm-gpio";
+ reg = <0x11000 0xB0>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-bank-name = "gpio1";
+ };
+
+ gpio2: gpio2@12000 {
+ compatible = "nuvoton,npcm-gpio";
+ reg = <0x12000 0xB0>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-bank-name = "gpio2";
+ };
+
+ gpio3: gpio3@13000 {
+ compatible = "nuvoton,npcm-gpio";
+ reg = <0x13000 0xB0>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-bank-name = "gpio3";
+ };
+
+ gpio4: gpio4@14000 {
+ compatible = "nuvoton,npcm-gpio";
+ reg = <0x14000 0xB0>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-bank-name = "gpio4";
+ };
+
+ gpio5: gpio5@15000 {
+ compatible = "nuvoton,npcm-gpio";
+ reg = <0x15000 0xB0>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-bank-name = "gpio5";
+ };
+
+ gpio6: gpio6@16000 {
+ compatible = "nuvoton,npcm-gpio";
+ reg = <0x16000 0xB0>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-bank-name = "gpio6";
+ };
+
+ gpio7: gpio7@17000 {
+ compatible = "nuvoton,npcm-gpio";
+ reg = <0x17000 0xB0>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-bank-name = "gpio7";
+ };
+ };
+ };
+};
diff --git a/arch/arm/include/asm/arch-npcm8xx/gcr.h b/arch/arm/include/asm/arch-npcm8xx/gcr.h
new file mode 100644
index 00000000000..ee6677a0e54
--- /dev/null
+++ b/arch/arm/include/asm/arch-npcm8xx/gcr.h
@@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * System Global Control Register definitions
+ * Copyright (c) 2022 Nuvoton Technology Corp.
+ */
+
+#ifndef _NPCM_GCR_H_
+#define _NPCM_GCR_H_
+
+#define NPCM_GCR_BA 0xF0800000
+
+/* On-Chip ARBEL NPCM8XX VERSIONS */
+#define ARBEL_Z1 0x00A35850
+#define ARBEL_A1 0x04a35850
+#define ARBEL_NPCM845 0x00000000
+#define ARBEL_NPCM830 0x00300395
+#define ARBEL_NPCM810 0x00000220
+
+#define MFSEL4_ESPISEL BIT(8)
+#define MFSEL1_LPCSEL BIT(26)
+#define INTCR2_WDC BIT(21)
+
+struct npcm_gcr {
+ unsigned int pdid;
+ unsigned int pwron;
+ unsigned int swstrps;
+ unsigned int rsvd1[2];
+ unsigned int miscpe;
+ unsigned int spldcnt;
+ unsigned int rsvd2[1];
+ unsigned int flockr2;
+ unsigned int flockr3;
+ unsigned int rsvd3[3];
+ unsigned int a35_mode;
+ unsigned int spswc;
+ unsigned int intcr;
+ unsigned int intsr;
+ unsigned int obscr1;
+ unsigned int obsdr1;
+ unsigned int rsvd4[1];
+ unsigned int hifcr;
+ unsigned int rsvd5[3];
+ unsigned int intcr2;
+ unsigned int rsvd6[1];
+ unsigned int srcnt;
+ unsigned int ressr;
+ unsigned int rlockr1;
+ unsigned int flockr1;
+ unsigned int dscnt;
+ unsigned int mdlr;
+ unsigned int scrpad_c;
+ unsigned int scrpad_b;
+ unsigned int rsvd7[4];
+ unsigned int daclvlr;
+ unsigned int intcr3;
+ unsigned int pcirctl;
+ unsigned int rsvd8[2];
+ unsigned int vsintr;
+ unsigned int rsvd9[1];
+ unsigned int sd2sur1;
+ unsigned int sd2sur2;
+ unsigned int sd2irv3;
+ unsigned int intcr4;
+ unsigned int obscr2;
+ unsigned int obsdr2;
+ unsigned int rsvd10[5];
+ unsigned int i2csegsel;
+ unsigned int i2csegctl;
+ unsigned int vsrcr;
+ unsigned int mlockr;
+ unsigned int rsvd11[8];
+ unsigned int etsr;
+ unsigned int dft1r;
+ unsigned int dft2r;
+ unsigned int dft3r;
+ unsigned int edffsr;
+ unsigned int rsvd12[1];
+ unsigned int intcrpce3;
+ unsigned int intcrpce2;
+ unsigned int intcrpce0;
+ unsigned int intcrpce1;
+ unsigned int dactest;
+ unsigned int scrpad;
+ unsigned int usb1phyctl;
+ unsigned int usb2phyctl;
+ unsigned int usb3phyctl;
+ unsigned int intsr2;
+ unsigned int intcrpce2b;
+ unsigned int intcrpce0b;
+ unsigned int intcrpce1b;
+ unsigned int intcrpce3b;
+ unsigned int rsvd13[4];
+ unsigned int intcrpce2c;
+ unsigned int intcrpce0c;
+ unsigned int intcrpce1c;
+ unsigned int intcrpce3c;
+ unsigned int rsvd14[40];
+ unsigned int sd2irv4;
+ unsigned int sd2irv5;
+ unsigned int sd2irv6;
+ unsigned int sd2irv7;
+ unsigned int sd2irv8;
+ unsigned int sd2irv9;
+ unsigned int sd2irv10;
+ unsigned int sd2irv11;
+ unsigned int rsvd15[8];
+ unsigned int mfsel1;
+ unsigned int mfsel2;
+ unsigned int mfsel3;
+ unsigned int mfsel4;
+ unsigned int mfsel5;
+ unsigned int mfsel6;
+ unsigned int mfsel7;
+ unsigned int rsvd16[1];
+ unsigned int mfsel_lk1;
+ unsigned int mfsel_lk2;
+ unsigned int mfsel_lk3;
+ unsigned int mfsel_lk4;
+ unsigned int mfsel_lk5;
+ unsigned int mfsel_lk6;
+ unsigned int mfsel_lk7;
+ unsigned int rsvd17[1];
+ unsigned int mfsel_set1;
+ unsigned int mfsel_set2;
+ unsigned int mfsel_set3;
+ unsigned int mfsel_set4;
+ unsigned int mfsel_set5;
+ unsigned int mfsel_set6;
+ unsigned int mfsel_set7;
+ unsigned int rsvd18[1];
+ unsigned int mfsel_clr1;
+ unsigned int mfsel_clr2;
+ unsigned int mfsel_clr3;
+ unsigned int mfsel_clr4;
+ unsigned int mfsel_clr5;
+ unsigned int mfsel_clr6;
+ unsigned int mfsel_clr7;
+ };
+
+#endif
diff --git a/arch/arm/include/asm/arch-npcm8xx/rst.h b/arch/arm/include/asm/arch-npcm8xx/rst.h
new file mode 100644
index 00000000000..379e841fcae
--- /dev/null
+++ b/arch/arm/include/asm/arch-npcm8xx/rst.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef _NPCM_RST_H_
+#define _NPCM_RST_H_
+
+/* Watchdog Timer Controller Register */
+#define WTCR0_REG 0xF000801C
+#define WTCR_WTR BIT(0)
+#define WTCR_WTRE BIT(1)
+#define WTCR_WTE BIT(7)
+
+/* Reset status bits */
+#define PORST BIT(31)
+#define CORST BIT(30)
+#define WD0RST BIT(29)
+#define SW1RST BIT(28)
+#define SW2RST BIT(27)
+#define SW3RST BIT(26)
+#define SW4RST BIT(25)
+#define WD1RST BIT(24)
+#define WD2RST BIT(23)
+#define RST_STS_MASK GENMASK(31, 23)
+
+int npcm_get_reset_status(void);
+
+#endif
diff --git a/arch/arm/lib/bdinfo.c b/arch/arm/lib/bdinfo.c
index b22ee07b859..826e09e72c0 100644
--- a/arch/arm/lib/bdinfo.c
+++ b/arch/arm/lib/bdinfo.c
@@ -9,9 +9,21 @@
#include <common.h>
#include <init.h>
#include <asm/global_data.h>
+#include <asm/mach-types.h>
DECLARE_GLOBAL_DATA_PTR;
+int arch_setup_bdinfo(void)
+{
+#ifdef CONFIG_MACH_TYPE
+ struct bd_info *bd = gd->bd;
+
+ bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
+#endif
+
+ return 0;
+}
+
void arch_print_bdinfo(void)
{
struct bd_info *bd = gd->bd;
diff --git a/arch/arm/mach-npcm/Kconfig b/arch/arm/mach-npcm/Kconfig
index cf5043d6b82..7f2f9ac0971 100644
--- a/arch/arm/mach-npcm/Kconfig
+++ b/arch/arm/mach-npcm/Kconfig
@@ -19,8 +19,16 @@ config ARCH_NPCM7xx
General support for NPCM7xx BMC (Poleg).
Nuvoton NPCM7xx BMC is based on the Cortex A9.
+config ARCH_NPCM8XX
+ bool "Support Nuvoton NPCM8xx SoC"
+ select ARM64
+ help
+ General support for NPCM8xx BMC (Arbel).
+ Nuvoton NPCM8xx BMC is based on the Cortex A35.
+
endchoice
source "arch/arm/mach-npcm/npcm7xx/Kconfig"
+source "arch/arm/mach-npcm/npcm8xx/Kconfig"
endif
diff --git a/arch/arm/mach-npcm/Makefile b/arch/arm/mach-npcm/Makefile
index 8a1572b4f0e..b448329dea7 100644
--- a/arch/arm/mach-npcm/Makefile
+++ b/arch/arm/mach-npcm/Makefile
@@ -1 +1,2 @@
obj-$(CONFIG_ARCH_NPCM7xx) += npcm7xx/
+obj-$(CONFIG_ARCH_NPCM8XX) += npcm8xx/
diff --git a/arch/arm/mach-npcm/npcm8xx/Kconfig b/arch/arm/mach-npcm/npcm8xx/Kconfig
new file mode 100644
index 00000000000..5f4a0506dcb
--- /dev/null
+++ b/arch/arm/mach-npcm/npcm8xx/Kconfig
@@ -0,0 +1,18 @@
+if ARCH_NPCM8XX
+
+config SYS_CPU
+ default "armv8"
+
+config SYS_SOC
+ default "npcm8xx"
+
+config TARGET_ARBEL_EVB
+ bool "Arbel Evaluation Board"
+ help
+ ARBEL_EVB is Nuvoton evaluation board for NPCM845 SoC,
+ supports general functions of Basebase Management Controller
+ (BMC).
+
+source "board/nuvoton/arbel_evb/Kconfig"
+
+endif
diff --git a/arch/arm/mach-npcm/npcm8xx/Makefile b/arch/arm/mach-npcm/npcm8xx/Makefile
new file mode 100644
index 00000000000..6c080e19da3
--- /dev/null
+++ b/arch/arm/mach-npcm/npcm8xx/Makefile
@@ -0,0 +1 @@
+obj-y += cpu.o reset.o
diff --git a/arch/arm/mach-npcm/npcm8xx/cpu.c b/arch/arm/mach-npcm/npcm8xx/cpu.c
new file mode 100644
index 00000000000..2d839cfae95
--- /dev/null
+++ b/arch/arm/mach-npcm/npcm8xx/cpu.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Nuvoton Technology Corp.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/arch/gcr.h>
+#include <asm/armv8/mmu.h>
+
+#define SYSCNT_CTRL_BASE_ADDR 0xF07FC000
+#define SC_CNTCR_ENABLE BIT(0)
+#define SC_CNTCR_HDBG BIT(1)
+#define SC_CNTCR_FREQ0 BIT(8)
+#define SC_CNTCR_FREQ1 BIT(9)
+
+/* System Counter register map */
+struct sctr_regs {
+ u32 cntcr;
+ u32 cntsr;
+ u32 cntcv1;
+ u32 cntcv2;
+ u32 resv1[4];
+ u32 cntfid0;
+ u32 cntfid1;
+ u32 cntfid2;
+ u32 resv2[1001];
+ u32 counterid[1];
+};
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int print_cpuinfo(void)
+{
+ struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
+ unsigned int val;
+ unsigned long mpidr_val;
+
+ asm volatile("mrs %0, mpidr_el1" : "=r" (mpidr_val));
+
+ val = readl(&gcr->mdlr);
+
+ printf("CPU-%lu: ", mpidr_val & 0x3);
+
+ switch (val) {
+ case ARBEL_NPCM845:
+ printf("NPCM845 ");
+ break;
+ case ARBEL_NPCM830:
+ printf("NPCM830 ");
+ break;
+ case ARBEL_NPCM810:
+ printf("NPCM810 ");
+ break;
+ default:
+ printf("NPCM8XX ");
+ break;
+ }
+
+ val = readl(&gcr->pdid);
+ switch (val) {
+ case ARBEL_Z1:
+ printf("Z1 @ ");
+ break;
+ case ARBEL_A1:
+ printf("A1 @ ");
+ break;
+ default:
+ printf("Unknown\n");
+ break;
+ }
+
+ return 0;
+}
+
+int arch_cpu_init(void)
+{
+ if (!IS_ENABLED(CONFIG_SYS_DCACHE_OFF)) {
+ /* Enable cache to speed up system running */
+ if (get_sctlr() & CR_M)
+ return 0;
+
+ icache_enable();
+ __asm_invalidate_dcache_all();
+ __asm_invalidate_tlb_all();
+ set_sctlr(get_sctlr() | CR_C);
+ }
+
+ return 0;
+}
+
+static struct mm_region npcm_mem_map[1 + CONFIG_NR_DRAM_BANKS + 1] = {
+ {
+ /* DRAM */
+ .phys = 0x0UL,
+ .virt = 0x0UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ },
+ {
+ .phys = 0x80000000UL,
+ .virt = 0x80000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ },
+ {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = npcm_mem_map;
+
+int timer_init(void)
+{
+ struct sctr_regs *sctr = (struct sctr_regs *)SYSCNT_CTRL_BASE_ADDR;
+ u32 cntfrq_el0;
+
+ /* Enable system counter */
+ __asm__ __volatile__("mrs %0, CNTFRQ_EL0\n\t" : "=r" (cntfrq_el0) : : "memory");
+ writel(cntfrq_el0, &sctr->cntfid0);
+ clrsetbits_le32(&sctr->cntcr, SC_CNTCR_FREQ0 | SC_CNTCR_FREQ1,
+ SC_CNTCR_ENABLE | SC_CNTCR_HDBG);
+
+ gd->arch.tbl = 0;
+ gd->arch.tbu = 0;
+
+ return 0;
+}
diff --git a/arch/arm/mach-npcm/npcm8xx/reset.c b/arch/arm/mach-npcm/npcm8xx/reset.c
new file mode 100644
index 00000000000..6954e6c6a17
--- /dev/null
+++ b/arch/arm/mach-npcm/npcm8xx/reset.c
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2022 Nuvoton Technology Corp.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/gcr.h>
+#include <asm/arch/rst.h>
+
+void reset_cpu(void)
+{
+ /* Generate a watchdog0 reset */
+ writel(WTCR_WTR | WTCR_WTRE | WTCR_WTE, WTCR0_REG);
+
+ while (1)
+ ;
+}
+
+void reset_misc(void)
+{
+ struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
+
+ clrbits_le32(&gcr->intcr2, INTCR2_WDC);
+}
+
+int npcm_get_reset_status(void)
+{
+ struct npcm_gcr *gcr = (struct npcm_gcr *)NPCM_GCR_BA;
+ u32 val;
+
+ val = readl(&gcr->ressr);
+ if (!val)
+ val = readl(&gcr->intcr2);
+
+ return val & RST_STS_MASK;
+}
diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h
index 6709e692e6b..6ed21c781fe 100644
--- a/arch/powerpc/include/asm/global_data.h
+++ b/arch/powerpc/include/asm/global_data.h
@@ -92,12 +92,6 @@ struct arch_global_data {
#include <asm-generic/global_data.h>
-#if 1
#define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2")
-#else /* We could use plain global data, but the resulting code is bigger */
-#define XTRN_DECLARE_GLOBAL_DATA_PTR extern
-#define DECLARE_GLOBAL_DATA_PTR XTRN_DECLARE_GLOBAL_DATA_PTR \
- gd_t *gd
-#endif
#endif /* __ASM_GBL_DATA_H */
diff --git a/arch/powerpc/lib/stack.c b/arch/powerpc/lib/stack.c
index f2a4652e081..2e731aa8701 100644
--- a/arch/powerpc/lib/stack.c
+++ b/arch/powerpc/lib/stack.c
@@ -13,6 +13,7 @@
#include <common.h>
#include <init.h>
#include <asm/global_data.h>
+#include <asm/mp.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -30,3 +31,19 @@ int arch_reserve_stacks(void)
return 0;
}
+
+int arch_setup_dest_addr(void)
+{
+#if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
+ /*
+ * We need to make sure the location we intend to put secondary core
+ * boot code is reserved and not used by any part of u-boot
+ */
+ if (gd->relocaddr > determine_mp_bootpg(NULL)) {
+ gd->relocaddr = determine_mp_bootpg(NULL);
+ debug("Reserving MP boot page to %08lx\n", gd->relocaddr);
+ }
+#endif
+
+ return 0;
+}
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-15 02:48:04 +0000