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-rw-r--r--arch/powerpc/Kconfig2
-rw-r--r--arch/powerpc/cpu/mpc83xx/Kconfig5
-rw-r--r--arch/powerpc/cpu/mpc83xx/cpu.c2
-rw-r--r--arch/powerpc/cpu/mpc83xx/hrcw/Kconfig3
-rw-r--r--arch/powerpc/cpu/mpc83xx/start.S4
-rw-r--r--arch/powerpc/cpu/mpc8xx/Kconfig6
-rw-r--r--arch/powerpc/cpu/mpc8xx/cpu_init.c5
-rw-r--r--arch/powerpc/cpu/mpc8xx/speed.c4
-rw-r--r--arch/powerpc/dts/Makefile1
-rw-r--r--arch/powerpc/dts/cmpc885.dts12
-rw-r--r--arch/powerpc/dts/cmpcpro.dts189
-rw-r--r--arch/powerpc/dts/mcr3000.dts20
-rw-r--r--arch/powerpc/include/asm/arch-mpc83xx/gpio.h5
-rw-r--r--arch/powerpc/include/asm/arch-mpc83xx/soc.h16
-rw-r--r--arch/powerpc/include/asm/mpc8xxx_spi.h1
15 files changed, 246 insertions, 29 deletions
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index bee59c3bea4..f20d58b4de6 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -31,7 +31,7 @@ config MPC8xx
select CREATE_ARCH_SYMLINK
select BOARD_EARLY_INIT_F
imply CMD_REGINFO
- imply WDT_MPC8xx
+ imply WDT_MPC8xxx
endchoice
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index b695c7e4d81..582e1412211 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -20,6 +20,10 @@ choice
prompt "Target select"
optional
+config TARGET_CMPCPRO
+ bool "Support CMPCPRO board from CSSI"
+ select ARCH_MPC832X
+
config TARGET_MPC837XERDB
bool "Support MPC837XERDB"
select ARCH_MPC837X
@@ -205,5 +209,6 @@ config NEVER_ASSERT_ODT_TO_CPU
source "board/freescale/mpc837xerdb/Kconfig"
source "board/gdsys/mpc8308/Kconfig"
+source "board/cssi/cmpcpro/Kconfig"
endmenu
diff --git a/arch/powerpc/cpu/mpc83xx/cpu.c b/arch/powerpc/cpu/mpc83xx/cpu.c
index a6c063556e8..f6ffe295b8e 100644
--- a/arch/powerpc/cpu/mpc83xx/cpu.c
+++ b/arch/powerpc/cpu/mpc83xx/cpu.c
@@ -165,7 +165,7 @@ unsigned long get_tbclk(void)
}
#endif
-#if defined(CONFIG_WATCHDOG)
+#if defined(CONFIG_WATCHDOG) && !defined(CONFIG_WDT)
void watchdog_reset (void)
{
int re_enable = disable_interrupts();
diff --git a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
index b67ccd661d3..44f66cd5287 100644
--- a/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/hrcw/Kconfig
@@ -539,8 +539,7 @@ config DDR_MC_CLOCK_MODE
config SYSTEM_PLL_VCO_DIV
int
- default 0 if ARCH_MPC832X
- default 2 if ARCH_MPC8313
+ default 2 if ARCH_MPC8313 || ARCH_MPC832X
default 0 if SYSTEM_PLL_VCO_DIV_2 && !ARCH_MPC8360 && !ARCH_MPC837X
default 1 if SYSTEM_PLL_VCO_DIV_4 && !ARCH_MPC8360 && !ARCH_MPC837X
default 2 if SYSTEM_PLL_VCO_DIV_8 && !ARCH_MPC8360 && !ARCH_MPC837X
diff --git a/arch/powerpc/cpu/mpc83xx/start.S b/arch/powerpc/cpu/mpc83xx/start.S
index e3878e431fb..6749263da8a 100644
--- a/arch/powerpc/cpu/mpc83xx/start.S
+++ b/arch/powerpc/cpu/mpc83xx/start.S
@@ -215,6 +215,7 @@ in_flash:
* gt-regs BAT can be reused after board_init_f calls
* board_early_init_f (EVB only).
*/
+#ifdef CONFIG_SYS_INIT_RAM_LOCK
/* enable address translation */
bl enable_addr_trans
sync
@@ -222,7 +223,6 @@ in_flash:
/* enable the data cache */
bl dcache_enable
sync
-#ifdef CONFIG_SYS_INIT_RAM_LOCK
bl lock_ram_in_cache
sync
#endif
@@ -483,6 +483,7 @@ init_e300_core: /* time t 10 */
lis r3, CONFIG_SYS_IMMR@h
+#ifndef CONFIG_WDT_MPC8xxx
#if defined(CONFIG_WATCHDOG)
/* Initialise the Watchdog values and reset it (if req) */
/*------------------------------------------------------*/
@@ -508,6 +509,7 @@ init_e300_core: /* time t 10 */
stw r4, SWCRR(r3)
1:
#endif /* CONFIG_WATCHDOG */
+#endif
#if defined(CONFIG_MASK_AER_AO)
/* Write the Arbiter Event Enable to mask Address Only traps. */
diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index 628d3617bc8..bfd903bc107 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -30,9 +30,6 @@ config MPC885
endchoice
-config 8xx_GCLK_FREQ
- int "CPU GCLK Frequency"
-
comment "Specific commands"
config CMD_IMMAP
@@ -51,7 +48,8 @@ config SYS_SIUMCR
SIU Module Configuration (11-6)
config SYS_SYPCR
- hex "SYPCR register"
+ hex "SYPCR register" if !WDT_MPC8xxx
+ default 0
help
System Protection Control (11-9)
diff --git a/arch/powerpc/cpu/mpc8xx/cpu_init.c b/arch/powerpc/cpu/mpc8xx/cpu_init.c
index 86b08a61749..feef792ee77 100644
--- a/arch/powerpc/cpu/mpc8xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc8xx/cpu_init.c
@@ -26,10 +26,9 @@ void cpu_init_f(immap_t __iomem *immr)
/* SYPCR - contains watchdog control (11-9) */
-#ifndef CONFIG_HW_WATCHDOG
/* deactivate watchdog if not enabled in config */
- out_be32(&immr->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR & ~SYPCR_SWE);
-#endif
+ if (!IS_ENABLED(CONFIG_WDT_MPC8xxx))
+ out_be32(&immr->im_siu_conf.sc_sypcr, CONFIG_SYS_SYPCR & ~SYPCR_SWE);
schedule();
diff --git a/arch/powerpc/cpu/mpc8xx/speed.c b/arch/powerpc/cpu/mpc8xx/speed.c
index ad3d3f9101c..1a882a38820 100644
--- a/arch/powerpc/cpu/mpc8xx/speed.c
+++ b/arch/powerpc/cpu/mpc8xx/speed.c
@@ -14,7 +14,7 @@
DECLARE_GLOBAL_DATA_PTR;
/*
- * get_clocks() fills in gd->cpu_clock depending on CONFIG_8xx_GCLK_FREQ
+ * get_clocks() fills in gd->cpu_clk depending on CONFIG_SYS_CLK_FREQ
*/
int get_clocks(void)
{
@@ -28,7 +28,7 @@ int get_clocks(void)
* (For example, the cogent CMA286-60 CPU module has no
* separate oscillator for PITRTCLK)
*/
- gd->cpu_clk = CONFIG_8xx_GCLK_FREQ;
+ gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
if ((sccr & SCCR_EBDF11) == 0) {
/* No Bus Divider active */
diff --git a/arch/powerpc/dts/Makefile b/arch/powerpc/dts/Makefile
index 26b592b85db..bb436f02bcf 100644
--- a/arch/powerpc/dts/Makefile
+++ b/arch/powerpc/dts/Makefile
@@ -30,6 +30,7 @@ dtb-$(CONFIG_TARGET_TUXX1) += kmtuxa1.dtb
dtb-$(CONFIG_TARGET_MCR3000) += mcr3000.dtb
dtb-$(CONFIG_TARGET_GAZERBEAM) += gazerbeam.dtb
dtb-$(CONFIG_TARGET_CMPC885) += cmpc885.dtb
+dtb-$(CONFIG_TARGET_CMPCPRO) += cmpcpro.dtb
include $(srctree)/scripts/Makefile.dts
diff --git a/arch/powerpc/dts/cmpc885.dts b/arch/powerpc/dts/cmpc885.dts
index adda0f3e9dd..7b9566a0fa4 100644
--- a/arch/powerpc/dts/cmpc885.dts
+++ b/arch/powerpc/dts/cmpc885.dts
@@ -18,11 +18,6 @@
stdout-path = &SERIAL;
};
- WDT: watchdog@0 {
- device_type = "watchdog";
- compatible = "fsl,pq1-wdt";
- };
-
SERIAL: serial {
compatible = "fsl,pq1-smc";
};
@@ -43,6 +38,13 @@
ranges = <0 0xff000000 0x4000>;
reg = <0xff000000 0x00000200>;
+ WDT: watchdog@0 {
+ compatible = "fsl,pq1-wdt";
+ reg = <0x0 0x10>;
+ timeout-sec = <2>;
+ hw_margin_ms = <1000>;
+ };
+
CPM1_PIO_B: gpio-controller@ab8 {
#gpio-cells = <2>;
compatible = "fsl,cpm1-pario-bank-b";
diff --git a/arch/powerpc/dts/cmpcpro.dts b/arch/powerpc/dts/cmpcpro.dts
new file mode 100644
index 00000000000..c27d9dba335
--- /dev/null
+++ b/arch/powerpc/dts/cmpcpro.dts
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * CMPC885 Device Tree Source
+ *
+ * Copyright 2020 CS GROUP France
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/clk/mpc83xx-clk.h>
+
+/ {
+ model = "CMPCPRO";
+ compatible = "fsl, cmpc85xx", "fsl,mod85xx", "CMPCPRO", "MPC8321E", "fsl,cmpcpro";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ chosen {
+ stdout-path = &serial0;
+ };
+ WDT: watchdog@0 {
+ device_type = "watchdog";
+ compatible = "fsl,pq1-wdt";
+ };
+
+ aliases {
+ ethernet0 = &eth0;
+ etehrnet1 = &eth1;
+ serial0 = &serial0;
+ };
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ PowerPC,8321@0 {
+ device_type = "cpu";
+ reg = <0x0>;
+ d-cache-line-size = <0x20>; // 32 bytes
+ i-cache-line-size = <0x20>; // 32 bytes
+ d-cache-size = <16384>; // L1, 16K
+ i-cache-size = <16384>; // L1, 16K
+ timebase-frequency = <0>;
+ bus-frequency = <0>;
+ clock-frequency = <0>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x00000000 0x20000000>;
+ };
+
+ soc8321@b0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "soc";
+ compatible = "simple-bus";
+ ranges = <0x0 0xb0000000 0x00100000>;
+ reg = <0xb0000000 0x00000200>;
+ bus-frequency = <0>;
+ pmc: power@b00 {
+ compatible = "fsl,mpc8323-pmc", "fsl,mpc8349-pmc";
+ reg = <0xb00 0x100 0xa00 0x100>;
+ interrupts = <80 0x8>;
+ interrupt-parent = <&ipic>;
+ };
+ serial0: serial@4500 {
+ clocks = <&socclocks MPC83XX_CLK_CSB>;
+ cell-index = <0>;
+ device_type = "serial";
+ compatible = "fsl,ns16550", "ns16550";
+ reg = <0x4500 0x100>;
+ clock-frequency = <0>;
+ interrupts = <9 0x8>;
+ interrupt-parent = <&ipic>;
+ };
+ ipic:pic@700 {
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <0x700 0x100>;
+ device_type = "ipic";
+ };
+ par_io@1400 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x1400 0x100>;
+ ranges;
+ compatible = "fsl,mpc8323-qe-pario","simple-bus";
+ device_type = "par_io";
+ num-ports = <7>;
+ qe_pio_a: gpio-controller@1400 {
+ #gpio-cells = <2>;
+ compatible = "fsl,mpc8323-qe-pario-bank","fsl,mpc8308-gpio";
+ reg = <0x1400 0x18>;
+ gpio-controller;
+ };
+ qe_pio_b: gpio-controller@1418 {
+ #gpio-cells = <2>;
+ compatible = "fsl,mpc8323-qe-pario-bank","fsl,mpc8308-gpio";
+ reg = <0x1418 0x18>;
+ gpio-controller;
+ };
+ qe_pio_c: gpio-controller@1430 {
+ #gpio-cells = <2>;
+ compatible = "fsl,mpc8323-qe-pario-bank","fsl,mpc8308-gpio";
+ reg = <0x1430 0x18>;
+ gpio-controller;
+ };
+ qe_pio_d: gpio-controller@1448 {
+ #gpio-cells = <2>;
+ compatible = "fsl,mpc8323-qe-pario-bank","fsl,mpc8308-gpio";
+ reg = <0x1448 0x18>;
+ gpio-controller;
+ };
+ };
+ };
+ socclocks: clocks {
+ bootph-all;
+ compatible = "fsl,mpc832x-clk";
+ #clock-cells = <1>;
+ };
+ qe@b0100000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device_type = "qe";
+ compatible = "fsl,qe","simple-bus";
+ ranges = <0x0 0xb0100000 0x00100000>;
+ reg = <0xb0100000 0x480>;
+ brg-frequency = <0>;
+ bus-frequency = <198000000>;
+ fsl,qe-num-riscs = <1>;
+ fsl,qe-num-snums = <28>;
+ spi@4c0 {
+ clocks = <&socclocks MPC83XX_CLK_CSB>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cell-index = <0>;
+ compatible = "fsl,mpc832x-spi";
+ reg = <0x4c0 0x40>;
+ mode = "cpu";
+ gpios = <&qe_pio_d 3 1>;
+ clock-frequency = <0>;
+ eeprom@3 {
+ compatible = "atmel,at25", "cs,eeprom";
+ cell-index = <1>;
+ };
+ };
+ eth0: ucc@3000 {
+ device_type = "network";
+ compatible = "ucc_geth";
+ cell-index = <2>;
+ reg = <0x3000 0x200>;
+ rx-clock-name = "clk17";
+ tx-clock-name = "clk17";
+ phy-handle = <&phy1>;
+ phy-connection-type = "rmii";
+ };
+ eth1: ucc@2200 {
+ device_type = "network";
+ compatible = "ucc_geth";
+ cell-index = <3>;
+ reg = <0x2200 0x200>;
+ rx-clock-name = "clk12";
+ tx-clock-name = "clk12";
+ phy-handle = <&phy2>;
+ phy-connection-type = "rmii";
+ };
+ mdio@3120 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3120 0x18>;
+ compatible = "fsl,ucc-mdio";
+ phy1:ethernet-phy@1 {
+ interrupt-parent = <&ipic>;
+ reg = <0x1>;
+ interrupts = <17 8>;
+ device_type = "ethernet-phy";
+ };
+ phy2:ethernet-phy@2 {
+ interrupt-parent = <&ipic>;
+ reg = <0x2>;
+ interrupts = <17 8>;
+ device_type = "ethernet-phy";
+ };
+ };
+ };
+};
diff --git a/arch/powerpc/dts/mcr3000.dts b/arch/powerpc/dts/mcr3000.dts
index 5f32d8a2e55..c4d7737bc67 100644
--- a/arch/powerpc/dts/mcr3000.dts
+++ b/arch/powerpc/dts/mcr3000.dts
@@ -9,9 +9,25 @@
/dts-v1/;
/ {
- WDT: watchdog@0 {
- compatible = "fsl,pq1-wdt";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ soc: immr@ff000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ device-type = "soc";
+ compatible = "simple-bus";
+ ranges = <0 0xff000000 0x4000>;
+ reg = <0xff000000 0x00000200>;
+
+ WDT: watchdog@0 {
+ compatible = "fsl,pq1-wdt";
+ reg = <0x0 0x10>;
+ timeout-sec = <2>;
+ hw_margin_ms = <1000>;
+ };
};
+
SERIAL: smc@0 {
compatible = "fsl,pq1-smc";
};
diff --git a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
index 19c2506c9b1..df95d2238fd 100644
--- a/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
+++ b/arch/powerpc/include/asm/arch-mpc83xx/gpio.h
@@ -22,6 +22,11 @@ struct mpc8xxx_gpio_plat {
uint ngpios;
};
+struct qe_gpio_plat {
+ ulong addr;
+ unsigned long size;
+};
+
#ifndef DM_GPIO
void mpc83xx_gpio_init_f(void);
void mpc83xx_gpio_init_r(void);
diff --git a/arch/powerpc/include/asm/arch-mpc83xx/soc.h b/arch/powerpc/include/asm/arch-mpc83xx/soc.h
index 39bf7d5a7f9..ce54f9bebbe 100644
--- a/arch/powerpc/include/asm/arch-mpc83xx/soc.h
+++ b/arch/powerpc/include/asm/arch-mpc83xx/soc.h
@@ -18,14 +18,14 @@ enum soc_type {
SOC_MPC8379,
};
-bool mpc83xx_has_sdhc(int type)
+static inline bool mpc83xx_has_sdhc(int type)
{
return (type == SOC_MPC8308) ||
(type == SOC_MPC8309) ||
(type == SOC_MPC8379);
}
-bool mpc83xx_has_tsec(int type)
+static inline bool mpc83xx_has_tsec(int type)
{
return (type == SOC_MPC8308) ||
(type == SOC_MPC8313) ||
@@ -34,37 +34,37 @@ bool mpc83xx_has_tsec(int type)
(type == SOC_MPC8379);
}
-bool mpc83xx_has_pcie1(int type)
+static inline bool mpc83xx_has_pcie1(int type)
{
return (type == SOC_MPC8308) ||
(type == SOC_MPC8315) ||
(type == SOC_MPC8379);
}
-bool mpc83xx_has_pcie2(int type)
+static inline bool mpc83xx_has_pcie2(int type)
{
return (type == SOC_MPC8315) ||
(type == SOC_MPC8379);
}
-bool mpc83xx_has_sata(int type)
+static inline bool mpc83xx_has_sata(int type)
{
return (type == SOC_MPC8315) ||
(type == SOC_MPC8379);
}
-bool mpc83xx_has_pci(int type)
+static inline bool mpc83xx_has_pci(int type)
{
return type != SOC_MPC8308;
}
-bool mpc83xx_has_second_i2c(int type)
+static inline bool mpc83xx_has_second_i2c(int type)
{
return (type != SOC_MPC8315) &&
(type != SOC_MPC832X);
}
-bool mpc83xx_has_quicc_engine(int type)
+static inline bool mpc83xx_has_quicc_engine(int type)
{
return (type == SOC_MPC8309) ||
(type == SOC_MPC832X) ||
diff --git a/arch/powerpc/include/asm/mpc8xxx_spi.h b/arch/powerpc/include/asm/mpc8xxx_spi.h
index 83cfe23b4e7..8e9411aefb3 100644
--- a/arch/powerpc/include/asm/mpc8xxx_spi.h
+++ b/arch/powerpc/include/asm/mpc8xxx_spi.h
@@ -12,6 +12,7 @@
#if defined(CONFIG_ARCH_MPC8308) || \
defined(CONFIG_ARCH_MPC8313) || \
+ defined(CONFIG_ARCH_MPC832X) || \
defined(CONFIG_ARCH_MPC834X) || \
defined(CONFIG_ARCH_MPC837X)
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-13 10:46:38 +0000