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Diffstat (limited to 'board/atmel/sama7g5ek/sama7g5ek.c')
-rw-r--r--board/atmel/sama7g5ek/sama7g5ek.c68
1 files changed, 68 insertions, 0 deletions
diff --git a/board/atmel/sama7g5ek/sama7g5ek.c b/board/atmel/sama7g5ek/sama7g5ek.c
new file mode 100644
index 00000000000..42b032cf363
--- /dev/null
+++ b/board/atmel/sama7g5ek/sama7g5ek.c
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2020 Microchip Technology, Inc.
+ * Eugen Hristev <eugen.hristev@microchip.com>
+ */
+
+#include <common.h>
+#include <debug_uart.h>
+#include <init.h>
+#include <asm/io.h>
+#include <asm/arch/at91_common.h>
+#include <asm/arch/atmel_pio4.h>
+#include <asm/arch/clk.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/sama7g5.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_late_init(void)
+{
+ return 0;
+}
+
+#if (IS_ENABLED(CONFIG_DEBUG_UART_BOARD_INIT))
+static void board_uart0_hw_init(void)
+{
+ /* FLEXCOM3 IO0 */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTD, 17, ATMEL_PIO_PUEN_MASK);
+ /* FLEXCOM3 IO1 */
+ atmel_pio4_set_f_periph(AT91_PIO_PORTD, 16, 0);
+
+ at91_periph_clk_enable(ATMEL_ID_FLEXCOM3);
+}
+
+void board_debug_uart_init(void)
+{
+ board_uart0_hw_init();
+}
+#endif
+
+int board_early_init_f(void)
+{
+#if (IS_ENABLED(CONFIG_DEBUG_UART))
+ debug_uart_init();
+#endif
+ return 0;
+}
+
+int board_init(void)
+{
+ /* address of boot parameters */
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
+ CONFIG_SYS_SDRAM_SIZE);
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ return 0;
+}
+