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-rw-r--r--board/compulab/cm_t35/cm_t35.c157
-rw-r--r--board/compulab/cm_t3517/Kconfig12
-rw-r--r--board/compulab/cm_t3517/MAINTAINERS6
-rw-r--r--board/compulab/cm_t3517/Makefile9
-rw-r--r--board/compulab/cm_t3517/cm_t3517.c231
-rw-r--r--board/compulab/cm_t3517/mux.c236
-rw-r--r--board/compulab/cm_t54/cm_t54.c7
-rw-r--r--board/compulab/common/Makefile7
-rw-r--r--board/compulab/common/common.c59
-rw-r--r--board/compulab/common/common.h47
-rw-r--r--board/compulab/common/eeprom.c14
-rw-r--r--board/compulab/common/omap3_smc911x.c93
-rw-r--r--board/compulab/common/splash.c72
13 files changed, 796 insertions, 154 deletions
diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c
index d0b0930f423..886c7239005 100644
--- a/board/compulab/cm_t35/cm_t35.c
+++ b/board/compulab/cm_t35/cm_t35.c
@@ -19,12 +19,11 @@
#include <i2c.h>
#include <usb.h>
#include <mmc.h>
-#include <nand.h>
#include <twl4030.h>
-#include <bmp_layout.h>
#include <linux/compiler.h>
#include <asm/io.h>
+#include <asm/errno.h>
#include <asm/arch/mem.h>
#include <asm/arch/mux.h>
#include <asm/arch/mmc_host_def.h>
@@ -33,6 +32,7 @@
#include <asm/ehci-omap.h>
#include <asm/gpio.h>
+#include "../common/common.h"
#include "../common/eeprom.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -43,58 +43,6 @@ const omap3_sysinfo sysinfo = {
"NAND",
};
-static u32 gpmc_net_config[GPMC_MAX_REG] = {
- NET_GPMC_CONFIG1,
- NET_GPMC_CONFIG2,
- NET_GPMC_CONFIG3,
- NET_GPMC_CONFIG4,
- NET_GPMC_CONFIG5,
- NET_GPMC_CONFIG6,
- 0
-};
-
-#ifdef CONFIG_LCD
-#ifdef CONFIG_CMD_NAND
-static int splash_load_from_nand(u32 bmp_load_addr)
-{
- struct bmp_header *bmp_hdr;
- int res, splash_screen_nand_offset = 0x100000;
- size_t bmp_size, bmp_header_size = sizeof(struct bmp_header);
-
- if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp)
- goto splash_address_too_high;
-
- res = nand_read_skip_bad(&nand_info[nand_curr_device],
- splash_screen_nand_offset, &bmp_header_size,
- NULL, nand_info[nand_curr_device].size,
- (u_char *)bmp_load_addr);
- if (res < 0)
- return res;
-
- bmp_hdr = (struct bmp_header *)bmp_load_addr;
- bmp_size = le32_to_cpu(bmp_hdr->file_size);
-
- if (bmp_load_addr + bmp_size >= gd->start_addr_sp)
- goto splash_address_too_high;
-
- return nand_read_skip_bad(&nand_info[nand_curr_device],
- splash_screen_nand_offset, &bmp_size,
- NULL, nand_info[nand_curr_device].size,
- (u_char *)bmp_load_addr);
-
-splash_address_too_high:
- printf("Error: splashimage address too high. Data overwrites U-Boot "
- "and/or placed beyond DRAM boundaries.\n");
-
- return -1;
-}
-#else
-static inline int splash_load_from_nand(void)
-{
- return -1;
-}
-#endif /* CONFIG_CMD_NAND */
-
#ifdef CONFIG_SPL_BUILD
/*
* Routine: get_board_mem_timings
@@ -111,24 +59,12 @@ void get_board_mem_timings(struct board_sdrc_timings *timings)
}
#endif
+#define CM_T35_SPLASH_NAND_OFFSET 0x100000
+
int splash_screen_prepare(void)
{
- char *env_splashimage_value;
- u32 bmp_load_addr;
-
- env_splashimage_value = getenv("splashimage");
- if (env_splashimage_value == NULL)
- return -1;
-
- bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16);
- if (bmp_load_addr == 0) {
- printf("Error: bad splashimage address specified\n");
- return -1;
- }
-
- return splash_load_from_nand(bmp_load_addr);
+ return cl_splash_screen_prepare(CM_T35_SPLASH_NAND_OFFSET);
}
-#endif /* CONFIG_LCD */
/*
* Routine: board_init
@@ -154,34 +90,18 @@ int board_init(void)
return 0;
}
-static u32 cm_t3x_rev;
-
/*
* Routine: get_board_rev
* Description: read system revision
*/
u32 get_board_rev(void)
{
- if (!cm_t3x_rev)
- cm_t3x_rev = cl_eeprom_get_board_rev();
-
- return cm_t3x_rev;
+ return cl_eeprom_get_board_rev();
};
-/*
- * Routine: misc_init_r
- * Description: display die ID
- */
int misc_init_r(void)
{
- u32 board_rev = get_board_rev();
- u32 rev_major = board_rev / 100;
- u32 rev_minor = board_rev - (rev_major * 100);
-
- if ((rev_minor / 10) * 10 == rev_minor)
- rev_minor = rev_minor / 10;
-
- printf("PCB: %u.%u\n", rev_major, rev_minor);
+ cl_print_pcb_info();
dieid_num_r();
return 0;
@@ -462,37 +382,12 @@ int board_mmc_init(bd_t *bis)
}
#endif
-/*
- * Routine: setup_net_chip_gmpc
- * Description: Setting up the configuration GPMC registers specific to the
- * Ethernet hardware.
- */
-static void setup_net_chip_gmpc(void)
-{
- struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
-
- enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[5],
- CM_T3X_SMC911X_BASE, GPMC_SIZE_16M);
- enable_gpmc_cs_config(gpmc_net_config, &gpmc_cfg->cs[4],
- SB_T35_SMC911X_BASE, GPMC_SIZE_16M);
-
- /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
- writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
-
- /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
- writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
-
- /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
- writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
- &ctrl_base->gpmc_nadv_ale);
-}
-
#ifdef CONFIG_SYS_I2C_OMAP34XX
/*
* Routine: reset_net_chip
* Description: reset the Ethernet controller via TPS65930 GPIO
*/
-static void reset_net_chip(void)
+static int cm_t3x_reset_net_chip(int gpio)
{
/* Set GPIO1 of TPS65930 as output */
twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x03,
@@ -507,9 +402,10 @@ static void reset_net_chip(void)
twl4030_i2c_write_u8(TWL4030_CHIP_GPIO, TWL4030_BASEADD_GPIO + 0x0C,
0x02);
mdelay(1);
+ return 0;
}
#else
-static inline void reset_net_chip(void) {}
+static inline int cm_t3x_reset_net_chip(int gpio) { return 0; }
#endif
#ifdef CONFIG_SMC911X
@@ -536,7 +432,6 @@ static int handle_mac_address(void)
return eth_setenv_enetaddr("ethaddr", enetaddr);
}
-
/*
* Routine: board_eth_init
* Description: initialize module and base-board Ethernet chips
@@ -545,18 +440,16 @@ int board_eth_init(bd_t *bis)
{
int rc = 0, rc1 = 0;
- setup_net_chip_gmpc();
- reset_net_chip();
-
rc1 = handle_mac_address();
if (rc1)
printf("No MAC address found! ");
- rc1 = smc911x_initialize(0, CM_T3X_SMC911X_BASE);
+ rc1 = cl_omap3_smc911x_init(0, 5, CM_T3X_SMC911X_BASE,
+ cm_t3x_reset_net_chip, -EINVAL);
if (rc1 > 0)
rc++;
- rc1 = smc911x_initialize(1, SB_T35_SMC911X_BASE);
+ rc1 = cl_omap3_smc911x_init(1, 4, SB_T35_SMC911X_BASE, NULL, -EINVAL);
if (rc1 > 0)
rc++;
@@ -564,16 +457,6 @@ int board_eth_init(bd_t *bis)
}
#endif
-void __weak get_board_serial(struct tag_serialnr *serialnr)
-{
- /*
- * This corresponds to what happens when we can communicate with the
- * eeprom but don't get a valid board serial value.
- */
- serialnr->low = 0;
- serialnr->high = 0;
-};
-
#ifdef CONFIG_USB_EHCI_OMAP
struct omap_usbhs_board_data usbhs_bdata = {
.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
@@ -583,21 +466,12 @@ struct omap_usbhs_board_data usbhs_bdata = {
#define SB_T35_USB_HUB_RESET_GPIO 167
int ehci_hcd_init(int index, enum usb_init_type init,
- struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
{
u8 val;
int offset;
- if (gpio_request(SB_T35_USB_HUB_RESET_GPIO, "SB-T35 usb hub reset")) {
- printf("Error: can't obtain GPIO %d for SB-T35 usb hub reset",
- SB_T35_USB_HUB_RESET_GPIO);
- return -1;
- }
-
- gpio_direction_output(SB_T35_USB_HUB_RESET_GPIO, 0);
- udelay(10);
- gpio_set_value(SB_T35_USB_HUB_RESET_GPIO, 1);
- udelay(1000);
+ cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst");
offset = TWL4030_BASEADD_GPIO + TWL4030_GPIO_GPIODATADIR1;
twl4030_i2c_read_u8(TWL4030_CHIP_GPIO, offset, &val);
@@ -614,6 +488,7 @@ int ehci_hcd_init(int index, enum usb_init_type init,
int ehci_hcd_stop(void)
{
+ cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO);
return omap_ehci_hcd_stop();
}
#endif /* CONFIG_USB_EHCI_OMAP */
diff --git a/board/compulab/cm_t3517/Kconfig b/board/compulab/cm_t3517/Kconfig
new file mode 100644
index 00000000000..2f5473d76a1
--- /dev/null
+++ b/board/compulab/cm_t3517/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_CM_T3517
+
+config SYS_BOARD
+ default "cm_t3517"
+
+config SYS_VENDOR
+ default "compulab"
+
+config SYS_CONFIG_NAME
+ default "cm_t3517"
+
+endif
diff --git a/board/compulab/cm_t3517/MAINTAINERS b/board/compulab/cm_t3517/MAINTAINERS
new file mode 100644
index 00000000000..fbb6882138b
--- /dev/null
+++ b/board/compulab/cm_t3517/MAINTAINERS
@@ -0,0 +1,6 @@
+CM_T3517 BOARD
+M: Igor Grinberg <grinberg@compulab.co.il>
+S: Maintained
+F: board/compulab/cm_t3517/
+F: include/configs/cm_t3517.h
+F: configs/cm_t3517_defconfig
diff --git a/board/compulab/cm_t3517/Makefile b/board/compulab/cm_t3517/Makefile
new file mode 100644
index 00000000000..4f0db01e378
--- /dev/null
+++ b/board/compulab/cm_t3517/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+#
+# Authors: Igor Grinberg <grinberg@compulab.co.il>
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += cm_t3517.o mux.o
diff --git a/board/compulab/cm_t3517/cm_t3517.c b/board/compulab/cm_t3517/cm_t3517.c
new file mode 100644
index 00000000000..cac1ad9ef11
--- /dev/null
+++ b/board/compulab/cm_t3517/cm_t3517.c
@@ -0,0 +1,231 @@
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <status_led.h>
+#include <net.h>
+#include <netdev.h>
+#include <usb.h>
+#include <mmc.h>
+#include <linux/compiler.h>
+#include <linux/usb/musb.h>
+
+#include <asm/io.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/am35x_def.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/musb.h>
+#include <asm/omap_musb.h>
+#include <asm/ehci-omap.h>
+
+#include "../common/common.h"
+#include "../common/eeprom.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+const omap3_sysinfo sysinfo = {
+ DDR_DISCRETE,
+ "CM-T3517 board",
+ "NAND 128/512M",
+};
+
+#ifdef CONFIG_USB_MUSB_AM35X
+static struct musb_hdrc_config cm_t3517_musb_config = {
+ .multipoint = 1,
+ .dyn_fifo = 1,
+ .num_eps = 16,
+ .ram_bits = 12,
+};
+
+static struct omap_musb_board_data cm_t3517_musb_board_data = {
+ .set_phy_power = am35x_musb_phy_power,
+ .clear_irq = am35x_musb_clear_irq,
+ .reset = am35x_musb_reset,
+};
+
+static struct musb_hdrc_platform_data cm_t3517_musb_pdata = {
+#if defined(CONFIG_MUSB_HOST)
+ .mode = MUSB_HOST,
+#elif defined(CONFIG_MUSB_GADGET)
+ .mode = MUSB_PERIPHERAL,
+#else
+#error "Please define either CONFIG_MUSB_HOST or CONFIG_MUSB_GADGET"
+#endif
+ .config = &cm_t3517_musb_config,
+ .power = 250,
+ .platform_ops = &am35x_ops,
+ .board_data = &cm_t3517_musb_board_data,
+};
+
+static void cm_t3517_musb_init(void)
+{
+ /*
+ * Set up USB clock/mode in the DEVCONF2 register.
+ * USB2.0 PHY reference clock is 13 MHz
+ */
+ clrsetbits_le32(&am35x_scm_general_regs->devconf2,
+ CONF2_REFFREQ | CONF2_OTGMODE | CONF2_PHY_GPIOMODE,
+ CONF2_REFFREQ_13MHZ | CONF2_SESENDEN |
+ CONF2_VBDTCTEN | CONF2_DATPOL);
+
+ if (musb_register(&cm_t3517_musb_pdata, &cm_t3517_musb_board_data,
+ (void *)AM35XX_IPSS_USBOTGSS_BASE))
+ printf("Failed initializing AM35x MUSB!\n");
+}
+#else
+static inline void am3517_evm_musb_init(void) {}
+#endif
+
+int board_init(void)
+{
+ gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
+
+ /* boot param addr */
+ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
+
+#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT)
+ status_led_set(STATUS_LED_BOOT, STATUS_LED_ON);
+#endif
+
+ cm_t3517_musb_init();
+
+ return 0;
+}
+
+int misc_init_r(void)
+{
+ cl_print_pcb_info();
+ dieid_num_r();
+
+ return 0;
+}
+
+#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD)
+#define SB_T35_CD_GPIO 144
+#define SB_T35_WP_GPIO 59
+
+int board_mmc_init(bd_t *bis)
+{
+ return omap_mmc_init(0, 0, 0, SB_T35_CD_GPIO, SB_T35_WP_GPIO);
+}
+#endif
+
+#ifdef CONFIG_DRIVER_TI_EMAC
+#define CONTROL_EFUSE_EMAC_LSB 0x48002380
+#define CONTROL_EFUSE_EMAC_MSB 0x48002384
+
+static int am3517_get_efuse_enetaddr(u8 *enetaddr)
+{
+ u32 lsb = __raw_readl(CONTROL_EFUSE_EMAC_LSB);
+ u32 msb = __raw_readl(CONTROL_EFUSE_EMAC_MSB);
+
+ enetaddr[0] = (u8)((msb >> 16) & 0xff);
+ enetaddr[1] = (u8)((msb >> 8) & 0xff);
+ enetaddr[2] = (u8)(msb & 0xff);
+ enetaddr[3] = (u8)((lsb >> 16) & 0xff);
+ enetaddr[4] = (u8)((lsb >> 8) & 0xff);
+ enetaddr[5] = (u8)(lsb & 0xff);
+
+ return is_valid_ether_addr(enetaddr);
+}
+
+static inline int cm_t3517_init_emac(bd_t *bis)
+{
+ int ret = cpu_eth_init(bis);
+
+ if (ret > 0)
+ return ret;
+
+ printf("Failed initializing EMAC! ");
+ return 0;
+}
+#else /* !CONFIG_DRIVER_TI_EMAC */
+static inline int am3517_get_efuse_enetaddr(u8 *enetaddr) { return 1; }
+static inline int cm_t3517_init_emac(bd_t *bis) { return 0; }
+#endif /* CONFIG_DRIVER_TI_EMAC */
+
+/*
+ * Routine: handle_mac_address
+ * Description: prepare MAC address for on-board Ethernet.
+ */
+static int cm_t3517_handle_mac_address(void)
+{
+ unsigned char enetaddr[6];
+ int ret;
+
+ ret = eth_getenv_enetaddr("ethaddr", enetaddr);
+ if (ret)
+ return 0;
+
+ ret = cl_eeprom_read_mac_addr(enetaddr);
+ if (ret) {
+ ret = am3517_get_efuse_enetaddr(enetaddr);
+ if (ret)
+ return ret;
+ }
+
+ if (!is_valid_ether_addr(enetaddr))
+ return -1;
+
+ return eth_setenv_enetaddr("ethaddr", enetaddr);
+}
+
+#define SB_T35_ETH_RST_GPIO 164
+
+/*
+ * Routine: board_eth_init
+ * Description: initialize module and base-board Ethernet chips
+ */
+int board_eth_init(bd_t *bis)
+{
+ int rc = 0, rc1 = 0;
+
+ rc1 = cm_t3517_handle_mac_address();
+ if (rc1)
+ printf("No MAC address found! ");
+
+ rc1 = cm_t3517_init_emac(bis);
+ if (rc1 > 0)
+ rc++;
+
+ rc1 = cl_omap3_smc911x_init(0, 4, CONFIG_SMC911X_BASE,
+ NULL, SB_T35_ETH_RST_GPIO);
+ if (rc1 > 0)
+ rc++;
+
+ return rc;
+}
+
+#ifdef CONFIG_USB_EHCI_OMAP
+static struct omap_usbhs_board_data cm_t3517_usbhs_bdata = {
+ .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
+ .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
+ .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
+};
+
+#define CM_T3517_USB_HUB_RESET_GPIO 152
+#define SB_T35_USB_HUB_RESET_GPIO 98
+
+int ehci_hcd_init(int index, enum usb_init_type init,
+ struct ehci_hccr **hccr, struct ehci_hcor **hcor)
+{
+ cl_usb_hub_init(CM_T3517_USB_HUB_RESET_GPIO, "cm-t3517 hub rst");
+ cl_usb_hub_init(SB_T35_USB_HUB_RESET_GPIO, "sb-t35 hub rst");
+
+ return omap_ehci_hcd_init(index, &cm_t3517_usbhs_bdata, hccr, hcor);
+}
+
+int ehci_hcd_stop(void)
+{
+ cl_usb_hub_deinit(CM_T3517_USB_HUB_RESET_GPIO);
+ cl_usb_hub_deinit(SB_T35_USB_HUB_RESET_GPIO);
+
+ return omap_ehci_hcd_stop();
+}
+#endif /* CONFIG_USB_EHCI_OMAP */
diff --git a/board/compulab/cm_t3517/mux.c b/board/compulab/cm_t3517/mux.c
new file mode 100644
index 00000000000..88ce2cc2e64
--- /dev/null
+++ b/board/compulab/cm_t3517/mux.c
@@ -0,0 +1,236 @@
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+
+void set_muxconf_regs(void)
+{
+ /* SDRC */
+ MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(SDRC_CKE1), (IDIS | PTD | DIS | M7));
+
+ /* GPMC */
+ MUX_VAL(CP(GPMC_A1), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A2), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A3), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A4), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A5), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A6), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A7), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A8), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D0), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D1), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D2), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D3), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D4), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D5), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D6), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D7), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D8), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D9), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D10), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D11), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D12), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D13), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D14), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_D15), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0));
+
+ /* SB-T35 Ethernet */
+ MUX_VAL(CP(GPMC_NCS4), (IEN | PTU | EN | M0));
+ /* DVI enable */
+ MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | DIS | M4));/*GPIO_54*/
+ /* DataImage backlight */
+ MUX_VAL(CP(GPMC_NCS7), (IDIS | PTU | DIS | M4));/*GPIO_58*/
+
+ /* SB-T35 SD/MMC WP GPIO59 */
+ MUX_VAL(CP(GPMC_CLK), (IEN | PTU | EN | M4)); /*GPIO_59*/
+ MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTU | EN | M0));
+ /* SB-T35 Audio Enable GPIO61 */
+ MUX_VAL(CP(GPMC_NBE1), (IDIS | PTU | EN | M4)); /*GPIO_61*/
+ MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0));
+ /* SB-T35 Ethernet IRQ GPIO65 */
+ MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M4)); /*GPIO_65*/
+
+ /* UART3 Console */
+ MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0));
+ /* RTC V3020 nCS GPIO163 */
+ MUX_VAL(CP(UART3_CTS_RCTX), (IEN | PTU | EN | M4)); /*GPIO_163*/
+ /* SB-T35 Ethernet nRESET GPIO164 */
+ MUX_VAL(CP(UART3_RTS_SD), (IDIS | PTU | EN | M4)); /*GPIO_164*/
+
+ /* SB-T35 SD/MMC CD GPIO144 */
+ MUX_VAL(CP(UART2_CTS), (IEN | PTU | EN | M4)); /*GPIO_144*/
+ /* WIFI nRESET GPIO145 */
+ MUX_VAL(CP(UART2_RTS), (IEN | PTD | EN | M4)); /*GPIO_145*/
+ /* USB1 PHY Reset GPIO 146 */
+ MUX_VAL(CP(UART2_TX), (IEN | PTD | EN | M4)); /*GPIO_146*/
+ /* USB2 PHY Reset GPIO 147 */
+ MUX_VAL(CP(UART2_RX), (IEN | PTD | EN | M4)); /*GPIO_147*/
+
+ /* MMC1 */
+ MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0));
+
+ /* DSS */
+ MUX_VAL(CP(DSS_PCLK), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_HSYNC), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_VSYNC), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_ACBIAS), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA0), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA1), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA2), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA3), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA4), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA5), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA6), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA7), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA8), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA9), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA10), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA11), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA12), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA13), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA14), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA15), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA16), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA17), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA18), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA19), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA20), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA21), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA22), (IDIS | PTD | DIS | M0));
+ MUX_VAL(CP(DSS_DATA23), (IDIS | PTD | DIS | M0));
+
+ /* I2C */
+ MUX_VAL(CP(I2C1_SCL), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C1_SDA), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C3_SCL), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(I2C3_SDA), (IEN | PTU | EN | M0));
+
+ /* SB-T35 USB HUB Reset GPIO98 */
+ MUX_VAL(CP(CCDC_WEN), (IDIS | PTU | EN | M4)); /*GPIO_98*/
+ /* CM-T3517 USB HUB Reset GPIO152 */
+ MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M4)); /*GPIO_152*/
+
+ /* RMII */
+ MUX_VAL(CP(RMII_MDIO_DATA), (IEN | PTU | EN | M0));
+ MUX_VAL(CP(RMII_MDIO_CLK), (M0));
+ MUX_VAL(CP(RMII_RXD0), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(RMII_RXD1), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(RMII_CRS_DV), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(RMII_RXER), (IEN | PTD | DIS | M0));
+ MUX_VAL(CP(RMII_TXD0), (IDIS | M0));
+ MUX_VAL(CP(RMII_TXD1), (IDIS | M0));
+ MUX_VAL(CP(RMII_TXEN), (IDIS | M0));
+ MUX_VAL(CP(RMII_50MHZ_CLK), (IEN | PTU | DIS | M0));
+
+ /* Green LED GPIO186 */
+ MUX_VAL(CP(SYS_CLKOUT2), (IDIS | PTU | DIS | M4)); /*GPIO_186*/
+
+ /* SPI */
+ MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M1)); /*MCSPI4_CLK*/
+ MUX_VAL(CP(MCBSP1_DX), (IEN | PTD | DIS | M1)); /*MCSPI4_SIMO*/
+ MUX_VAL(CP(MCBSP1_DR), (IEN | PTD | DIS | M1)); /*MCSPI4_SOMI*/
+ MUX_VAL(CP(MCBSP1_FSX), (IEN | PTU | EN | M1)); /*MCSPI4_CS0*/
+ /* LCD reset GPIO157 */
+ MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)); /*GPIO_157*/
+
+ /* RTC V3020 CS Enable GPIO160 */
+ MUX_VAL(CP(MCBSP_CLKS), (IEN | PTD | EN | M4)); /*GPIO_160*/
+ /* SB-T35 LVDS Transmitter SHDN GPIO162 */
+ MUX_VAL(CP(MCBSP1_CLKX), (IEN | PTU | DIS | M4)); /*GPIO_162*/
+
+ /* USB0 - mUSB */
+ MUX_VAL(CP(USB0_DRVBUS), (IEN | PTD | EN | M0));
+ /* USB1 EHCI */
+ MUX_VAL(CP(ETK_D0_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT0*/
+ MUX_VAL(CP(ETK_D1_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT1*/
+ MUX_VAL(CP(ETK_D2_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT2*/
+ MUX_VAL(CP(ETK_D7_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT3*/
+ MUX_VAL(CP(ETK_D4_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT4*/
+ MUX_VAL(CP(ETK_D5_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT5*/
+ MUX_VAL(CP(ETK_D6_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT6*/
+ MUX_VAL(CP(ETK_D3_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DT7*/
+ MUX_VAL(CP(ETK_D8_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_DIR*/
+ MUX_VAL(CP(ETK_D9_ES2), (IEN | PTD | EN | M3)); /*HSUSB1_NXT*/
+ MUX_VAL(CP(ETK_CTL_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB1_CLK*/
+ MUX_VAL(CP(ETK_CLK_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB1_STP*/
+ /* USB2 EHCI */
+ MUX_VAL(CP(ETK_D14_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT0*/
+ MUX_VAL(CP(ETK_D15_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DT1*/
+ MUX_VAL(CP(MCSPI1_CS3), (IEN | PTD | EN | M3)); /*HSUSB2_DT2*/
+ MUX_VAL(CP(MCSPI2_CS1), (IEN | PTD | EN | M3)); /*HSUSB2_DT3*/
+ MUX_VAL(CP(MCSPI2_SIMO), (IEN | PTD | EN | M3)); /*HSUSB2_DT4*/
+ MUX_VAL(CP(MCSPI2_SOMI), (IEN | PTD | EN | M3)); /*HSUSB2_DT5*/
+ MUX_VAL(CP(MCSPI2_CS0), (IEN | PTD | EN | M3)); /*HSUSB2_DT6*/
+ MUX_VAL(CP(MCSPI2_CLK), (IEN | PTD | EN | M3)); /*HSUSB2_DT7*/
+ MUX_VAL(CP(ETK_D12_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_DIR*/
+ MUX_VAL(CP(ETK_D13_ES2), (IEN | PTD | EN | M3)); /*HSUSB2_NXT*/
+ MUX_VAL(CP(ETK_D10_ES2), (IDIS | PTD | DIS | M3)); /*HSUSB2_CLK*/
+ MUX_VAL(CP(ETK_D11_ES2), (IDIS | PTU | DIS | M3)); /*HSUSB2_STP*/
+
+ /* SYS_BOOT */
+ MUX_VAL(CP(SYS_BOOT0), (IEN | PTU | DIS | M4)); /*GPIO_2*/
+ MUX_VAL(CP(SYS_BOOT1), (IEN | PTU | DIS | M4)); /*GPIO_3*/
+ MUX_VAL(CP(SYS_BOOT2), (IEN | PTU | DIS | M4)); /*GPIO_4*/
+ MUX_VAL(CP(SYS_BOOT3), (IEN | PTU | DIS | M4)); /*GPIO_5*/
+ MUX_VAL(CP(SYS_BOOT4), (IEN | PTU | DIS | M4)); /*GPIO_6*/
+ MUX_VAL(CP(SYS_BOOT5), (IEN | PTU | DIS | M4)); /*GPIO_7*/
+}
diff --git a/board/compulab/cm_t54/cm_t54.c b/board/compulab/cm_t54/cm_t54.c
index 944b7234d63..b1a067d8816 100644
--- a/board/compulab/cm_t54/cm_t54.c
+++ b/board/compulab/cm_t54/cm_t54.c
@@ -100,16 +100,11 @@ uint mmc_get_env_part(struct mmc *mmc)
#define SB_T54_CD_GPIO 228
#define SB_T54_WP_GPIO 229
-int board_mmc_getcd(struct mmc *mmc)
-{
- return !gpio_get_value(SB_T54_CD_GPIO);
-}
-
int board_mmc_init(bd_t *bis)
{
int ret0, ret1;
- ret0 = omap_mmc_init(0, 0, 0, -1, SB_T54_WP_GPIO);
+ ret0 = omap_mmc_init(0, 0, 0, SB_T54_CD_GPIO, SB_T54_WP_GPIO);
if (ret0)
printf("cm_t54: failed to initialize mmc0\n");
diff --git a/board/compulab/common/Makefile b/board/compulab/common/Makefile
index 4044ac9d626..dbf0009652a 100644
--- a/board/compulab/common/Makefile
+++ b/board/compulab/common/Makefile
@@ -6,5 +6,8 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_SYS_I2C) += eeprom.o
-obj-$(CONFIG_LCD) += omap3_display.o
+obj-y += common.o
+obj-$(CONFIG_SYS_I2C) += eeprom.o
+obj-$(CONFIG_LCD) += omap3_display.o
+obj-$(CONFIG_SPLASH_SCREEN) += splash.o
+obj-$(CONFIG_SMC911X) += omap3_smc911x.o
diff --git a/board/compulab/common/common.c b/board/compulab/common/common.c
new file mode 100644
index 00000000000..b25d9a20b40
--- /dev/null
+++ b/board/compulab/common/common.c
@@ -0,0 +1,59 @@
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <asm/bootm.h>
+#include <asm/gpio.h>
+
+#include "common.h"
+#include "eeprom.h"
+
+void cl_print_pcb_info(void)
+{
+ u32 board_rev = get_board_rev();
+ u32 rev_major = board_rev / 100;
+ u32 rev_minor = board_rev - (rev_major * 100);
+
+ if ((rev_minor / 10) * 10 == rev_minor)
+ rev_minor = rev_minor / 10;
+
+ printf("PCB: %u.%u\n", rev_major, rev_minor);
+}
+
+#ifdef CONFIG_SERIAL_TAG
+void __weak get_board_serial(struct tag_serialnr *serialnr)
+{
+ /*
+ * This corresponds to what happens when we can communicate with the
+ * eeprom but don't get a valid board serial value.
+ */
+ serialnr->low = 0;
+ serialnr->high = 0;
+};
+#endif
+
+#ifdef CONFIG_CMD_USB
+int cl_usb_hub_init(int gpio, const char *label)
+{
+ if (gpio_request(gpio, label)) {
+ printf("Error: can't obtain GPIO%d for %s", gpio, label);
+ return -1;
+ }
+
+ gpio_direction_output(gpio, 0);
+ udelay(10);
+ gpio_set_value(gpio, 1);
+ udelay(1000);
+ return 0;
+}
+
+void cl_usb_hub_deinit(int gpio)
+{
+ gpio_free(gpio);
+}
+#endif
diff --git a/board/compulab/common/common.h b/board/compulab/common/common.h
new file mode 100644
index 00000000000..68ffb111dc3
--- /dev/null
+++ b/board/compulab/common/common.h
@@ -0,0 +1,47 @@
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef _CL_COMMON_
+#define _CL_COMMON_
+
+#include <asm/errno.h>
+
+void cl_print_pcb_info(void);
+
+#ifdef CONFIG_CMD_USB
+int cl_usb_hub_init(int gpio, const char *label);
+void cl_usb_hub_deinit(int gpio);
+#else /* !CONFIG_CMD_USB */
+static inline int cl_usb_hub_init(int gpio, const char *label)
+{
+ return -ENOSYS;
+}
+static inline void cl_usb_hub_deinit(int gpio) {}
+#endif /* CONFIG_CMD_USB */
+
+#ifdef CONFIG_SPLASH_SCREEN
+int cl_splash_screen_prepare(int nand_offset);
+#else /* !CONFIG_SPLASH_SCREEN */
+static inline int cl_splash_screen_prepare(int nand_offset)
+{
+ return -ENOSYS;
+}
+#endif /* CONFIG_SPLASH_SCREEN */
+
+#ifdef CONFIG_SMC911X
+int cl_omap3_smc911x_init(int id, int cs, u32 base_addr,
+ int (*reset)(int), int rst_gpio);
+#else /* !CONFIG_SMC911X */
+static inline int cl_omap3_smc911x_init(int id, int cs, u32 base_addr,
+ int (*reset)(int), int rst_gpio)
+{
+ return -ENOSYS;
+}
+#endif /* CONFIG_SMC911X */
+
+#endif /* _CL_COMMON_ */
diff --git a/board/compulab/common/eeprom.c b/board/compulab/common/eeprom.c
index 2df3adabf8b..a45e7be11f7 100644
--- a/board/compulab/common/eeprom.c
+++ b/board/compulab/common/eeprom.c
@@ -109,23 +109,27 @@ int cl_eeprom_read_mac_addr(uchar *buf)
return cl_eeprom_read(offset, buf, 6);
}
+static u32 board_rev;
+
/*
* Routine: cl_eeprom_get_board_rev
* Description: read system revision from eeprom
*/
u32 cl_eeprom_get_board_rev(void)
{
- u32 rev = 0;
char str[5]; /* Legacy representation can contain at most 4 digits */
uint offset = BOARD_REV_OFFSET_LEGACY;
+ if (board_rev)
+ return board_rev;
+
if (cl_eeprom_setup_layout())
return 0;
if (cl_eeprom_layout != LAYOUT_LEGACY)
offset = BOARD_REV_OFFSET;
- if (cl_eeprom_read(offset, (uchar *)&rev, BOARD_REV_SIZE))
+ if (cl_eeprom_read(offset, (uchar *)&board_rev, BOARD_REV_SIZE))
return 0;
/*
@@ -133,9 +137,9 @@ u32 cl_eeprom_get_board_rev(void)
* representation. i.e. for rev 1.00: 0x100 --> 0x64
*/
if (cl_eeprom_layout == LAYOUT_LEGACY) {
- sprintf(str, "%x", rev);
- rev = simple_strtoul(str, NULL, 10);
+ sprintf(str, "%x", board_rev);
+ board_rev = simple_strtoul(str, NULL, 10);
}
- return rev;
+ return board_rev;
};
diff --git a/board/compulab/common/omap3_smc911x.c b/board/compulab/common/omap3_smc911x.c
new file mode 100644
index 00000000000..45616619877
--- /dev/null
+++ b/board/compulab/common/omap3_smc911x.c
@@ -0,0 +1,93 @@
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <netdev.h>
+
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/mem.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/gpio.h>
+
+#include "common.h"
+
+static u32 cl_omap3_smc911x_gpmc_net_config[GPMC_MAX_REG] = {
+ NET_GPMC_CONFIG1,
+ NET_GPMC_CONFIG2,
+ NET_GPMC_CONFIG3,
+ NET_GPMC_CONFIG4,
+ NET_GPMC_CONFIG5,
+ NET_GPMC_CONFIG6,
+ 0
+};
+
+static void cl_omap3_smc911x_setup_net_chip_gmpc(int cs, u32 base_addr)
+{
+ struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
+
+ enable_gpmc_cs_config(cl_omap3_smc911x_gpmc_net_config,
+ &gpmc_cfg->cs[cs], base_addr, GPMC_SIZE_16M);
+
+ /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
+ writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
+
+ /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
+
+ /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
+ writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
+ &ctrl_base->gpmc_nadv_ale);
+}
+
+#ifdef CONFIG_OMAP_GPIO
+static int cl_omap3_smc911x_reset_net_chip(int gpio)
+{
+ int err;
+
+ if (!gpio_is_valid(gpio))
+ return -EINVAL;
+
+ err = gpio_request(gpio, "eth rst");
+ if (err)
+ return err;
+
+ /* Set gpio as output and send a pulse */
+ gpio_direction_output(gpio, 1);
+ udelay(1);
+ gpio_set_value(gpio, 0);
+ mdelay(40);
+ gpio_set_value(gpio, 1);
+ mdelay(1);
+
+ return 0;
+}
+#else /* !CONFIG_OMAP_GPIO */
+static inline int cl_omap3_smc911x_reset_net_chip(int gpio) { return 0; }
+#endif /* CONFIG_OMAP_GPIO */
+
+int cl_omap3_smc911x_init(int id, int cs, u32 base_addr,
+ int (*reset)(int), int rst_gpio)
+{
+ int ret;
+
+ cl_omap3_smc911x_setup_net_chip_gmpc(cs, base_addr);
+
+ if (reset)
+ reset(rst_gpio);
+ else
+ cl_omap3_smc911x_reset_net_chip(rst_gpio);
+
+ ret = smc911x_initialize(id, base_addr);
+ if (ret > 0)
+ return ret;
+
+ printf("Failed initializing SMC911x! ");
+ return 0;
+}
diff --git a/board/compulab/common/splash.c b/board/compulab/common/splash.c
new file mode 100644
index 00000000000..49ed49b81e9
--- /dev/null
+++ b/board/compulab/common/splash.c
@@ -0,0 +1,72 @@
+/*
+ * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il>
+ *
+ * Authors: Igor Grinberg <grinberg@compulab.co.il>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <bmp_layout.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CMD_NAND
+static int splash_load_from_nand(u32 bmp_load_addr, int nand_offset)
+{
+ struct bmp_header *bmp_hdr;
+ int res;
+ size_t bmp_size, bmp_header_size = sizeof(struct bmp_header);
+
+ if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp)
+ goto splash_address_too_high;
+
+ res = nand_read_skip_bad(&nand_info[nand_curr_device],
+ nand_offset, &bmp_header_size,
+ NULL, nand_info[nand_curr_device].size,
+ (u_char *)bmp_load_addr);
+ if (res < 0)
+ return res;
+
+ bmp_hdr = (struct bmp_header *)bmp_load_addr;
+ bmp_size = le32_to_cpu(bmp_hdr->file_size);
+
+ if (bmp_load_addr + bmp_size >= gd->start_addr_sp)
+ goto splash_address_too_high;
+
+ return nand_read_skip_bad(&nand_info[nand_curr_device],
+ nand_offset, &bmp_size,
+ NULL, nand_info[nand_curr_device].size,
+ (u_char *)bmp_load_addr);
+
+splash_address_too_high:
+ printf("Error: splashimage address too high. Data overwrites U-Boot "
+ "and/or placed beyond DRAM boundaries.\n");
+
+ return -1;
+}
+#else
+static inline int splash_load_from_nand(u32 bmp_load_addr, int nand_offset)
+{
+ return -1;
+}
+#endif /* CONFIG_CMD_NAND */
+
+int cl_splash_screen_prepare(int nand_offset)
+{
+ char *env_splashimage_value;
+ u32 bmp_load_addr;
+
+ env_splashimage_value = getenv("splashimage");
+ if (env_splashimage_value == NULL)
+ return -1;
+
+ bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16);
+ if (bmp_load_addr == 0) {
+ printf("Error: bad splashimage address specified\n");
+ return -1;
+ }
+
+ return splash_load_from_nand(bmp_load_addr, nand_offset);
+}
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-11 00:08:06 +0000