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-rw-r--r--board/freescale/mpc8548cds/law.c31
-rw-r--r--board/freescale/mpc8548cds/mpc8548cds.c8
-rw-r--r--board/freescale/mpc8548cds/tlb.c64
3 files changed, 38 insertions, 65 deletions
diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c
index 5b6943da9e6..efd90401c14 100644
--- a/board/freescale/mpc8548cds/law.c
+++ b/board/freescale/mpc8548cds/law.c
@@ -27,36 +27,9 @@
#include <asm/fsl_law.h>
#include <asm/mmu.h>
-/*
- * LAW(Local Access Window) configuration:
- *
- * 0x0000_0000 0x7fff_ffff DDR 2G
- * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
- * 0xa000_0000 0xbfff_ffff PCIe MEM 512M
- * 0xc000_0000 0xdfff_ffff RapidIO 512M
- * 0xe000_0000 0xe000_ffff CCSR 1M
- * 0xe200_0000 0xe10f_ffff PCI1 IO 1M
- * 0xe280_0000 0xe20f_ffff PCI2 IO 1M
- * 0xe300_0000 0xe30f_ffff PCIe IO 1M
- * 0xf000_0000 0xf3ff_ffff SDRAM 64M
- * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M
- * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M
- * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M
- *
- * Notes:
- * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window.
- * If flash is 8M at default position (last 8M), no LAW needed.
- *
- * LAW 0 is reserved for boot mapping
- */
-
struct law_entry law_table[] = {
-#ifdef CONFIG_SYS_PCI2_MEM_PHYS
- SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
- SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
-#endif
- /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
- SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+ /* LBC window - maps 256M */
+ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index 3bcaac48518..a8d57cdddef 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -50,10 +50,10 @@ int checkboard (void)
uint cpu_board_rev = get_cpu_board_revision ();
- printf ("Board: CDS Version 0x%02x, PCI Slot %d\n",
- get_board_version (), pci_slot);
-
- printf ("CPU Board Revision %d.%d (0x%04x)\n",
+ puts("Board: MPC8548CDS");
+ printf(" Carrier Rev: 0x%02x, PCI Slot %d\n",
+ get_board_version(), pci_slot);
+ printf(" Daughtercard Rev: %d.%d (0x%04x)\n",
MPC85XX_CPU_BOARD_MAJOR (cpu_board_rev),
MPC85XX_CPU_BOARD_MINOR (cpu_board_rev), cpu_board_rev);
/*
diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c
index b2c1b31af65..eb29e07165b 100644
--- a/board/freescale/mpc8548cds/tlb.c
+++ b/board/freescale/mpc8548cds/tlb.c
@@ -41,63 +41,63 @@ struct fsl_e_tlb_entry tlb_table[] = {
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 0, BOOKE_PAGESZ_4K, 0),
+ /* TLB 1 */
/*
- * TLB 0: 16M Non-cacheable, guarded
- * 0xff000000 16M FLASH
- * Out of reset this entry is only 4K.
+ * Entry 0:
+ * FLASH(cover boot page) 16M Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_BOOT_BLOCK, CONFIG_SYS_BOOT_BLOCK,
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 0, BOOKE_PAGESZ_16M, 1),
/*
- * TLB 1: 1G Non-cacheable, guarded
- * 0x80000000 1G PCI1/PCIE 8,9,a,b
+ * Entry 1:
+ * CCSRBAR 1M Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 1, BOOKE_PAGESZ_1G, 1),
+ 0, 1, BOOKE_PAGESZ_1M, 1),
/*
- * TLB 2: 256M Non-cacheable, guarded
+ * Entry 2:
+ * LBC SDRAM 64M Cacheable, non-guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT, CONFIG_SYS_SRIO1_MEM_PHYS,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 2, BOOKE_PAGESZ_256M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE,
+ CONFIG_SYS_LBC_SDRAM_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, 0,
+ 0, 2, BOOKE_PAGESZ_64M, 1),
/*
- * TLB 3: 256M Non-cacheable, guarded
+ * Entry 3:
+ * CADMUS registers 1M Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_SRIO1_MEM_VIRT + 0x10000000, CONFIG_SYS_SRIO1_MEM_PHYS + 0x10000000,
+ SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 3, BOOKE_PAGESZ_256M, 1),
+ 0, 3, BOOKE_PAGESZ_1M, 1),
/*
- * TLB 5: 64M Non-cacheable, guarded
- * 0xe000_0000 1M CCSRBAR
- * 0xe200_0000 1M PCI1 IO
- * 0xe210_0000 1M PCI2 IO
- * 0xe300_0000 1M PCIe IO
+ * Entry 4:
+ * PCI and PCIe MEM 1G Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 5, BOOKE_PAGESZ_64M, 1),
+ 0, 4, BOOKE_PAGESZ_1G, 1),
/*
- * TLB 6: 64M Cacheable, non-guarded
- * 0xf000_0000 64M LBC SDRAM
+ * Entry 5:
+ * PCI1 IO 1M Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_LBC_CACHE_BASE, CONFIG_SYS_LBC_CACHE_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, 0,
- 0, 6, BOOKE_PAGESZ_64M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 5, BOOKE_PAGESZ_1M, 1),
/*
- * TLB 7: 64M Non-cacheable, guarded
- * 0xf8000000 64M CADMUS registers, relocated L2SRAM
+ * Entry 6:
+ * PCIe IO 1M Non-cacheable, guarded
*/
- SET_TLB_ENTRY(1, CONFIG_SYS_LBC_NONCACHE_BASE, CONFIG_SYS_LBC_NONCACHE_BASE,
- MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_64M, 1),
+ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
+ MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 6, BOOKE_PAGESZ_1M, 1),
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-15 11:39:38 +0000