diff options
Diffstat (limited to 'board/phytec/phycore_am64x/phycore-am64x.c')
-rw-r--r-- | board/phytec/phycore_am64x/phycore-am64x.c | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/board/phytec/phycore_am64x/phycore-am64x.c b/board/phytec/phycore_am64x/phycore-am64x.c new file mode 100644 index 00000000000..8f3b22657c7 --- /dev/null +++ b/board/phytec/phycore_am64x/phycore-am64x.c @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2021 PHYTEC America, LLC - https://www.phytec.com + * Author: Matt McKee <mmckee@phytec.com> + * + * Copyright (C) 2022 - 2024 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov <w.egorov@phytec.de> + */ + +#include <asm/io.h> +#include <env.h> +#include <env_internal.h> +#include <spl.h> +#include <fdt_support.h> +#include <asm/arch/hardware.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ + return 0; +} + +int dram_init(void) +{ + return fdtdec_setup_mem_size_base(); +} + +int dram_init_banksize(void) +{ + return fdtdec_setup_memory_banksize(); +} + +#define CTRLMMR_USB0_PHY_CTRL 0x43004008 +#define CORE_VOLTAGE 0x80000000 + +#ifdef CONFIG_SPL_BOARD_INIT +void spl_board_init(void) +{ + u32 val; + + /* Set USB PHY core voltage to 0.85V */ + val = readl(CTRLMMR_USB0_PHY_CTRL); + val &= ~(CORE_VOLTAGE); + writel(val, CTRLMMR_USB0_PHY_CTRL); + + /* Init DRAM size for R5/A53 SPL */ + dram_init_banksize(); +} +#endif |