5 files changed, 195 insertions, 0 deletions
diff --git a/board/sysam/stmark2/Kconfig b/board/sysam/stmark2/Kconfig
new file mode 100644
index 00000000000..87ab7ab7b52
--- /dev/null
+++ b/board/sysam/stmark2/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_STMARK2
+
+config SYS_CPU
+	default "mcf5445x"
+
+config SYS_BOARD
+	default "stmark2"
+
+config SYS_VENDOR
+	default "sysam"
+
+config SYS_CONFIG_NAME
+	default "stmark2"
+
+endif
diff --git a/board/sysam/stmark2/MAINTAINERS b/board/sysam/stmark2/MAINTAINERS
new file mode 100644
index 00000000000..b87f432bb3f
--- /dev/null
+++ b/board/sysam/stmark2/MAINTAINERS
@@ -0,0 +1,6 @@
+STMARK2 BOARD
+M:	Angelo Dureghello <angelo@sysam.it>
+S:	Maintained
+F:	board/sysam/stmark2/
+F:	include/configs/stmark2.h
+F:	configs/stmark2_defconfig
diff --git a/board/sysam/stmark2/Makefile b/board/sysam/stmark2/Makefile
new file mode 100644
index 00000000000..064a57ea05e
--- /dev/null
+++ b/board/sysam/stmark2/Makefile
@@ -0,0 +1,8 @@
+#
+# (C) Copyright 2014  Angelo Dureghello <angelo@sysam.it>
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y = stmark2.o
+extra-y += sbf_dram_init.o
diff --git a/board/sysam/stmark2/sbf_dram_init.S b/board/sysam/stmark2/sbf_dram_init.S
new file mode 100644
index 00000000000..52abda5c3c4
--- /dev/null
+++ b/board/sysam/stmark2/sbf_dram_init.S
@@ -0,0 +1,119 @@
+/*
+ * Board-specific early ddr/sdram init.
+ *
+ * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+.equ	PPMCR0, 	0xfc04002d
+.equ	MSCR_SDRAMC,	0xec094060
+.equ	MISCCR2,	0xec09001a
+.equ	DDR_RCR,	0xfc0b8180
+.equ	DDR_PADCR,	0xfc0b81ac
+.equ	DDR_CR00,	0xfc0b8000
+.equ	DDR_CR06,	0xfc0b8018
+.equ	DDR_CR09,	0xfc0b8024
+.equ	DDR_CR40,	0xfc0b80a0
+.equ	DDR_CR45,	0xfc0b80b4
+.equ	DDR_CR56,	0xfc0b80e0
+
+.global sbf_dram_init
+.text
+
+sbf_dram_init:
+	/* CD46 = DDR on */
+	move.l	#PPMCR0, %a1
+	move.b	#46, (%a1)
+
+	/* stmark 2, max drive strength */
+	move.l	#MSCR_SDRAMC, %a1
+	move.b	#1, (%a1)
+
+	/*
+	 * use cpu clock, seems more realiable
+	 *
+	 * DDR2 clock is serviced from DDR controller as input clock / 2
+	 * so, if clock comes from
+	 *   vco, i.e. 480(vco) / 2, so ddr clock is 240 Mhz (measured)
+	 *   cpu, i.e. 250(cpu) / 2, so ddr clock is 125 Mhz (measured)
+	 *
+	 *     .
+	 *    / \    DDR2 can't be clocked lower than 125Mhz
+	 *   / ! \   DDR2 init must pass further i/dcache enable test
+	 *  /_____\
+	 *  WARNING
+	 */
+
+	/* cpu / 2 = 125 Mhz for 480 Mhz pll */
+	move.l	#MISCCR2, %a1
+	move.w	#0xa01d, (%a1)
+
+	/* DDR force sw reset settings */
+	move.l	#DDR_RCR, %a1
+	move.l	#0x00000000, (%a1)
+	move.l	#0x40000000, (%a1)
+
+	/*
+	 * PAD_ODT_CS: for us seems both 1(75 ohm) and 2(150ohm) are good,
+	 * 500/700 mV are ok
+	 */
+	move.l	#DDR_PADCR, %a1
+	move.l	#0x01030203, (%a1)	/* as freescale tower */
+
+	move.l	#DDR_CR00, %a1
+	move.l	#0x01010101, (%a1)+	/* 0x00 */
+	move.l	#0x00000101, (%a1)+	/* 0x04 */
+	move.l	#0x01010100, (%a1)+	/* 0x08 */
+	move.l	#0x01010000, (%a1)+	/* 0x0C */
+	move.l	#0x00010101, (%a1)+	/* 0x10 */
+	move.l	#DDR_CR06, %a1
+	move.l	#0x00010100, (%a1)+	/* 0x18 */
+	move.l	#0x00000001, (%a1)+	/* 0x1C */
+	move.l	#0x01000001, (%a1)+	/* 0x20 */
+	move.l	#0x00000100, (%a1)+	/* 0x24 */
+	move.l	#0x00010001, (%a1)+	/* 0x28 */
+	move.l	#0x00000200, (%a1)+	/* 0x2C */
+	move.l	#0x01000002, (%a1)+	/* 0x30 */
+	move.l	#0x00000000, (%a1)+	/* 0x34 */
+	move.l	#0x00000100, (%a1)+	/* 0x38 */
+	move.l	#0x02000100, (%a1)+	/* 0x3C */
+	move.l	#0x02000407, (%a1)+	/* 0x40 */
+	move.l	#0x02030007, (%a1)+	/* 0x44 */
+	move.l	#0x02000100, (%a1)+	/* 0x48 */
+	move.l	#0x0A030203, (%a1)+	/* 0x4C */
+	move.l	#0x00020708, (%a1)+	/* 0x50 */
+	move.l	#0x00050008, (%a1)+	/* 0x54 */
+	move.l	#0x04030002, (%a1)+	/* 0x58 */
+	move.l	#0x00000004, (%a1)+	/* 0x5C */
+	move.l	#0x020A0000, (%a1)+	/* 0x60 */
+	move.l	#0x0C00000E, (%a1)+	/* 0x64 */
+	move.l	#0x00002004, (%a1)+	/* 0x68 */
+	move.l	#0x00000000, (%a1)+	/* 0x6C */
+	move.l	#0x00100010, (%a1)+	/* 0x70 */
+	move.l	#0x00100010, (%a1)+	/* 0x74 */
+	move.l	#0x00000000, (%a1)+	/* 0x78 */
+	move.l	#0x07990000, (%a1)+	/* 0x7C */
+	move.l	#DDR_CR40, %a1
+	move.l	#0x00000000, (%a1)+	/* 0xA0 */
+	move.l	#0x00C80064, (%a1)+	/* 0xA4 */
+	move.l	#0x44520002, (%a1)+	/* 0xA8 */
+	move.l	#0x00C80023, (%a1)+	/* 0xAC */
+	move.l	#DDR_CR45, %a1
+	move.l	#0x0000C350, (%a1)	/* 0xB4 */
+	move.l	#DDR_CR56, %a1
+	move.l	#0x04000000, (%a1)+	/* 0xE0 */
+	move.l	#0x03000304, (%a1)+	/* 0xE4 */
+	move.l	#0x40040000, (%a1)+	/* 0xE8 */
+	move.l	#0xC0004004, (%a1)+	/* 0xEC */
+	move.l	#0x0642C000, (%a1)+	/* 0xF0 */
+	move.l	#0x00000642, (%a1)+	/* 0xF4 */
+	move.l	#DDR_CR09, %a1
+	tpf
+	move.l	#0x01000100, (%a1)	/* 0x24 */
+
+	move.l	#0x2000, %d1
+	bsr	asm_delay
+
+
+	rts
diff --git a/board/sysam/stmark2/stmark2.c b/board/sysam/stmark2/stmark2.c
new file mode 100644
index 00000000000..4f291ab6d64
--- /dev/null
+++ b/board/sysam/stmark2/stmark2.c
@@ -0,0 +1,47 @@
+/*
+ * Board-specific init.
+ *
+ * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <spi.h>
+#include <asm/io.h>
+#include <asm/immap.h>
+#include <mmc.h>
+#include <fsl_esdhc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	/*
+	 * need to to:
+	 * Check serial flash size. if 2mb evb, else 8mb demo
+	 */
+	puts("Board: ");
+	puts("Sysam stmark2\n");
+	return 0;
+}
+
+int dram_init(void)
+{
+	u32 dramsize;
+
+	/*
+	 * Serial Boot: The dram is already initialized in start.S
+	 * only require to return DRAM size
+	 */
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
+
+	gd->ram_size = dramsize;
+
+	return 0;
+}
+
+int testdram(void)
+{
+	return 0;
+}