diff options
Diffstat (limited to 'board/w7o')
| -rw-r--r-- | board/w7o/init.S | 10 | ||||
| -rw-r--r-- | board/w7o/w7o.c | 36 |
2 files changed, 23 insertions, 23 deletions
diff --git a/board/w7o/init.S b/board/w7o/init.S index 090b07a1e62..5477f986b98 100644 --- a/board/w7o/init.S +++ b/board/w7o/init.S @@ -182,7 +182,7 @@ sdram_init: * Disable memory controller to allow * values to be changed. */ - addi r3, 0, mem_mcopt1 + addi r3, 0, SDRAM0_CFG mtdcr SDRAM0_CFGADDR, r3 addis r4, 0, 0x0 ori r4, r4, 0x0 @@ -192,7 +192,7 @@ sdram_init: * Set MB0CF for ext bank 0. (0-4MB) Address Mode 5 since 11x8x2 * All other banks are disabled. */ - addi r3, 0, mem_mb0cf + addi r3, 0, SDRAM0_B0CR mtdcr SDRAM0_CFGADDR, r3 addis r4, 0, 0x0000 /* BA=0x0, SZ=4MB */ ori r4, r4, 0x8001 /* Mode is 5, 11x8x2or4, BE=Enabled */ @@ -222,7 +222,7 @@ sdram_init: /* * Set up SDTR1 */ - addi r3, 0, mem_sdtr1 + addi r3, 0, SDRAM0_TR mtdcr SDRAM0_CFGADDR, r3 addis r4, 0, 0x0086 /* SDTR1 value for 100Mhz */ ori r4, r4, 0x400D @@ -231,7 +231,7 @@ sdram_init: /* * Set RTR */ - addi r3, 0, mem_rtr + addi r3, 0, SDRAM0_RTR mtdcr SDRAM0_CFGADDR, r3 addis r4, 0, 0x05F0 /* RTR refresh val = 15.625ms@100Mhz */ mtdcr SDRAM0_CFGDATA, r4 @@ -250,7 +250,7 @@ sdram_init: /******************************************************************** * Set memory controller options reg, MCOPT1. *******************************************************************/ - addi r3, 0, mem_mcopt1 + addi r3, 0, SDRAM0_CFG mtdcr SDRAM0_CFGADDR, r3 addis r4, 0, 0x80E0 /* DC_EN=1,SRE=0,PME=0,MEMCHK=0 */ ori r4, r4, 0x0000 /* REGEN=0,DRW=00,BRPF=01,ECCDD=1 */ diff --git a/board/w7o/w7o.c b/board/w7o/w7o.c index 6479beeb13b..a818808ba08 100644 --- a/board/w7o/w7o.c +++ b/board/w7o/w7o.c @@ -64,16 +64,16 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) Level One PHY; active low; level sensitive * IRQ 31 (EXT IRQ 6) SAM 1; active high; level sensitive */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0, + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ #elif defined(CONFIG_W7OLMC) /* @@ -95,16 +95,16 @@ int board_early_init_f (void) * IRQ 30 (EXT IRQ 5) RCMM Reset; active low; level sensitive * IRQ 31 (EXT IRQ 6) PHY; active high; level sensitive */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ - mtdcr (uicer, 0x00000000); /* disable all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0ER, 0x00000000); /* disable all ints */ - mtdcr (uiccr, 0x00000000); /* set all to be non-critical */ - mtdcr (uicpr, 0xFFFFFF80); /* set int polarities */ - mtdcr (uictr, 0x10000000); /* set int trigger levels */ - mtdcr (uicvcr, 0x00000001); /* set vect base=0, + mtdcr (UIC0CR, 0x00000000); /* set all to be non-critical */ + mtdcr (UIC0PR, 0xFFFFFF80); /* set int polarities */ + mtdcr (UIC0TR, 0x10000000); /* set int trigger levels */ + mtdcr (UIC0VCR, 0x00000001); /* set vect base=0, INT0 highest priority */ - mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr (UIC0SR, 0xFFFFFFFF); /* clear all ints */ #else /* Unknown */ # error "Unknown W7O board configuration" @@ -170,16 +170,16 @@ unsigned long get_dram_size (void) int size = 0; /* Get bank Size registers */ - mtdcr (SDRAM0_CFGADDR, mem_mb0cf); /* get bank 0 config reg */ + mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR); /* get bank 0 config reg */ regs[0] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, mem_mb1cf); /* get bank 1 config reg */ + mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR); /* get bank 1 config reg */ regs[1] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, mem_mb2cf); /* get bank 2 config reg */ + mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR); /* get bank 2 config reg */ regs[2] = mfdcr (SDRAM0_CFGDATA); - mtdcr (SDRAM0_CFGADDR, mem_mb3cf); /* get bank 3 config reg */ + mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR); /* get bank 3 config reg */ regs[3] = mfdcr (SDRAM0_CFGDATA); /* compute the size, add each bank if enabled */ |