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-rw-r--r--board/amcc/sequoia/sequoia.c9
-rw-r--r--board/amcc/sequoia/sequoia.h67
-rw-r--r--board/esd/cpci405/cpci405.c48
-rw-r--r--board/freescale/mpc8544ds/Makefile6
-rw-r--r--board/hermes/hermes.c1
-rw-r--r--board/logodl/logodl.c1
-rw-r--r--board/lwmon5/lwmon5.c17
-rw-r--r--board/lwmon5/sdram.c64
-rw-r--r--board/mpc8560ads/mpc8560ads.c26
-rw-r--r--board/pcs440ep/config.mk3
-rw-r--r--board/pcs440ep/flash.c4
-rw-r--r--board/pcs440ep/init.S41
-rw-r--r--board/pcs440ep/pcs440ep.c495
-rw-r--r--board/pcs440ep/u-boot.lds1
-rw-r--r--board/sc520_cdp/sc520_cdp.c1
-rw-r--r--board/sc520_spunk/sc520_spunk.c1
-rw-r--r--board/stxssa/stxssa.c274
17 files changed, 791 insertions, 268 deletions
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index b4376539503..f823117687e 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -25,7 +25,6 @@
#include <common.h>
#include <asm/processor.h>
#include <ppc440.h>
-#include "sequoia.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -226,7 +225,7 @@ int misc_init_r(void)
if (act == NULL || strcmp(act, "hostdev") == 0) {
/* SDR Setting */
mfsdr(SDR0_PFC1, sdr0_pfc1);
- mfsdr(SDR0_USB0, usb2d0cr);
+ mfsdr(SDR0_USB2D0CR, usb2d0cr);
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mfsdr(SDR0_USB2H0CR, usb2h0cr);
@@ -254,7 +253,7 @@ int misc_init_r(void)
sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL; /*0*/
mtsdr(SDR0_PFC1, sdr0_pfc1);
- mtsdr(SDR0_USB0, usb2d0cr);
+ mtsdr(SDR0_USB2D0CR, usb2d0cr);
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mtsdr(SDR0_USB2H0CR, usb2h0cr);
@@ -298,7 +297,7 @@ int misc_init_r(void)
/* SDR Setting */
mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
mfsdr(SDR0_USB2H0CR, usb2h0cr);
- mfsdr(SDR0_USB0, usb2d0cr);
+ mfsdr(SDR0_USB2D0CR, usb2d0cr);
mfsdr(SDR0_PFC1, sdr0_pfc1);
usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
@@ -323,7 +322,7 @@ int misc_init_r(void)
mtsdr(SDR0_USB2H0CR, usb2h0cr);
mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
- mtsdr(SDR0_USB0, usb2d0cr);
+ mtsdr(SDR0_USB2D0CR, usb2d0cr);
mtsdr(SDR0_PFC1, sdr0_pfc1);
/*clear resets*/
diff --git a/board/amcc/sequoia/sequoia.h b/board/amcc/sequoia/sequoia.h
deleted file mode 100644
index 1d44b164649..00000000000
--- a/board/amcc/sequoia/sequoia.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * (C) Copyright 2006
- * Stefan Roese, DENX Software Engineering, sr@denx.de.
- *
- * (C) Copyright 2006
- * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
- * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-
-/*----------------------------------------------------------------------------+
- | EBC Configuration Register - EBC0_CFG
- +----------------------------------------------------------------------------*/
-/* External Bus Three-State Control */
-#define EBC0_CFG_EBTC_DRIVEN 0x80000000
-/* Device-Paced Time-out Disable */
-#define EBC0_CFG_PTD_ENABLED 0x00000000
-/* Ready Timeout Count */
-#define EBC0_CFG_RTC_MASK 0x38000000
-#define EBC0_CFG_RTC_16PERCLK 0x00000000
-#define EBC0_CFG_RTC_32PERCLK 0x08000000
-#define EBC0_CFG_RTC_64PERCLK 0x10000000
-#define EBC0_CFG_RTC_128PERCLK 0x18000000
-#define EBC0_CFG_RTC_256PERCLK 0x20000000
-#define EBC0_CFG_RTC_512PERCLK 0x28000000
-#define EBC0_CFG_RTC_1024PERCLK 0x30000000
-#define EBC0_CFG_RTC_2048PERCLK 0x38000000
-/* External Master Priority Low */
-#define EBC0_CFG_EMPL_LOW 0x00000000
-#define EBC0_CFG_EMPL_MEDIUM_LOW 0x02000000
-#define EBC0_CFG_EMPL_MEDIUM_HIGH 0x04000000
-#define EBC0_CFG_EMPL_HIGH 0x06000000
-/* External Master Priority High */
-#define EBC0_CFG_EMPH_LOW 0x00000000
-#define EBC0_CFG_EMPH_MEDIUM_LOW 0x00800000
-#define EBC0_CFG_EMPH_MEDIUM_HIGH 0x01000000
-#define EBC0_CFG_EMPH_HIGH 0x01800000
-/* Chip Select Three-State Control */
-#define EBC0_CFG_CSTC_DRIVEN 0x00400000
-/* Burst Prefetch */
-#define EBC0_CFG_BPF_ONEDW 0x00000000
-#define EBC0_CFG_BPF_TWODW 0x00100000
-#define EBC0_CFG_BPF_FOURDW 0x00200000
-/* External Master Size */
-#define EBC0_CFG_EMS_8BIT 0x00000000
-/* Power Management Enable */
-#define EBC0_CFG_PME_DISABLED 0x00000000
-#define EBC0_CFG_PME_ENABLED 0x00020000
-/* Power Management Timer */
-#define EBC0_CFG_PMT_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12)
-
-#define SDR0_USB0 0x0320 /* USB Control Register */
diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c
index 58f792e2e4a..69cb8cef562 100644
--- a/board/esd/cpci405/cpci405.c
+++ b/board/esd/cpci405/cpci405.c
@@ -31,7 +31,7 @@
DECLARE_GLOBAL_DATA_PTR;
-extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /*cmd_boot.c*/
+extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); /*cmd_boot.c*/
#if 0
#define FPGA_DEBUG
#endif
@@ -109,10 +109,10 @@ int board_early_init_f (void)
/*
* First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
*/
- out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
- out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
+ out32(GPIO0_ODR, 0x00000000); /* no open drain pins */
+ out32(GPIO0_TCR, CFG_FPGA_PRG); /* setup for output */
out32(GPIO0_OR, CFG_FPGA_PRG); /* set output pins to high */
- out32(GPIO0_OR, 0); /* pull prg low */
+ out32(GPIO0_OR, 0); /* pull prg low */
/*
* Boot onboard FPGA
@@ -174,21 +174,21 @@ int board_early_init_f (void)
* IRQ 30 (EXT IRQ 5) PCI SLOT 3; active low; level sensitive
* IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
*/
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
- mtdcr(uicer, 0x00000000); /* disable all ints */
- mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(uicer, 0x00000000); /* disable all ints */
+ mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
#ifdef CONFIG_CPCI405_6U
if (cpci405_version() == 3) {
- mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
+ mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
} else {
- mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
+ mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
}
#else
- mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
+ mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
#endif
- mtdcr(uictr, 0x10000000); /* set int trigger levels */
- mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
- mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
+ mtdcr(uictr, 0x10000000); /* set int trigger levels */
+ mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
+ mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
return 0;
}
@@ -198,22 +198,22 @@ int board_early_init_f (void)
int ctermm2(void)
{
#ifdef CONFIG_CPCI405_VER2
- return 0; /* no, board is cpci405 */
+ return 0; /* no, board is cpci405 */
#else
if ((*(unsigned char *)0xf0000400 == 0x00) &&
(*(unsigned char *)0xf0000401 == 0x01))
- return 0; /* no, board is cpci405 */
+ return 0; /* no, board is cpci405 */
else
- return -1; /* yes, board is cterm-m2 */
+ return -1; /* yes, board is cterm-m2 */
#endif
}
int cpci405_host(void)
{
if (mfdcr(strap) & PSR_PCI_ARBIT_EN)
- return -1; /* yes, board is cpci405 host */
+ return -1; /* yes, board is cpci405 host */
else
- return 0; /* no, board is cpci405 adapter */
+ return 0; /* no, board is cpci405 adapter */
}
int cpci405_version(void)
@@ -228,8 +228,8 @@ int cpci405_version(void)
mtdcr(cntrl0, cntrl0Reg | 0x03000000);
out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
- udelay(1000); /* wait some time before reading input */
- value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
+ udelay(1000); /* wait some time before reading input */
+ value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
/*
* Restore GPIO settings
@@ -478,7 +478,7 @@ int checkboard (void)
}
#ifndef CONFIG_CPCI405_VER2
- puts ("\nFPGA: ");
+ puts ("\nFPGA: ");
/* display infos on fpgaimage */
index = 15;
@@ -574,11 +574,11 @@ int pci_pre_init(struct pci_controller *hose)
#ifdef CONFIG_CPCI405AB
-#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
+#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
|= CFG_FPGA_MODE_1WIRE_DIR)
-#define ONE_WIRE_SET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
+#define ONE_WIRE_SET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
&= ~CFG_FPGA_MODE_1WIRE_DIR)
-#define ONE_WIRE_GET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_STATUS) \
+#define ONE_WIRE_GET (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_STATUS) \
& CFG_FPGA_MODE_1WIRE)
/*
diff --git a/board/freescale/mpc8544ds/Makefile b/board/freescale/mpc8544ds/Makefile
index bec21686391..308f707de03 100644
--- a/board/freescale/mpc8544ds/Makefile
+++ b/board/freescale/mpc8544ds/Makefile
@@ -24,9 +24,9 @@
include $(TOPDIR)/config.mk
-# ifneq ($(OBJTREE),$(SRCTREE))
-# $(shell mkdir -p $(obj)./common)
-# endif
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
LIB = $(obj)lib$(BOARD).a
diff --git a/board/hermes/hermes.c b/board/hermes/hermes.c
index a523db1a487..8fd081fef3a 100644
--- a/board/hermes/hermes.c
+++ b/board/hermes/hermes.c
@@ -597,6 +597,7 @@ void show_boot_progress (int status)
{
volatile immap_t *immr = (immap_t *) CFG_IMMR;
+ if (status < -32) status = -1; /* let things compatible */
status ^= 0x0F;
status = (status & 0x0F) << 14;
immr->im_cpm.cp_pbdat = (immr->im_cpm.cp_pbdat & ~PB_LED_ALL) | status;
diff --git a/board/logodl/logodl.c b/board/logodl/logodl.c
index 14fd28f56fc..897787bcf7a 100644
--- a/board/logodl/logodl.c
+++ b/board/logodl/logodl.c
@@ -107,6 +107,7 @@ void logodl_set_led(int led, int state)
void show_boot_progress (int status)
{
+ if (status < -32) status = -1; /* let things compatible */
/*
switch(status) {
case 1: logodl_set_led(0,1); break;
diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c
index d5b8f8c81ba..d916284753d 100644
--- a/board/lwmon5/lwmon5.c
+++ b/board/lwmon5/lwmon5.c
@@ -19,9 +19,10 @@
*/
#include <common.h>
-#include <asm/processor.h>
#include <ppc440.h>
+#include <asm/processor.h>
#include <asm/gpio.h>
+#include <asm/io.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -220,6 +221,13 @@ int misc_init_r(void)
udelay(500);
gpio_write_bit(CFG_GPIO_LIME_RST, 1);
+ /* Lime memory clock adjusted to 133MHz */
+ out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_133MHZ);
+ /* Wait untill time expired. Because of requirements in lime manual */
+ udelay(300);
+ /* Write lime controller memory parameters */
+ out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE);
+
/*
* Reset PHY's
*/
@@ -229,13 +237,6 @@ int misc_init_r(void)
gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
- /*
- * Reset USB hub
- */
- gpio_write_bit(CFG_GPIO_HUB_RST, 0);
- udelay(100);
- gpio_write_bit(CFG_GPIO_HUB_RST, 1);
-
return 0;
}
diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c
index 85811adadf9..9a4a8eea8fb 100644
--- a/board/lwmon5/sdram.c
+++ b/board/lwmon5/sdram.c
@@ -474,8 +474,27 @@ static void program_ecc(u32 start_address,
blank_string(strlen(str));
} else {
/* ECC bit set method for cached memory */
+#if 1 /* test-only: will remove this define later, when ECC problems are solved! */
+ /*
+ * Some boards (like lwmon5) need to preserve the memory
+ * content upon ECC generation (for the log-buffer).
+ * Therefore we don't fill the memory with a pattern or
+ * just zero it, but write the same values back that are
+ * already in the memory cells.
+ */
+ address_increment = CFG_CACHELINE_SIZE;
+ end_address = current_address + num_bytes;
+
+ current_address = start_address;
+ while (current_address < end_address) {
+ ppcDcbi(current_address);
+ ppcDcbf(current_address);
+ current_address += CFG_CACHELINE_SIZE;
+ }
+#else
dcbz_area(start_address, num_bytes);
dflush();
+#endif
}
sync();
@@ -518,6 +537,8 @@ long int initdram (int board_type)
{
u32 val;
+#if 0 /* test-only: will remove this define later, when ECC problems are solved! */
+ /* CL=3 */
mtsdram(DDR0_02, 0x00000000);
mtsdram(DDR0_00, 0x0000190A);
@@ -558,6 +579,49 @@ long int initdram (int board_type)
mtsdram(DDR0_43, 0x030A0200);
mtsdram(DDR0_44, 0x00000003);
mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
+#else
+ /* CL=4 */
+ mtsdram(DDR0_02, 0x00000000);
+
+ mtsdram(DDR0_00, 0x0000190A);
+ mtsdram(DDR0_01, 0x01000000);
+ mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */
+
+ mtsdram(DDR0_04, 0x0B030300);
+ mtsdram(DDR0_05, 0x02020308);
+ mtsdram(DDR0_06, 0x0003C812);
+ mtsdram(DDR0_07, 0x00090100);
+ mtsdram(DDR0_08, 0x03c80001);
+ mtsdram(DDR0_09, 0x00011D5F);
+ mtsdram(DDR0_10, 0x00000300);
+ mtsdram(DDR0_11, 0x000CC800);
+ mtsdram(DDR0_12, 0x00000003);
+ mtsdram(DDR0_14, 0x00000000);
+ mtsdram(DDR0_17, 0x1e000000);
+ mtsdram(DDR0_18, 0x1e1e1e1e);
+ mtsdram(DDR0_19, 0x1e1e1e1e);
+ mtsdram(DDR0_20, 0x0B0B0B0B);
+ mtsdram(DDR0_21, 0x0B0B0B0B);
+#ifdef CONFIG_DDR_ECC
+ mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */
+#else
+ mtsdram(DDR0_22, 0x00267F0B);
+#endif
+
+ mtsdram(DDR0_23, 0x01000000);
+ mtsdram(DDR0_24, 0x01010001);
+
+ mtsdram(DDR0_26, 0x2D93028A);
+ mtsdram(DDR0_27, 0x0784682B);
+
+ mtsdram(DDR0_28, 0x00000080);
+ mtsdram(DDR0_31, 0x00000000);
+ mtsdram(DDR0_42, 0x01000008);
+
+ mtsdram(DDR0_43, 0x050A0200);
+ mtsdram(DDR0_44, 0x00000005);
+ mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */
+#endif
wait_for_dlllock();
diff --git a/board/mpc8560ads/mpc8560ads.c b/board/mpc8560ads/mpc8560ads.c
index d19bad68353..41acb97af7e 100644
--- a/board/mpc8560ads/mpc8560ads.c
+++ b/board/mpc8560ads/mpc8560ads.c
@@ -550,8 +550,34 @@ pci_init_board(void)
#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
void
+ft_soc_setup(void *blob, bd_t *bd)
+{
+ u32 *p;
+ int len;
+ ulong data;
+
+ p = ft_get_prop(blob, "/" OF_SOC "/cpm@e0000000/brg-frequency", &len);
+
+ if (p != NULL)
+ *p = cpu_to_be32(bd->bi_brgfreq);
+
+ p = ft_get_prop(blob,
+ "/" OF_SOC "/cpm@e0000000/scc@91a00/current-speed",
+ &len);
+ if (p != NULL)
+ *p = cpu_to_be32(bd->bi_baudrate);
+
+ p = ft_get_prop(blob,
+ "/" OF_SOC "/cpm@e0000000/scc@91a20/current-speed",
+ &len);
+ if (p != NULL)
+ *p = cpu_to_be32(bd->bi_baudrate);
+}
+
+void
ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
+ ft_soc_setup(blob, bd);
}
#endif
diff --git a/board/pcs440ep/config.mk b/board/pcs440ep/config.mk
index 319c4fa214a..4d942ebc71b 100644
--- a/board/pcs440ep/config.mk
+++ b/board/pcs440ep/config.mk
@@ -25,6 +25,9 @@
# PCS440EP board
#
+# Check the U-Boot Image with a SHA1 checksum
+ALL += $(obj)u-boot.sha1
+
#TEXT_BASE = 0x00001000
ifeq ($(ramsym),1)
diff --git a/board/pcs440ep/flash.c b/board/pcs440ep/flash.c
index ece54781b9d..70014407c6e 100644
--- a/board/pcs440ep/flash.c
+++ b/board/pcs440ep/flash.c
@@ -83,6 +83,7 @@ void flash_print_info(flash_info_t *info)
case FLASH_MAN_FUJ: printf ("FUJITSU "); break;
case FLASH_MAN_SST: printf ("SST "); break;
case FLASH_MAN_EXCEL: printf ("Excel Semiconductor "); break;
+ case FLASH_MAN_MX: printf ("MXIC "); break;
default: printf ("Unknown Vendor "); break;
}
@@ -195,6 +196,9 @@ static ulong flash_get_size(vu_long *addr, flash_info_t *info)
case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT:
info->flash_id = FLASH_MAN_EXCEL;
break;
+ case (CFG_FLASH_WORD_SIZE)MX_MANUFACT:
+ info->flash_id = FLASH_MAN_MX;
+ break;
default:
info->flash_id = FLASH_UNKNOWN;
info->sector_count = 0;
diff --git a/board/pcs440ep/init.S b/board/pcs440ep/init.S
index 0eee4d8099e..36a40c97a3d 100644
--- a/board/pcs440ep/init.S
+++ b/board/pcs440ep/init.S
@@ -87,27 +87,32 @@
.globl tlbtab
tlbtab:
- tlbtab_start
+ tlbtab_start
- /*
- * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
- * speed up boot process. It is patched after relocation to enable SA_I
- */
- tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
+ /*
+ * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
+ * speed up boot process. It is patched after relocation to enable SA_I
+ */
+ tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
- /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
- tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+ /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
+ tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
- tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
- tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
+ /*
+ * TLB entries for SDRAM are not needed on this platform.
+ * They are dynamically generated in the SPD DDR detection
+ * routine.
+ */
- /* PCI */
- tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
- tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
- /* USB 2.0 Device */
- tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
+ /* PCI */
+ tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
+ tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
- tlbtab_end
+ /* USB 2.0 Device */
+ tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
+
+ tlbtab_end
diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c
index b73ab2adecc..ada6b82c927 100644
--- a/board/pcs440ep/pcs440ep.c
+++ b/board/pcs440ep/pcs440ep.c
@@ -23,20 +23,112 @@
#include <common.h>
#include <ppc4xx.h>
+#include <malloc.h>
+#include <command.h>
+#include <crc.h>
#include <asm/processor.h>
#include <spd_sdram.h>
+#include <status_led.h>
+#include <sha1.h>
DECLARE_GLOBAL_DATA_PTR;
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
-static void set_leds(int val)
+unsigned char sha1_checksum[SHA1_SUM_LEN];
+
+/* swap 4 Bits (Bit0 = Bit3, Bit1 = Bit2, Bit2 = Bit1 and Bit3 = Bit0) */
+unsigned char swapbits[16] = {0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe,
+ 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf};
+
+static void set_leds (int val)
+{
+ out32(GPIO0_OR, (in32 (GPIO0_OR) & ~0x78000000) | (val << 27));
+}
+
+#define GET_LEDS ((in32 (GPIO0_OR) & 0x78000000) >> 27)
+
+void __led_init (led_id_t mask, int state)
+{
+ int val = GET_LEDS;
+
+ if (state == STATUS_LED_ON)
+ val |= mask;
+ else
+ val &= ~mask;
+ set_leds (val);
+}
+
+void __led_set (led_id_t mask, int state)
+{
+ int val = GET_LEDS;
+
+ if (state == STATUS_LED_ON)
+ val |= mask;
+ else if (state == STATUS_LED_OFF)
+ val &= ~mask;
+ set_leds (val);
+}
+
+void __led_toggle (led_id_t mask)
{
- unsigned char led[16] = {0x0, 0x8, 0x4, 0xc, 0x2, 0xa, 0x6, 0xe,
- 0x1, 0x9, 0x5, 0xd, 0x3, 0xb, 0x7, 0xf};
- out32(GPIO0_OR, (in32(GPIO0_OR) & ~0x78000000) | (led[val] << 27));
+ int val = GET_LEDS;
+
+ val ^= mask;
+ set_leds (val);
}
+static void status_led_blink (void)
+{
+ int i;
+ int val = GET_LEDS;
+
+ /* set all LED which are on, to state BLINKING */
+ for (i = 0; i < 4; i++) {
+ if (val & 0x08) status_led_set (i, STATUS_LED_BLINKING);
+ val = val << 1;
+ }
+}
+
+#if defined(CONFIG_SHOW_BOOT_PROGRESS)
+void show_boot_progress (int val)
+{
+ /* find all valid Codes for val in README */
+ if (val == -30) return;
+ if (val < 0) {
+ /* smthing goes wrong */
+ status_led_blink ();
+ return;
+ }
+ switch (val) {
+ case 1:
+ /* validating Image */
+ status_led_set (0, STATUS_LED_OFF);
+ status_led_set (1, STATUS_LED_ON);
+ status_led_set (2, STATUS_LED_ON);
+ break;
+ case 15:
+ /* booting */
+ status_led_set (0, STATUS_LED_ON);
+ status_led_set (1, STATUS_LED_ON);
+ status_led_set (2, STATUS_LED_ON);
+ break;
+ case 64:
+ /* starting Ethernet configuration */
+ status_led_set (0, STATUS_LED_OFF);
+ status_led_set (1, STATUS_LED_OFF);
+ status_led_set (2, STATUS_LED_ON);
+ break;
+ case 80:
+ /* loading Image */
+ status_led_set (0, STATUS_LED_ON);
+ status_led_set (1, STATUS_LED_OFF);
+ status_led_set (2, STATUS_LED_ON);
+ break;
+ }
+}
+#endif
+
int board_early_init_f(void)
{
register uint reg;
@@ -85,6 +177,251 @@ int board_early_init_f(void)
return 0;
}
+#define EEPROM_LEN 256
+void load_sernum_ethaddr (void)
+{
+ int ret;
+ char buf[EEPROM_LEN];
+ char mac[32];
+ char *use_eeprom;
+ u16 checksumcrc16 = 0;
+
+ /* read the MACs from EEprom */
+ status_led_set (0, STATUS_LED_ON);
+ status_led_set (1, STATUS_LED_ON);
+ ret = eeprom_read (CFG_I2C_EEPROM_ADDR, 0, (uchar *)buf, EEPROM_LEN);
+ if (ret == 0) {
+ checksumcrc16 = cyg_crc16 ((uchar *)buf, EEPROM_LEN - 2);
+ /* check, if the EEprom is programmed:
+ * - The Prefix(Byte 0,1,2) is equal to "ATR"
+ * - The checksum, stored in the last 2 Bytes, is correct
+ */
+ if ((strncmp (buf,"ATR",3) != 0) ||
+ ((checksumcrc16 >> 8) != buf[EEPROM_LEN - 2]) ||
+ ((checksumcrc16 & 0xff) != buf[EEPROM_LEN - 1])) {
+ /* EEprom is not programmed */
+ printf("%s: EEPROM Checksum not OK\n", __FUNCTION__);
+ } else {
+ /* get the MACs */
+ sprintf (mac, "%02x:%02x:%02x:%02x:%02x:%02x",
+ buf[3],
+ buf[4],
+ buf[5],
+ buf[6],
+ buf[7],
+ buf[8]);
+ setenv ("ethaddr", (char *) mac);
+ sprintf (mac, "%02x:%02x:%02x:%02x:%02x:%02x",
+ buf[9],
+ buf[10],
+ buf[11],
+ buf[12],
+ buf[13],
+ buf[14]);
+ setenv ("eth1addr", (char *) mac);
+ return;
+ }
+ }
+
+ /* some error reading the EEprom */
+ if ((use_eeprom = getenv ("use_eeprom_ethaddr")) == NULL) {
+ /* dont use bootcmd */
+ setenv("bootdelay", "-1");
+ return;
+ }
+ /* == default ? use standard */
+ if (strncmp (use_eeprom, "default", 7) == 0) {
+ return;
+ }
+ /* Env doesnt exist -> hang */
+ status_led_blink ();
+ hang ();
+ return;
+}
+
+#ifdef CONFIG_PREBOOT
+
+static uchar kbd_magic_prefix[] = "key_magic";
+static uchar kbd_command_prefix[] = "key_cmd";
+
+struct kbd_data_t {
+ char s1;
+ char s2;
+};
+
+struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
+{
+ char *val;
+ unsigned long tmp;
+
+ /* use the DIPs for some bootoptions */
+ val = getenv (ENV_NAME_DIP);
+ tmp = simple_strtoul (val, NULL, 16);
+
+ kbd_data->s2 = (tmp & 0x0f);
+ kbd_data->s1 = (tmp & 0xf0) >> 4;
+ return kbd_data;
+}
+
+static int compare_magic (const struct kbd_data_t *kbd_data, char *str)
+{
+ char s1 = str[0];
+
+ if (s1 >= '0' && s1 <= '9')
+ s1 -= '0';
+ else if (s1 >= 'a' && s1 <= 'f')
+ s1 = s1 - 'a' + 10;
+ else if (s1 >= 'A' && s1 <= 'F')
+ s1 = s1 - 'A' + 10;
+ else
+ return -1;
+
+ if (s1 != kbd_data->s1) return -1;
+
+ s1 = str[1];
+ if (s1 >= '0' && s1 <= '9')
+ s1 -= '0';
+ else if (s1 >= 'a' && s1 <= 'f')
+ s1 = s1 - 'a' + 10;
+ else if (s1 >= 'A' && s1 <= 'F')
+ s1 = s1 - 'A' + 10;
+ else
+ return -1;
+
+ if (s1 != kbd_data->s2) return -1;
+ return 0;
+}
+
+static char *key_match (const struct kbd_data_t *kbd_data)
+{
+ char magic[sizeof (kbd_magic_prefix) + 1];
+ char *suffix;
+ char *kbd_magic_keys;
+
+ /*
+ * The following string defines the characters that can be appended
+ * to "key_magic" to form the names of environment variables that
+ * hold "magic" key codes, i. e. such key codes that can cause
+ * pre-boot actions. If the string is empty (""), then only
+ * "key_magic" is checked (old behaviour); the string "125" causes
+ * checks for "key_magic1", "key_magic2" and "key_magic5", etc.
+ */
+ if ((kbd_magic_keys = getenv ("magic_keys")) == NULL)
+ kbd_magic_keys = "";
+
+ /* loop over all magic keys;
+ * use '\0' suffix in case of empty string
+ */
+ for (suffix = kbd_magic_keys; *suffix ||
+ suffix == kbd_magic_keys; ++suffix) {
+ sprintf (magic, "%s%c", kbd_magic_prefix, *suffix);
+ if (compare_magic (kbd_data, getenv (magic)) == 0) {
+ char cmd_name[sizeof (kbd_command_prefix) + 1];
+ char *cmd;
+
+ sprintf (cmd_name, "%s%c", kbd_command_prefix, *suffix);
+ cmd = getenv (cmd_name);
+
+ return (cmd);
+ }
+ }
+ return (NULL);
+}
+
+#endif /* CONFIG_PREBOOT */
+
+static int pcs440ep_readinputs (void)
+{
+ int i;
+ char value[20];
+
+ /* read the inputs and set the Envvars */
+ /* Revision Level Bit 26 - 29 */
+ i = ((in32 (GPIO0_IR) & 0x0000003c) >> 2);
+ i = swapbits[i];
+ sprintf (value, "%02x", i);
+ setenv (ENV_NAME_REVLEV, value);
+ /* Solder Switch Bit 30 - 33 */
+ i = (in32 (GPIO0_IR) & 0x00000003) << 2;
+ i += (in32 (GPIO1_IR) & 0xc0000000) >> 30;
+ i = swapbits[i];
+ sprintf (value, "%02x", i);
+ setenv (ENV_NAME_SOLDER, value);
+ /* DIP Switch Bit 49 - 56 */
+ i = ((in32 (GPIO1_IR) & 0x00007f80) >> 7);
+ i = (swapbits[i & 0x0f] << 4) + swapbits[(i & 0xf0) >> 4];
+ sprintf (value, "%02x", i);
+ setenv (ENV_NAME_DIP, value);
+ return 0;
+}
+
+
+#if defined(CONFIG_SHA1_CHECK_UB_IMG)
+/*************************************************************************
+ * calculate a SHA1 sum for the U-Boot image in Flash.
+ *
+ ************************************************************************/
+static int pcs440ep_sha1 (int docheck)
+{
+ unsigned char *data;
+ unsigned char *ptroff;
+ unsigned char output[20];
+ unsigned char org[20];
+ int i, len = CONFIG_SHA1_LEN;
+
+ memcpy ((char *)CFG_LOAD_ADDR, (char *)CONFIG_SHA1_START, len);
+ data = (unsigned char *)CFG_LOAD_ADDR;
+ ptroff = &data[len + SHA1_SUM_POS];
+
+ for (i = 0; i < SHA1_SUM_LEN; i++) {
+ org[i] = ptroff[i];
+ ptroff[i] = 0;
+ }
+
+ sha1_csum ((unsigned char *) data, len, (unsigned char *)output);
+
+ if (docheck == 2) {
+ for (i = 0; i < 20 ; i++) {
+ printf("%02X ", output[i]);
+ }
+ printf("\n");
+ }
+ if (docheck == 1) {
+ for (i = 0; i < 20 ; i++) {
+ if (org[i] != output[i]) return 1;
+ }
+ }
+ return 0;
+}
+
+/*************************************************************************
+ * do some checks after the SHA1 checksum from the U-Boot Image was
+ * calculated.
+ *
+ ************************************************************************/
+static void pcs440ep_checksha1 (void)
+{
+ int ret;
+ char *cs_test;
+
+ ret = pcs440ep_sha1 (1);
+ if (ret == 0) return;
+
+ if ((cs_test = getenv ("cs_test")) == NULL) {
+ /* Env doesnt exist -> hang */
+ status_led_blink ();
+ hang ();
+ }
+
+ if (strncmp (cs_test, "off", 3) == 0) {
+ printf ("SHA1 U-Boot sum NOT ok!\n");
+ setenv ("bootdelay", "-1");
+ }
+}
+#else
+static __inline__ void pcs440ep_checksha1 (void) { do {} while (0);}
+#endif
+
int misc_init_r (void)
{
uint pbcr;
@@ -139,6 +476,18 @@ int misc_init_r (void)
CFG_ENV_ADDR_REDUND + 2*CFG_ENV_SECT_SIZE - 1,
&flash_info[1]);
+ pcs440ep_readinputs ();
+ pcs440ep_checksha1 ();
+#ifdef CONFIG_PREBOOT
+ {
+ struct kbd_data_t kbd_data;
+ /* Decode keys */
+ char *str = strdup (key_match (get_keys (&kbd_data)));
+ /* Set or delete definition */
+ setenv ("preboot", str);
+ free (str);
+ }
+#endif /* CONFIG_PREBOOT */
return 0;
}
@@ -156,13 +505,31 @@ int checkboard(void)
return (0);
}
+void spd_ddr_init_hang (void)
+{
+ status_led_set (0, STATUS_LED_OFF);
+ status_led_set (1, STATUS_LED_ON);
+ /* we cannot use hang() because we are still running from
+ Flash, and so the status_led driver is not initialized */
+ puts ("### ERROR ### Please RESET the board ###\n");
+ for (;;) {
+ __led_toggle (4);
+ udelay (100000);
+ }
+}
+
long int initdram (int board_type)
{
long dram_size = 0;
- set_leds(1); /* display boot info counter */
+ status_led_set (0, STATUS_LED_ON);
+ status_led_set (1, STATUS_LED_OFF);
dram_size = spd_sdram();
- set_leds(2); /* display boot info counter */
+ status_led_set (0, STATUS_LED_OFF);
+ status_led_set (1, STATUS_LED_ON);
+ if (dram_size == 0) {
+ hang();
+ }
return dram_size;
}
@@ -377,3 +744,119 @@ void hw_watchdog_reset(void)
}
#endif
+
+/*************************************************************************
+ * "led" Commando for the U-Boot shell
+ *
+ ************************************************************************/
+int do_led (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int rcode = 0;
+ ulong pattern = 0;
+
+ pattern = simple_strtoul (argv[1], NULL, 10);
+ if (pattern > 200) {
+ status_led_blink ();
+ hang ();
+ return rcode;
+ }
+ if (pattern > 100) {
+ status_led_blink ();
+ return rcode;
+ }
+ pattern &= 0x0f;
+ set_leds (pattern);
+ return rcode;
+}
+
+U_BOOT_CMD(
+ led, 2, 1, do_led,
+ "led - set the led\n",
+ NULL
+);
+
+#if defined(CONFIG_SHA1_CHECK_UB_IMG)
+/*************************************************************************
+ * "sha1" Commando for the U-Boot shell
+ *
+ ************************************************************************/
+int do_sha1 (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+ int rcode = -1;
+
+ if (argc < 2) {
+ usage:
+ printf ("Usage:\n%s\n", cmdtp->usage);
+ return 1;
+ }
+
+ if (argc >= 3) {
+ unsigned char *data;
+ unsigned char output[20];
+ int len;
+ int i;
+
+ data = (unsigned char *)simple_strtoul (argv[1], NULL, 16);
+ len = simple_strtoul (argv[2], NULL, 16);
+ sha1_csum (data, len, (unsigned char *)output);
+ printf ("U-Boot sum:\n");
+ for (i = 0; i < 20 ; i++) {
+ printf ("%02X ", output[i]);
+ }
+ printf ("\n");
+ if (argc == 4) {
+ data = (unsigned char *)simple_strtoul (argv[3], NULL, 16);
+ memcpy (data, output, 20);
+ }
+ return 0;
+ }
+ if (argc == 2) {
+ char *ptr = argv[1];
+ if (*ptr != '-') goto usage;
+ ptr++;
+ if ((*ptr == 'c') || (*ptr == 'C')) {
+ rcode = pcs440ep_sha1 (1);
+ printf ("SHA1 U-Boot sum %sok!\n", (rcode != 0) ? "not " : "");
+ } else if ((*ptr == 'p') || (*ptr == 'P')) {
+ rcode = pcs440ep_sha1 (2);
+ } else {
+ rcode = pcs440ep_sha1 (0);
+ }
+ return rcode;
+ }
+ return rcode;
+}
+
+U_BOOT_CMD(
+ sha1, 4, 1, do_sha1,
+ "sha1 - calculate the SHA1 Sum\n",
+ "address len [addr] calculate the SHA1 sum [save at addr]\n"
+ " -p calculate the SHA1 sum from the U-Boot image in flash and print\n"
+ " -c check the U-Boot image in flash\n"
+);
+#endif
+
+#ifdef CONFIG_IDE_PREINIT
+int ide_preinit (void)
+{
+ /* Set True IDE Mode */
+ out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00100000));
+ out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00200000));
+ out32 (GPIO1_OR, (in32 (GPIO1_OR) & ~0x00008040));
+ udelay (100000);
+ return 0;
+}
+#endif
+
+#if defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET)
+void ide_set_reset (int idereset)
+{
+ debug ("ide_reset(%d)\n", idereset);
+ if (idereset == 0) {
+ out32 (GPIO0_OR, (in32 (GPIO0_OR) | 0x00200000));
+ } else {
+ out32 (GPIO0_OR, (in32 (GPIO0_OR) & ~0x00200000));
+ }
+ udelay (10000);
+}
+#endif /* defined (CFG_CMD_IDE) && defined (CONFIG_IDE_RESET) */
diff --git a/board/pcs440ep/u-boot.lds b/board/pcs440ep/u-boot.lds
index 6ab476ab143..6506ccdcf36 100644
--- a/board/pcs440ep/u-boot.lds
+++ b/board/pcs440ep/u-boot.lds
@@ -65,6 +65,7 @@ SECTIONS
{
cpu/ppc4xx/start.o (.text)
board/pcs440ep/init.o (.text)
+ lib_generic/sha1.o (.text)
*(.text)
*(.fixup)
diff --git a/board/sc520_cdp/sc520_cdp.c b/board/sc520_cdp/sc520_cdp.c
index b6add59bb48..f6f0e724437 100644
--- a/board/sc520_cdp/sc520_cdp.c
+++ b/board/sc520_cdp/sc520_cdp.c
@@ -507,6 +507,7 @@ int dram_init(void)
void show_boot_progress(int val)
{
+ if (val < -32) val = -1; /* let things compatible */
outb(val&0xff, 0x80);
outb((val&0xff00)>>8, 0x680);
}
diff --git a/board/sc520_spunk/sc520_spunk.c b/board/sc520_spunk/sc520_spunk.c
index ed226fd6423..d119a7d9977 100644
--- a/board/sc520_spunk/sc520_spunk.c
+++ b/board/sc520_spunk/sc520_spunk.c
@@ -507,6 +507,7 @@ void show_boot_progress(int val)
{
int version = read_mmcr_byte(SC520_SYSINFO);
+ if (val < -32) val = -1; /* let things compatible */
if (version == 0) {
/* PIO31-PIO16 Data */
write_mmcr_word(SC520_PIODATA31_16,
diff --git a/board/stxssa/stxssa.c b/board/stxssa/stxssa.c
index 0fb233d818a..5882124150e 100644
--- a/board/stxssa/stxssa.c
+++ b/board/stxssa/stxssa.c
@@ -52,147 +52,147 @@ long int fixed_sdram (void);
const iop_conf_t iop_conf_tab[4][32] = {
/* Port A configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
- /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
- /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
- /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
- /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
- /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
- /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
- /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
- /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
- /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
- /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
- /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
- /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
- /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
- /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
- /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
- /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
- /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
- /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
- /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
- /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
- /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
- /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
- /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
- /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
- /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
- /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
- /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
- /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
- /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
- /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
- /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
+ { /* conf ppar psor pdir podr pdat */
+ /* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
+ /* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
+ /* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
+ /* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
+ /* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
+ /* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
+ /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
+ /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
+ /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
+ /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
+ /* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
+ /* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
+ /* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
+ /* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
+ /* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
+ /* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
+ /* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
+ /* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
+ /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
+ /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
+ /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
+ /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
+ /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */
+ /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */
+ /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
+ /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */
+ /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
+ /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
+ /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
+ /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
+ /* PA1 */ { 1, 0, 0, 0, 0, 0 }, /* FREERUN */
+ /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
},
/* Port B configuration */
- { /* conf ppar psor pdir podr pdat */
- /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
- /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
- /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
- /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
- /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
- /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
- /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
- /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
- /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
- /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
- /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
- /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
- /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
- /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
- /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
- /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
- /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
- /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
- /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
- /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
- /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
- /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
- /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ { /* conf ppar psor pdir podr pdat */
+ /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
+ /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
+ /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
+ /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
+ /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
+ /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
+ /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
+ /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
+ /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
+ /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
+ /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
+ /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
+ /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
+ /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
+ /* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
+ /* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
+ /* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
+ /* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
+ /* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
+ /* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
+ /* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
+ /* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
+ /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
},
/* Port C */
- { /* conf ppar psor pdir podr pdat */
- /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
- /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
- /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
- /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
- /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
- /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
- /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
- /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
- /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
- /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
- /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
- /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
- /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
- /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
- /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
- /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
- /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
- /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
- /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
- /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
- /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
- /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */
- /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */
- /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
- /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
- /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
- /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
- /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
- /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
- /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
- /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
- /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
+ { /* conf ppar psor pdir podr pdat */
+ /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
+ /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
+ /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */
+ /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
+ /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */
+ /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
+ /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
+ /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
+ /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */
+ /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */
+ /* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
+ /* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
+ /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */
+ /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */
+ /* PC17 */ { 0, 0, 0, 1, 0, 0 }, /* PC17 */
+ /* PC16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */
+ /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */
+ /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */
+ /* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
+ /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */
+ /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */
+ /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */
+ /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */
+ /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
+ /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
+ /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
+ /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
+ /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
+ /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
+ /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */
+ /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */
+ /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */
},
/* Port D */
- { /* conf ppar psor pdir podr pdat */
- /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
- /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
- /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
- /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */
- /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TxD */
- /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
- /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
- /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
- /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
- /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
- /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
- /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
- /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
- /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
- /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
- /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
- /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
- /* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C CLK */
- /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
- /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
- /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
- /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
- /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
- /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
- /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
- /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
- /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
- /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
- /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
- /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
+ { /* conf ppar psor pdir podr pdat */
+ /* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
+ /* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
+ /* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
+ /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */
+ /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* SCC2 TxD */
+ /* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
+ /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
+ /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
+ /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
+ /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
+ /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
+ /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
+ /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
+ /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */
+ /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
+ /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
+ /* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
+ /* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C CLK */
+ /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
+ /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
+ /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
+ /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
+ /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
+ /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
+ /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
+ /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
+ /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
+ /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
+ /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
+ /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
}
};
@@ -227,12 +227,12 @@ reset_phy(void)
#if (CONFIG_ETHER_INDEX == 2)
bcsr->bcsr2 &= ~FETH2_RST;
udelay(2);
- bcsr->bcsr2 |= FETH2_RST;
+ bcsr->bcsr2 |= FETH2_RST;
udelay(1000);
#elif (CONFIG_ETHER_INDEX == 3)
bcsr->bcsr3 &= ~FETH3_RST;
udelay(2);
- bcsr->bcsr3 |= FETH3_RST;
+ bcsr->bcsr3 |= FETH3_RST;
udelay(1000);
#endif
#if defined(CONFIG_MII) && defined(CONFIG_ETHER_ON_FCC)
@@ -252,10 +252,10 @@ int
board_early_init_f(void)
{
#if defined(CONFIG_PCI)
- volatile immap_t *immr = (immap_t *)CFG_IMMR;
- volatile ccsr_pcix_t *pci = &immr->im_pcix;
+ volatile immap_t *immr = (immap_t *)CFG_IMMR;
+ volatile ccsr_pcix_t *pci = &immr->im_pcix;
- pci->peer &= 0xfffffffdf; /* disable master abort */
+ pci->peer &= 0xffffffdf; /* disable master abort */
#endif
/* Why is the phy reset done _after_ the ethernet
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-13 12:52:32 +0000