diff options
Diffstat (limited to 'board')
| -rw-r--r-- | board/alaska/Makefile | 45 | ||||
| -rw-r--r-- | board/alaska/alaska.c | 153 | ||||
| -rw-r--r-- | board/alaska/config.mk | 31 | ||||
| -rw-r--r-- | board/alaska/extserial.c | 110 | ||||
| -rw-r--r-- | board/alaska/flash.c | 807 | ||||
| -rw-r--r-- | board/alaska/serial.c | 131 | ||||
| -rw-r--r-- | board/alaska/u-boot.lds | 122 |
7 files changed, 1399 insertions, 0 deletions
diff --git a/board/alaska/Makefile b/board/alaska/Makefile new file mode 100644 index 00000000000..d2b5bb78a39 --- /dev/null +++ b/board/alaska/Makefile @@ -0,0 +1,45 @@ +# (C) Copyright 2003-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS := $(BOARD).o flash.o extserial.o serial.o + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff --git a/board/alaska/alaska.c b/board/alaska/alaska.c new file mode 100644 index 00000000000..93874b24f5f --- /dev/null +++ b/board/alaska/alaska.c @@ -0,0 +1,153 @@ +/* + * (C) Copyright 2004, Freescale Inc. + * TsiChung Liew, Tsi-Chung.Liew@freescale.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc8220.h> +#include <asm/processor.h> +#include <asm/mmu.h> + +void setupBat (ulong size) +{ + ulong batu, batl; + int blocksize = 0; + + /* Flash 0 */ +#if defined (CFG_AMD_BOOT) + batu = CFG_FLASH0_BASE | (BL_512K << 2) | BPP_RW | BPP_RX; +#else + batu = CFG_FLASH0_BASE | (BL_16M << 2) | BPP_RW | BPP_RX; +#endif + batl = CFG_FLASH0_BASE | 0x22; + write_bat (IBAT0, batu, batl); + write_bat (DBAT0, batu, batl); + + /* Flash 1 */ +#if defined (CFG_AMD_BOOT) + batu = CFG_FLASH1_BASE | (BL_16M << 2) | BPP_RW | BPP_RX; +#else + batu = CFG_FLASH1_BASE | (BL_512K << 2) | BPP_RW | BPP_RX; +#endif + batl = CFG_FLASH1_BASE | 0x22; + write_bat (IBAT1, batu, batl); + write_bat (DBAT1, batu, batl); + + /* CPLD */ + batu = CFG_CPLD_BASE | (BL_512K << 2) | BPP_RW | BPP_RX; + batl = CFG_CPLD_BASE | 0x22; + write_bat (IBAT2, 0, 0); + write_bat (DBAT2, batu, batl); + + /* FPGA */ + batu = CFG_FPGA_BASE | (BL_512K << 2) | BPP_RW | BPP_RX; + batl = CFG_FPGA_BASE | 0x22; + write_bat (IBAT3, 0, 0); + write_bat (DBAT3, batu, batl); + + /* MBAR - Data only */ + batu = CFG_MBAR | BPP_RW | BPP_RX; + batl = CFG_MBAR | 0x22; + mtspr (IBAT4L, 0); + mtspr (IBAT4U, 0); + mtspr (DBAT4L, batl); + mtspr (DBAT4U, batu); + + /* MBAR - SRAM */ + batu = CFG_SRAM_BASE | BPP_RW | BPP_RX; + batl = CFG_SRAM_BASE | 0x42; + mtspr (IBAT5L, batl); + mtspr (IBAT5U, batu); + mtspr (DBAT5L, batl); + mtspr (DBAT5U, batu); + + if (size <= 0x800000) /* 8MB */ + blocksize = BL_8M << 2; + else if (size <= 0x1000000) /* 16MB */ + blocksize = BL_16M << 2; + else if (size <= 0x2000000) /* 32MB */ + blocksize = BL_32M << 2; + else if (size <= 0x4000000) /* 64MB */ + blocksize = BL_64M << 2; + else if (size <= 0x8000000) /* 128MB */ + blocksize = BL_128M << 2; + else if (size <= 0x10000000) /* 256MB */ + blocksize = BL_256M << 2; + + /* Memory */ + batu = CFG_SDRAM_BASE | blocksize | BPP_RW | BPP_RX; + batl = CFG_SDRAM_BASE | 0x42; + mtspr (IBAT6L, batl); + mtspr (IBAT6U, batu); + mtspr (DBAT6L, batl); + mtspr (DBAT6U, batu); + + /* memory size is less than 256MB */ + if (size <= 0x10000000) { + /* Nothing */ + batu = 0; + batl = 0; + } else { + size -= 0x10000000; + if (size <= 0x800000) /* 8MB */ + blocksize = BL_8M << 2; + else if (size <= 0x1000000) /* 16MB */ + blocksize = BL_16M << 2; + else if (size <= 0x2000000) /* 32MB */ + blocksize = BL_32M << 2; + else if (size <= 0x4000000) /* 64MB */ + blocksize = BL_64M << 2; + else if (size <= 0x8000000) /* 128MB */ + blocksize = BL_128M << 2; + else if (size <= 0x10000000) /* 256MB */ + blocksize = BL_256M << 2; + + batu = (CFG_SDRAM_BASE + + 0x10000000) | blocksize | BPP_RW | BPP_RX; + batl = (CFG_SDRAM_BASE + 0x10000000) | 0x42; + } + + mtspr (IBAT7L, batl); + mtspr (IBAT7U, batu); + mtspr (DBAT7L, batl); + mtspr (DBAT7U, batu); +} + +long int initdram (int board_type) +{ + ulong size; + + size = dramSetup (); + +/* if iCache ad dCache is defined */ +#if (CONFIG_COMMANDS & CFG_CMD_CACHE) +/* setupBat(size);*/ +#endif + + return size; +} + +int checkboard (void) +{ + puts ("Board: Alaska MPC8220 Evaluation Board\n"); + + return 0; +} diff --git a/board/alaska/config.mk b/board/alaska/config.mk new file mode 100644 index 00000000000..99d28a54fc5 --- /dev/null +++ b/board/alaska/config.mk @@ -0,0 +1,31 @@ +# +# (C) Copyright 2003-2004 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +# +# alaska board +# + +TEXT_BASE = 0xfff00000 +# TEXT_BASE = 0x00100000 + +PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board diff --git a/board/alaska/extserial.c b/board/alaska/extserial.c new file mode 100644 index 00000000000..f17e06e4ea3 --- /dev/null +++ b/board/alaska/extserial.c @@ -0,0 +1,110 @@ +/* + * (C) Copyright 2004, Freescale, Inc + * TsiChung Liew, Tsi-Chung.Liew@freescale.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * Minimal serial functions needed to use one of the PSC ports + * as serial console interface. + */ + +#include <common.h> +#include <mpc8220.h> + +#if defined (CONFIG_EXTUART_CONSOLE) +# include <ns16550.h> + +# define PADSERIAL_BAUD_115200 0x40 +# define PADSERIAL_BAUD_57600 0x20 +# define PADSERIAL_BAUD_9600 0 +# define PADCARD_FREQ 18432000 + +const NS16550_t com_port = (NS16550_t) CFG_NS16550_COM1; + +int ext_serial_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + volatile u8 *dipswitch = (volatile u8 *) (CFG_CPLD_BASE + 0x1002); + int baud_divisor; + + /* Find out the baud rate speed on debug card dip switches */ + if (*dipswitch & PADSERIAL_BAUD_115200) + gd->baudrate = 115200; + else if (*dipswitch & PADSERIAL_BAUD_57600) + gd->baudrate = 57600; + else + gd->baudrate = 9600; + + /* Debug card frequency */ + baud_divisor = PADCARD_FREQ / (16 * gd->baudrate); + + NS16550_init (com_port, baud_divisor); + + return (0); +} + +void ext_serial_putc (const char c) +{ + if (c == '\n') + NS16550_putc (com_port, '\r'); + + NS16550_putc (com_port, c); +} + +void ext_serial_puts (const char *s) +{ + while (*s) { + serial_putc (*s++); + } +} + +int ext_serial_getc (void) +{ + return NS16550_getc (com_port); +} + +int ext_serial_tstc (void) +{ + return NS16550_tstc (com_port); +} + +void ext_serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + volatile u8 *dipswitch = (volatile u8 *) (CFG_CPLD_BASE + 0x1002); + int baud_divisor; + + /* Find out the baud rate speed on debug card dip switches */ + if (*dipswitch & PADSERIAL_BAUD_115200) + gd->baudrate = 115200; + else if (*dipswitch & PADSERIAL_BAUD_57600) + gd->baudrate = 57600; + else + gd->baudrate = 9600; + + /* Debug card frequency */ + baud_divisor = PADCARD_FREQ / (16 * gd->baudrate); + + NS16550_reinit (com_port, baud_divisor); +} +#endif /* CONFIG_EXTUART_CONSOLE */ diff --git a/board/alaska/flash.c b/board/alaska/flash.c new file mode 100644 index 00000000000..48c94727e07 --- /dev/null +++ b/board/alaska/flash.c @@ -0,0 +1,807 @@ +/* + * (C) Copyright 2001 + * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net + * + * (C) Copyright 2001-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <linux/byteorder/swab.h> + + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* Board support for 1 or 2 flash devices */ +#define FLASH_PORT_WIDTH8 + +typedef unsigned char FLASH_PORT_WIDTH; +typedef volatile unsigned char FLASH_PORT_WIDTHV; + +#define SWAP(x) (x) + +/* Intel-compatible flash ID */ +#define INTEL_COMPAT 0x89 +#define INTEL_ALT 0xB0 + +/* Intel-compatible flash commands */ +#define INTEL_PROGRAM 0x10 +#define INTEL_ERASE 0x20 +#define INTEL_CLEAR 0x50 +#define INTEL_LOCKBIT 0x60 +#define INTEL_PROTECT 0x01 +#define INTEL_STATUS 0x70 +#define INTEL_READID 0x90 +#define INTEL_CONFIRM 0xD0 +#define INTEL_RESET 0xFF + +/* Intel-compatible flash status bits */ +#define INTEL_FINISHED 0x80 +#define INTEL_OK 0x80 + +#define FPW FLASH_PORT_WIDTH +#define FPWV FLASH_PORT_WIDTHV + +#define FLASH_CYCLE1 0x0555 +#define FLASH_CYCLE2 0x02aa + +#define WR_BLOCK 0x20 + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size (FPW * addr, flash_info_t * info); +static int write_data (flash_info_t * info, ulong dest, FPW data); +static int write_data_block (flash_info_t * info, ulong src, ulong dest); +static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data); +static void flash_get_offsets (ulong base, flash_info_t * info); +void inline spin_wheel (void); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init (void) +{ + int i; + ulong size = 0; + ulong fsize = 0; + + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) { + memset (&flash_info[i], 0, sizeof (flash_info_t)); + + switch (i) { + case 0: + flash_get_size ((FPW *) CFG_FLASH1_BASE, + &flash_info[i]); + flash_get_offsets (CFG_FLASH1_BASE, &flash_info[i]); + break; + case 1: + flash_get_size ((FPW *) CFG_FLASH1_BASE, + &flash_info[i]); + fsize = CFG_FLASH1_BASE + flash_info[i - 1].size; + flash_get_offsets (fsize, &flash_info[i]); + break; + case 2: + flash_get_size ((FPW *) CFG_FLASH0_BASE, + &flash_info[i]); + flash_get_offsets (CFG_FLASH0_BASE, &flash_info[i]); + break; + case 3: + flash_get_size ((FPW *) CFG_FLASH0_BASE, + &flash_info[i]); + fsize = CFG_FLASH0_BASE + flash_info[i - 1].size; + flash_get_offsets (fsize, &flash_info[i]); + break; + default: + panic ("configured to many flash banks!\n"); + break; + } + size += flash_info[i].size; + } + + /* Protect monitor and environment sectors + */ +#if defined (CFG_AMD_BOOT) + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[2]); + flash_protect (FLAG_PROTECT_SET, + CFG_INTEL_BASE, + CFG_INTEL_BASE + monitor_flash_len - 1, + &flash_info[1]); +#else + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[3]); + flash_protect (FLAG_PROTECT_SET, + CFG_AMD_BASE, + CFG_AMD_BASE + monitor_flash_len - 1, &flash_info[0]); +#endif + + flash_protect (FLAG_PROTECT_SET, + CFG_ENV1_ADDR, + CFG_ENV1_ADDR + CFG_ENV1_SIZE - 1, &flash_info[1]); + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SIZE - 1, &flash_info[3]); + + return size; +} + +/*----------------------------------------------------------------------- + */ +static void flash_get_offsets (ulong base, flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) + return; + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * PHYS_AMD_SECT_SIZE); + info->protect[i] = 0; + } + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) { + for (i = 0; i < info->sector_count; i++) { + info->start[i] = base + (i * PHYS_INTEL_SECT_SIZE); + info->protect[i] = 0; + } + } +} + +/*----------------------------------------------------------------------- + */ +void flash_print_info (flash_info_t * info) +{ + int i; + + if (info->flash_id == FLASH_UNKNOWN) { + printf ("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_INTEL: + printf ("INTEL "); + break; + case FLASH_MAN_AMD: + printf ("AMD "); + break; + default: + printf ("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_28F128J3A: + printf ("28F128J3A\n"); + break; + + case FLASH_AM040: + printf ("AMD29F040B\n"); + break; + + default: + printf ("Unknown Chip Type\n"); + break; + } + + printf (" Size: %ld MB in %d Sectors\n", + info->size >> 20, info->sector_count); + + printf (" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + if ((i % 5) == 0) + printf ("\n "); + printf (" %08lX%s", + info->start[i], info->protect[i] ? " (RO)" : " "); + } + printf ("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size (FPW * addr, flash_info_t * info) +{ + FPWV value; + static int amd = 0; + + /* Write auto select command: read Manufacturer ID */ + /* Write auto select command sequence and test FLASH answer */ + addr[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* for AMD, Intel ignores this */ + __asm__ ("sync"); + addr[FLASH_CYCLE2] = (FPW) 0x00550055; /* for AMD, Intel ignores this */ + __asm__ ("sync"); + addr[FLASH_CYCLE1] = (FPW) 0x00900090; /* selects Intel or AMD */ + __asm__ ("sync"); + + udelay (100); + + switch (addr[0] & 0xff) { + + case (uchar) AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + value = addr[1]; + break; + + case (uchar) INTEL_MANUFACT: + info->flash_id = FLASH_MAN_INTEL; + value = addr[2]; + break; + + default: + printf ("unknown\n"); + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + return (0); /* no or unknown flash */ + } + + switch (value) { + + case (FPW) INTEL_ID_28F128J3A: + info->flash_id += FLASH_28F128J3A; + info->sector_count = 64; + info->size = 0x00800000; /* => 16 MB */ + break; + + case (FPW) AMD_ID_LV040B: + info->flash_id += FLASH_AM040; + if (amd == 0) { + info->sector_count = 7; + info->size = 0x00070000; /* => 448 KB */ + amd = 1; + } else { + /* for Environment settings */ + info->sector_count = 1; + info->size = PHYS_AMD_SECT_SIZE; /* => 64 KB */ + amd = 0; + } + break; + + default: + info->flash_id = FLASH_UNKNOWN; + break; + } + + if (info->sector_count > CFG_MAX_FLASH_SECT) { + printf ("** ERROR: sector count %d > max (%d) **\n", + info->sector_count, CFG_MAX_FLASH_SECT); + info->sector_count = CFG_MAX_FLASH_SECT; + } + + if (value == (FPW) INTEL_ID_28F128J3A) + addr[0] = (FPW) 0x00FF00FF; /* restore read mode */ + else + addr[0] = (FPW) 0x00F000F0; /* restore read mode */ + + return (info->size); +} + + +/*----------------------------------------------------------------------- + */ +int flash_erase (flash_info_t * info, int s_first, int s_last) +{ + int flag, prot, sect; + ulong type, start, last; + int rcode = 0, intel = 0; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) + printf ("- missing\n"); + else + printf ("- no sectors to erase\n"); + return 1; + } + + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_INTEL)) { + type = (info->flash_id & FLASH_VENDMASK); + if ((type != FLASH_MAN_AMD)) { + printf ("Can't erase unknown flash type %08lx - aborted\n", + info->flash_id); + return 1; + } + } + + if (type == FLASH_MAN_INTEL) + intel = 1; + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf ("- Warning: %d protected sectors will not be erased!\n", prot); + } else { + printf ("\n"); + } + + start = get_timer (0); + last = start; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + FPWV *addr = (FPWV *) (info->start[sect]); + FPW status; + + printf ("Erasing sector %2d ... ", sect); + + /* arm simple, non interrupt dependent timer */ + start = get_timer (0); + + if (intel) { + *addr = (FPW) 0x00500050; /* clear status register */ + *addr = (FPW) 0x00200020; /* erase setup */ + *addr = (FPW) 0x00D000D0; /* erase confirm */ + } else { + FPWV *base; /* first address in bank */ + + base = (FPWV *) (CFG_AMD_BASE); + base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (FPW) 0x00800080; /* erase mode */ + base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */ + *addr = (FPW) 0x00300030; /* erase sector */ + } + + while (((status = + *addr) & (FPW) 0x00800080) != + (FPW) 0x00800080) { + if (get_timer (start) > CFG_FLASH_ERASE_TOUT) { + printf ("Timeout\n"); + if (intel) { + *addr = (FPW) 0x00B000B0; /* suspend erase */ + *addr = (FPW) 0x00FF00FF; /* reset to read mode */ + } else + *addr = (FPW) 0x00F000F0; /* reset to read mode */ + + rcode = 1; + break; + } + } + + if (intel) { + *addr = (FPW) 0x00500050; /* clear status register cmd. */ + *addr = (FPW) 0x00FF00FF; /* resest to read mode */ + } else + *addr = (FPW) 0x00F000F0; /* reset to read mode */ + + printf (" done\n"); + } + } + return rcode; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + * 4 - Flash not identified + */ + +int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + if (info->flash_id == FLASH_UNKNOWN) { + return 4; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + { + FPW data = 0; /* 16 or 32 bit word, matches flash bus width */ + int bytes; /* number of bytes to program in current word */ + int left; /* number of bytes left to program */ + int i, res; + + for (left = cnt, res = 0; + left > 0 && res == 0; + addr += sizeof (data), left -= + sizeof (data) - bytes) { + + bytes = addr & (sizeof (data) - 1); + addr &= ~(sizeof (data) - 1); + + /* combine source and destination data so can program + * an entire word of 16 or 32 bits + */ + for (i = 0; i < sizeof (data); i++) { + data <<= 8; + if (i < bytes || i - bytes >= left) + data += *((uchar *) addr + i); + else + data += *src++; + } + + res = write_word_amd (info, (FPWV *) addr, + data); + } + return res; + } /* case FLASH_MAN_AMD */ + + case FLASH_MAN_INTEL: + { + ulong cp, wp; + FPW data; + int count, i, l, rc, port_width; + + /* get lower word aligned address */ + wp = addr; + port_width = 1; + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + for (; i < port_width && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + + for (; cnt == 0 && i < port_width; ++i, ++cp) + data = (data << 8) | (*(uchar *) cp); + + if ((rc = + write_data (info, wp, SWAP (data))) != 0) + return (rc); + wp += port_width; + } + + if (cnt > WR_BLOCK) { + /* + * handle word aligned part + */ + count = 0; + while (cnt >= WR_BLOCK) { + + if ((rc = + write_data_block (info, + (ulong) src, + wp)) != 0) + return (rc); + + wp += WR_BLOCK; + src += WR_BLOCK; + cnt -= WR_BLOCK; + + if (count++ > 0x800) { + spin_wheel (); + count = 0; + } + } + } + + if (cnt < WR_BLOCK) { + /* + * handle word aligned part + */ + count = 0; + while (cnt >= port_width) { + data = 0; + for (i = 0; i < port_width; ++i) + data = (data << 8) | *src++; + + if ((rc = + write_data (info, wp, + SWAP (data))) != 0) + return (rc); + + wp += port_width; + cnt -= port_width; + if (count++ > 0x800) { + spin_wheel (); + count = 0; + } + } + } + + if (cnt == 0) + return (0); + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < port_width && cnt > 0; + ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + + for (; i < port_width; ++i, ++cp) + data = (data << 8) | (*(uchar *) cp); + + return (write_data (info, wp, SWAP (data))); + } /* case FLASH_MAN_INTEL */ + + } /* switch */ + return (0); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data (flash_info_t * info, ulong dest, FPW data) +{ + FPWV *addr = (FPWV *) dest; + ulong start; + int flag; + + /* Check if Flash is (sufficiently) erased */ + if ((*addr & data) != data) { + printf ("not erased at %08lx (%lx)\n", (ulong) addr, *addr); + return (2); + } + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + *addr = (FPW) 0x00400040; /* write setup */ + *addr = data; + + /* arm simple, non interrupt dependent timer */ + start = get_timer (0); + + /* wait while polling the status register */ + while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + return (1); + } + } + + *addr = (FPW) 0x00FF00FF; /* restore read mode */ + + return (0); +} + +/*----------------------------------------------------------------------- + * Write a word or halfword to Flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_data_block (flash_info_t * info, ulong src, ulong dest) +{ + FPWV *srcaddr = (FPWV *) src; + FPWV *dstaddr = (FPWV *) dest; + ulong start; + int flag, i; + + /* Check if Flash is (sufficiently) erased */ + for (i = 0; i < WR_BLOCK; i++) + if ((*dstaddr++ & 0xff) != 0xff) { + printf ("not erased at %08lx (%lx)\n", + (ulong) dstaddr, *dstaddr); + return (2); + } + + dstaddr = (FPWV *) dest; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + *dstaddr = (FPW) 0x00e800e8; /* write block setup */ + + /* arm simple, non interrupt dependent timer */ + start = get_timer (0); + + /* wait while polling the status register */ + while ((*dstaddr & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + *dstaddr = (FPW) 0x00FF00FF; /* restore read mode */ + return (1); + } + } + + *dstaddr = (FPW) 0x001f001f; /* write 32 to buffer */ + for (i = 0; i < WR_BLOCK; i++) + *dstaddr++ = *srcaddr++; + + dstaddr -= 1; + *dstaddr = (FPW) 0x00d000d0; /* write 32 to buffer */ + + /* arm simple, non interrupt dependent timer */ + start = get_timer (0); + + /* wait while polling the status register */ + while ((*dstaddr & (FPW) 0x00800080) != (FPW) 0x00800080) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + *dstaddr = (FPW) 0x00FF00FF; /* restore read mode */ + return (1); + } + } + + *dstaddr = (FPW) 0x00FF00FF; /* restore read mode */ + + return (0); +} + +/*----------------------------------------------------------------------- + * Write a word to Flash for AMD FLASH + * A word is 16 or 32 bits, whichever the bus width of the flash bank + * (not an individual chip) is. + * + * returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data) +{ + ulong start; + int flag; + int res = 0; /* result, assume success */ + FPWV *base; /* first address in flash bank */ + + /* Check if Flash is (sufficiently) erased */ + if ((*dest & data) != data) { + return (2); + } + + base = (FPWV *) (CFG_AMD_BASE); + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts (); + + base[FLASH_CYCLE1] = (FPW) 0x00AA00AA; /* unlock */ + base[FLASH_CYCLE2] = (FPW) 0x00550055; /* unlock */ + base[FLASH_CYCLE1] = (FPW) 0x00A000A0; /* selects program mode */ + + *dest = data; /* start programming the data */ + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts (); + + start = get_timer (0); + + /* data polling for D7 */ + while (res == 0 + && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) { + if (get_timer (start) > CFG_FLASH_WRITE_TOUT) { + *dest = (FPW) 0x00F000F0; /* reset bank */ + res = 1; + } + } + + return (res); +} + +void inline spin_wheel (void) +{ + static int p = 0; + static char w[] = "\\/-"; + + printf ("\010%c", w[p]); + (++p == 3) ? (p = 0) : 0; +} + +/*----------------------------------------------------------------------- + * Set/Clear sector's lock bit, returns: + * 0 - OK + * 1 - Error (timeout, voltage problems, etc.) + */ +int flash_real_protect (flash_info_t * info, long sector, int prot) +{ + ulong start; + int i; + int rc = 0; + FPWV *addr = (FPWV *) (info->start[sector]); + int flag = disable_interrupts (); + + /* + * 29F040B AMD flash does not support software protection/unprotection, + * the only way to protect the AMD flash is marked it as prot bit. + * This flash only support hardware protection, by supply or not supply + * 12vpp to the flash + */ + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_AMD) { + info->protect[sector] = prot; + + return 0; + } + + *addr = INTEL_CLEAR; /* Clear status register */ + if (prot) { /* Set sector lock bit */ + *addr = INTEL_LOCKBIT; /* Sector lock bit */ + *addr = INTEL_PROTECT; /* set */ + } else { /* Clear sector lock bit */ + *addr = INTEL_LOCKBIT; /* All sectors lock bits */ + *addr = INTEL_CONFIRM; /* clear */ + } + + start = get_timer (0); + + while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) { + if (get_timer (start) > CFG_FLASH_UNLOCK_TOUT) { + printf ("Flash lock bit operation timed out\n"); + rc = 1; + break; + } + } + + if (*addr != INTEL_OK) { + printf ("Flash lock bit operation failed at %08X, CSR=%08X\n", + (uint) addr, (uint) * addr); + rc = 1; + } + + if (!rc) + info->protect[sector] = prot; + + /* + * Clear lock bit command clears all sectors lock bits, so + * we have to restore lock bits of protected sectors. + */ + if (!prot) { + for (i = 0; i < info->sector_count; i++) { + if (info->protect[i]) { + start = get_timer (0); + addr = (FPWV *) (info->start[i]); + *addr = INTEL_LOCKBIT; /* Sector lock bit */ + *addr = INTEL_PROTECT; /* set */ + while ((*addr & INTEL_FINISHED) != + INTEL_FINISHED) { + if (get_timer (start) > + CFG_FLASH_UNLOCK_TOUT) { + printf ("Flash lock bit operation timed out\n"); + rc = 1; + break; + } + } + } + } + } + + if (flag) + enable_interrupts (); + + *addr = INTEL_RESET; /* Reset to read array mode */ + + return rc; +} diff --git a/board/alaska/serial.c b/board/alaska/serial.c new file mode 100644 index 00000000000..08285b87b9b --- /dev/null +++ b/board/alaska/serial.c @@ -0,0 +1,131 @@ +/* + * (C) Copyright 2004, Freescale, Inc + * TsiChung Liew, Tsi-Chung.Liew@freescale.com. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +/* + * Minimal serial functions needed to use one of the PSC ports + * as serial console interface. + */ + +#include <common.h> +#include <mpc8220.h> + +int serial_init (void) +{ + DECLARE_GLOBAL_DATA_PTR; + +#if defined (CONFIG_EXTUART_CONSOLE) + volatile uchar *cpld = (volatile uchar *) CFG_CPLD_BASE; +#endif + + /* Check CPLD Switch 2 whether is external or internal */ +#if defined (CONFIG_EXTUART_CONSOLE) + if ((*cpld & 0x02) == 0x02) { + gd->bExtUart = 1; + return ext_serial_init (); + } else +#endif + { +#if defined(CONFIG_PSC_CONSOLE) + gd->bExtUart = 0; + return psc_serial_init (); +#endif + } + + return (0); +} + +void serial_putc (const char c) +{ + DECLARE_GLOBAL_DATA_PTR; + + if (gd->bExtUart) { +#if defined (CONFIG_EXTUART_CONSOLE) + ext_serial_putc (c); +#endif + } else { +#if defined(CONFIG_PSC_CONSOLE) + psc_serial_putc (c); +#endif + } +} + +void serial_puts (const char *s) +{ + DECLARE_GLOBAL_DATA_PTR; + + if (gd->bExtUart) { +#if defined (CONFIG_EXTUART_CONSOLE) + ext_serial_puts (s); +#endif + } else { +#if defined(CONFIG_PSC_CONSOLE) + psc_serial_puts (s); +#endif + } +} + +int serial_getc (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + if (gd->bExtUart) { +#if defined (CONFIG_EXTUART_CONSOLE) + return ext_serial_getc (); +#endif + } else { +#if defined(CONFIG_PSC_CONSOLE) + return psc_serial_getc (); +#endif + } +} + +int serial_tstc (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + if (gd->bExtUart) { +#if defined (CONFIG_EXTUART_CONSOLE) + return ext_serial_tstc (); +#endif + } else { +#if defined(CONFIG_PSC_CONSOLE) + return psc_serial_tstc (); +#endif + } +} + +void serial_setbrg (void) +{ + DECLARE_GLOBAL_DATA_PTR; + + if (gd->bExtUart) { +#if defined (CONFIG_EXTUART_CONSOLE) + ext_serial_setbrg (); +#endif + } else { +#if defined(CONFIG_PSC_CONSOLE) + psc_serial_setbrg (); +#endif + } +} diff --git a/board/alaska/u-boot.lds b/board/alaska/u-boot.lds new file mode 100644 index 00000000000..6e4a060bb6a --- /dev/null +++ b/board/alaska/u-boot.lds @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + cpu/mpc8220/start.o (.text) + *(.text) + *(.fixup) + *(.got1) + . = ALIGN(16); + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x0FFF) & 0xFFFFF000; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >> 2; + __fixup_entries = (. - _FIXUP_TABLE_) >> 2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(4096); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(4096); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} |