diff options
Diffstat (limited to 'board')
42 files changed, 1997 insertions, 1997 deletions
diff --git a/board/altera/arria5-socdk/qts/iocsr_config.h b/board/altera/arria5-socdk/qts/iocsr_config.h index 69a92de6361..f201ad34587 100644 --- a/board/altera/arria5-socdk/qts/iocsr_config.h +++ b/board/altera/arria5-socdk/qts/iocsr_config.h @@ -6,10 +6,10 @@ #ifndef __SOCFPGA_IOCSR_CONFIG_H__ #define __SOCFPGA_IOCSR_CONFIG_H__ -#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 1337 -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 1528 -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 1337 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 1528 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 const unsigned long iocsr_scan_chain0_table[] = { 0x00000000, diff --git a/board/altera/arria5-socdk/qts/pll_config.h b/board/altera/arria5-socdk/qts/pll_config.h index 6c832543444..7fe290b28d9 100644 --- a/board/altera/arria5-socdk/qts/pll_config.h +++ b/board/altera/arria5-socdk/qts/pll_config.h @@ -6,79 +6,79 @@ #ifndef __SOCFPGA_PLL_CONFIG_H__ #define __SOCFPGA_PLL_CONFIG_H__ -#define CONFIG_HPS_DBCTRL_STAYOSC1 1 +#define CFG_HPS_DBCTRL_STAYOSC1 1 -#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 41 -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 2 -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 8 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 41 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 2 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 8 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1 -#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 1 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79 -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 1 -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 9 -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1 -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 -#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 +#define CFG_HPS_PERPLLGRP_VCO_DENOM 1 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 79 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 1 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 9 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 1 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 1 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1 -#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 127 -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 2 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 127 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 -#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1050000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 1066000000 -#define CONFIG_HPS_CLK_EMAC0_HZ 250000000 -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 -#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 -#define CONFIG_HPS_CLK_NAND_HZ 50000000 -#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 -#define CONFIG_HPS_CLK_QSPI_HZ 350000000 -#define CONFIG_HPS_CLK_SPIM_HZ 200000000 -#define CONFIG_HPS_CLK_CAN0_HZ 100000000 -#define CONFIG_HPS_CLK_CAN1_HZ 100000000 -#define CONFIG_HPS_CLK_GPIODB_HZ 32000 -#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 -#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1050000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 1066000000 +#define CFG_HPS_CLK_EMAC0_HZ 250000000 +#define CFG_HPS_CLK_EMAC1_HZ 250000000 +#define CFG_HPS_CLK_USBCLK_HZ 200000000 +#define CFG_HPS_CLK_NAND_HZ 50000000 +#define CFG_HPS_CLK_SDMMC_HZ 200000000 +#define CFG_HPS_CLK_QSPI_HZ 350000000 +#define CFG_HPS_CLK_SPIM_HZ 200000000 +#define CFG_HPS_CLK_CAN0_HZ 100000000 +#define CFG_HPS_CLK_CAN1_HZ 100000000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000 -#define CONFIG_HPS_ALTERAGRP_MPUCLK 0 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 2 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 +#define CFG_HPS_ALTERAGRP_MPUCLK 0 +#define CFG_HPS_ALTERAGRP_MAINCLK 2 +#define CFG_HPS_ALTERAGRP_DBGATCLK 3 #endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/altera/arria5-socdk/qts/sdram_config.h b/board/altera/arria5-socdk/qts/sdram_config.h index 927a7a4f8e0..1d032e1af4b 100644 --- a/board/altera/arria5-socdk/qts/sdram_config.h +++ b/board/altera/arria5-socdk/qts/sdram_config.h @@ -7,76 +7,76 @@ #define __SOCFPGA_SDRAM_CONFIG_H__ /* SDRAM configuration */ -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 19 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 139 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 4160 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 19 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 26 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 19 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 139 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 4160 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 19 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 26 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 /* Sequencer auto configuration */ #define RW_MGR_ACTIVATE_0_AND_1 0x0D diff --git a/board/altera/cyclone5-socdk/qts/iocsr_config.h b/board/altera/cyclone5-socdk/qts/iocsr_config.h index 81c507b842b..a571fb3e509 100644 --- a/board/altera/cyclone5-socdk/qts/iocsr_config.h +++ b/board/altera/cyclone5-socdk/qts/iocsr_config.h @@ -6,10 +6,10 @@ #ifndef __SOCFPGA_IOCSR_CONFIG_H__ #define __SOCFPGA_IOCSR_CONFIG_H__ -#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 const unsigned long iocsr_scan_chain0_table[] = { 0x00000000, diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h index ae5cfab0cf7..a46d124e9e9 100644 --- a/board/altera/cyclone5-socdk/qts/pll_config.h +++ b/board/altera/cyclone5-socdk/qts/pll_config.h @@ -6,79 +6,79 @@ #ifndef __SOCFPGA_PLL_CONFIG_H__ #define __SOCFPGA_PLL_CONFIG_H__ -#define CONFIG_HPS_DBCTRL_STAYOSC1 1 +#define CFG_HPS_DBCTRL_STAYOSC1 1 -#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73 -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4 -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 73 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1 -#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 -#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 1 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1 -#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 -#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 -#define CONFIG_HPS_CLK_EMAC0_HZ 1953125 -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 -#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 -#define CONFIG_HPS_CLK_NAND_HZ 50000000 -#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 -#define CONFIG_HPS_CLK_QSPI_HZ 370000000 -#define CONFIG_HPS_CLK_SPIM_HZ 200000000 -#define CONFIG_HPS_CLK_CAN0_HZ 100000000 -#define CONFIG_HPS_CLK_CAN1_HZ 12500000 -#define CONFIG_HPS_CLK_GPIODB_HZ 32000 -#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 -#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1850000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 800000000 +#define CFG_HPS_CLK_EMAC0_HZ 1953125 +#define CFG_HPS_CLK_EMAC1_HZ 250000000 +#define CFG_HPS_CLK_USBCLK_HZ 200000000 +#define CFG_HPS_CLK_NAND_HZ 50000000 +#define CFG_HPS_CLK_SDMMC_HZ 200000000 +#define CFG_HPS_CLK_QSPI_HZ 370000000 +#define CFG_HPS_CLK_SPIM_HZ 200000000 +#define CFG_HPS_CLK_CAN0_HZ 100000000 +#define CFG_HPS_CLK_CAN1_HZ 12500000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000 -#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 4 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4 +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 4 +#define CFG_HPS_ALTERAGRP_DBGATCLK 4 #endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/altera/cyclone5-socdk/qts/sdram_config.h b/board/altera/cyclone5-socdk/qts/sdram_config.h index 8adbfec11f9..e3a8cfbfb38 100644 --- a/board/altera/cyclone5-socdk/qts/sdram_config.h +++ b/board/altera/cyclone5-socdk/qts/sdram_config.h @@ -7,76 +7,76 @@ #define __SOCFPGA_SDRAM_CONFIG_H__ /* SDRAM configuration */ -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 /* Sequencer auto configuration */ #define RW_MGR_ACTIVATE_0_AND_1 0x0D diff --git a/board/aries/mcvevk/qts/iocsr_config.h b/board/aries/mcvevk/qts/iocsr_config.h index e233d02b97d..dbcc1d719d4 100644 --- a/board/aries/mcvevk/qts/iocsr_config.h +++ b/board/aries/mcvevk/qts/iocsr_config.h @@ -6,10 +6,10 @@ #ifndef __SOCFPGA_IOCSR_CONFIG_H__ #define __SOCFPGA_IOCSR_CONFIG_H__ -#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 const unsigned long iocsr_scan_chain0_table[] = { 0x00000000, diff --git a/board/aries/mcvevk/qts/pll_config.h b/board/aries/mcvevk/qts/pll_config.h index 4fa868e458f..62cf6796afc 100644 --- a/board/aries/mcvevk/qts/pll_config.h +++ b/board/aries/mcvevk/qts/pll_config.h @@ -6,79 +6,79 @@ #ifndef __SOCFPGA_PLL_CONFIG_H__ #define __SOCFPGA_PLL_CONFIG_H__ -#define CONFIG_HPS_DBCTRL_STAYOSC1 1 +#define CFG_HPS_DBCTRL_STAYOSC1 1 -#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1 -#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1 -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 -#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 1 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 1 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1 -#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 -#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 -#define CONFIG_HPS_CLK_EMAC0_HZ 250000000 -#define CONFIG_HPS_CLK_EMAC1_HZ 1953125 -#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 -#define CONFIG_HPS_CLK_NAND_HZ 50000000 -#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 -#define CONFIG_HPS_CLK_QSPI_HZ 3125000 -#define CONFIG_HPS_CLK_SPIM_HZ 200000000 -#define CONFIG_HPS_CLK_CAN0_HZ 100000000 -#define CONFIG_HPS_CLK_CAN1_HZ 100000000 -#define CONFIG_HPS_CLK_GPIODB_HZ 32000 -#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 -#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 800000000 +#define CFG_HPS_CLK_EMAC0_HZ 250000000 +#define CFG_HPS_CLK_EMAC1_HZ 1953125 +#define CFG_HPS_CLK_USBCLK_HZ 200000000 +#define CFG_HPS_CLK_NAND_HZ 50000000 +#define CFG_HPS_CLK_SDMMC_HZ 200000000 +#define CFG_HPS_CLK_QSPI_HZ 3125000 +#define CFG_HPS_CLK_SPIM_HZ 200000000 +#define CFG_HPS_CLK_CAN0_HZ 100000000 +#define CFG_HPS_CLK_CAN1_HZ 100000000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000 -#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 3 +#define CFG_HPS_ALTERAGRP_DBGATCLK 3 #endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/aries/mcvevk/qts/sdram_config.h b/board/aries/mcvevk/qts/sdram_config.h index fd72926a89e..c6a24f5632a 100644 --- a/board/aries/mcvevk/qts/sdram_config.h +++ b/board/aries/mcvevk/qts/sdram_config.h @@ -7,76 +7,76 @@ #define __SOCFPGA_SDRAM_CONFIG_H__ /* SDRAM configuration */ -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 /* Sequencer auto configuration */ #define RW_MGR_ACTIVATE_0_AND_1 0x0D diff --git a/board/devboards/dbm-soc1/qts/iocsr_config.h b/board/devboards/dbm-soc1/qts/iocsr_config.h index 99ed62bb503..56b2130671a 100644 --- a/board/devboards/dbm-soc1/qts/iocsr_config.h +++ b/board/devboards/dbm-soc1/qts/iocsr_config.h @@ -6,10 +6,10 @@ #ifndef __SOCFPGA_IOCSR_CONFIG_H__ #define __SOCFPGA_IOCSR_CONFIG_H__ -#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 const unsigned long iocsr_scan_chain0_table[] = { 0x00000000, diff --git a/board/devboards/dbm-soc1/qts/pll_config.h b/board/devboards/dbm-soc1/qts/pll_config.h index f6ffa08654a..104e324d8a4 100644 --- a/board/devboards/dbm-soc1/qts/pll_config.h +++ b/board/devboards/dbm-soc1/qts/pll_config.h @@ -6,79 +6,79 @@ #ifndef __SOCFPGA_PLL_CONFIG_H__ #define __SOCFPGA_PLL_CONFIG_H__ -#define CONFIG_HPS_DBCTRL_STAYOSC1 1 +#define CFG_HPS_DBCTRL_STAYOSC1 1 -#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1 -#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 -#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1 -#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 -#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 -#define CONFIG_HPS_CLK_EMAC0_HZ 1953125 -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 -#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 -#define CONFIG_HPS_CLK_NAND_HZ 50000000 -#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 -#define CONFIG_HPS_CLK_QSPI_HZ 400000000 -#define CONFIG_HPS_CLK_SPIM_HZ 200000000 -#define CONFIG_HPS_CLK_CAN0_HZ 12500000 -#define CONFIG_HPS_CLK_CAN1_HZ 12500000 -#define CONFIG_HPS_CLK_GPIODB_HZ 32000 -#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 -#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 800000000 +#define CFG_HPS_CLK_EMAC0_HZ 1953125 +#define CFG_HPS_CLK_EMAC1_HZ 250000000 +#define CFG_HPS_CLK_USBCLK_HZ 200000000 +#define CFG_HPS_CLK_NAND_HZ 50000000 +#define CFG_HPS_CLK_SDMMC_HZ 200000000 +#define CFG_HPS_CLK_QSPI_HZ 400000000 +#define CFG_HPS_CLK_SPIM_HZ 200000000 +#define CFG_HPS_CLK_CAN0_HZ 12500000 +#define CFG_HPS_CLK_CAN1_HZ 12500000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000 -#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 3 +#define CFG_HPS_ALTERAGRP_DBGATCLK 3 #endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/devboards/dbm-soc1/qts/sdram_config.h b/board/devboards/dbm-soc1/qts/sdram_config.h index 2022969bed9..2c4559b1aad 100644 --- a/board/devboards/dbm-soc1/qts/sdram_config.h +++ b/board/devboards/dbm-soc1/qts/sdram_config.h @@ -7,76 +7,76 @@ #define __SOCFPGA_SDRAM_CONFIG_H__ /* SDRAM configuration */ -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 /* Sequencer auto configuration */ #define RW_MGR_ACTIVATE_0_AND_1 0x0D diff --git a/board/ebv/socrates/qts/iocsr_config.h b/board/ebv/socrates/qts/iocsr_config.h index 18b9c6ce4df..c24b5cb5f0b 100644 --- a/board/ebv/socrates/qts/iocsr_config.h +++ b/board/ebv/socrates/qts/iocsr_config.h @@ -6,10 +6,10 @@ #ifndef __SOCFPGA_IOCSR_CONFIG_H__ #define __SOCFPGA_IOCSR_CONFIG_H__ -#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 const unsigned long iocsr_scan_chain0_table[] = { 0x00000000, diff --git a/board/ebv/socrates/qts/pll_config.h b/board/ebv/socrates/qts/pll_config.h index 71d3674758f..eaa18c1c802 100644 --- a/board/ebv/socrates/qts/pll_config.h +++ b/board/ebv/socrates/qts/pll_config.h @@ -6,79 +6,79 @@ #ifndef __SOCFPGA_PLL_CONFIG_H__ #define __SOCFPGA_PLL_CONFIG_H__ -#define CONFIG_HPS_DBCTRL_STAYOSC1 1 +#define CFG_HPS_DBCTRL_STAYOSC1 1 -#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1 -#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 -#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 1 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1 -#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 79 -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 2 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 79 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 -#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 666666666 -#define CONFIG_HPS_CLK_EMAC0_HZ 1953125 -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 -#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 -#define CONFIG_HPS_CLK_NAND_HZ 50000000 -#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 -#define CONFIG_HPS_CLK_QSPI_HZ 400000000 -#define CONFIG_HPS_CLK_SPIM_HZ 200000000 -#define CONFIG_HPS_CLK_CAN0_HZ 100000000 -#define CONFIG_HPS_CLK_CAN1_HZ 12500000 -#define CONFIG_HPS_CLK_GPIODB_HZ 32000 -#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 -#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 666666666 +#define CFG_HPS_CLK_EMAC0_HZ 1953125 +#define CFG_HPS_CLK_EMAC1_HZ 250000000 +#define CFG_HPS_CLK_USBCLK_HZ 200000000 +#define CFG_HPS_CLK_NAND_HZ 50000000 +#define CFG_HPS_CLK_SDMMC_HZ 200000000 +#define CFG_HPS_CLK_QSPI_HZ 400000000 +#define CFG_HPS_CLK_SPIM_HZ 200000000 +#define CFG_HPS_CLK_CAN0_HZ 100000000 +#define CFG_HPS_CLK_CAN1_HZ 12500000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000 -#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 3 +#define CFG_HPS_ALTERAGRP_DBGATCLK 3 #endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/ebv/socrates/qts/sdram_config.h b/board/ebv/socrates/qts/sdram_config.h index 2f8465bf77c..318ef0cd1dd 100644 --- a/board/ebv/socrates/qts/sdram_config.h +++ b/board/ebv/socrates/qts/sdram_config.h @@ -7,76 +7,76 @@ #define __SOCFPGA_SDRAM_CONFIG_H__ /* SDRAM configuration */ -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 117 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1300 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 12 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 117 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1300 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 12 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 /* Sequencer auto configuration */ #define RW_MGR_ACTIVATE_0_AND_1 0x0D diff --git a/board/is1/qts/iocsr_config.h b/board/is1/qts/iocsr_config.h index 1d2774aa41a..e54af2caed4 100644 --- a/board/is1/qts/iocsr_config.h +++ b/board/is1/qts/iocsr_config.h @@ -6,10 +6,10 @@ #ifndef __SOCFPGA_IOCSR_CONFIG_H__ #define __SOCFPGA_IOCSR_CONFIG_H__ -#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 const unsigned long iocsr_scan_chain0_table[] = { 0x00000000, diff --git a/board/is1/qts/pll_config.h b/board/is1/qts/pll_config.h index 218ab35c042..0a5f5dd196f 100644 --- a/board/is1/qts/pll_config.h +++ b/board/is1/qts/pll_config.h @@ -6,79 +6,79 @@ #ifndef __SOCFPGA_PLL_CONFIG_H__ #define __SOCFPGA_PLL_CONFIG_H__ -#define CONFIG_HPS_DBCTRL_STAYOSC1 1 +#define CFG_HPS_DBCTRL_STAYOSC1 1 -#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 59 -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4 -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 59 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1 -#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 39 -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 -#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 39 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1 -#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 -#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1500000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 -#define CONFIG_HPS_CLK_EMAC0_HZ 250000000 -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 -#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 -#define CONFIG_HPS_CLK_NAND_HZ 488281 -#define CONFIG_HPS_CLK_SDMMC_HZ 1953125 -#define CONFIG_HPS_CLK_QSPI_HZ 375000000 -#define CONFIG_HPS_CLK_SPIM_HZ 12500000 -#define CONFIG_HPS_CLK_CAN0_HZ 12500000 -#define CONFIG_HPS_CLK_CAN1_HZ 12500000 -#define CONFIG_HPS_CLK_GPIODB_HZ 32000 -#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 -#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1500000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 800000000 +#define CFG_HPS_CLK_EMAC0_HZ 250000000 +#define CFG_HPS_CLK_EMAC1_HZ 250000000 +#define CFG_HPS_CLK_USBCLK_HZ 200000000 +#define CFG_HPS_CLK_NAND_HZ 488281 +#define CFG_HPS_CLK_SDMMC_HZ 1953125 +#define CFG_HPS_CLK_QSPI_HZ 375000000 +#define CFG_HPS_CLK_SPIM_HZ 12500000 +#define CFG_HPS_CLK_CAN0_HZ 12500000 +#define CFG_HPS_CLK_CAN1_HZ 12500000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000 -#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 4 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4 +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 4 +#define CFG_HPS_ALTERAGRP_DBGATCLK 4 #endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/is1/qts/sdram_config.h b/board/is1/qts/sdram_config.h index 2573171abeb..d8521a7e024 100644 --- a/board/is1/qts/sdram_config.h +++ b/board/is1/qts/sdram_config.h @@ -7,76 +7,76 @@ #define __SOCFPGA_SDRAM_CONFIG_H__ /* SDRAM configuration */ -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 16 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 64 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x777 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 14 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 16 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 64 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x777 +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 /* Sequencer auto configuration */ #define RW_MGR_ACTIVATE_0_AND_1 0x0D diff --git a/board/keymile/secu1/qts/iocsr_config.h b/board/keymile/secu1/qts/iocsr_config.h index 7640c56db16..9f05fce8b30 100644 --- a/board/keymile/secu1/qts/iocsr_config.h +++ b/board/keymile/secu1/qts/iocsr_config.h @@ -6,10 +6,10 @@ #ifndef __SOCFPGA_IOCSR_CONFIG_H__ #define __SOCFPGA_IOCSR_CONFIG_H__ -#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 1337 -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 1528 -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 1337 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 1528 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 const unsigned long iocsr_scan_chain0_table[] = { 0x00100000, diff --git a/board/keymile/secu1/qts/pll_config.h b/board/keymile/secu1/qts/pll_config.h index f0c31860ca4..7bc704a1820 100644 --- a/board/keymile/secu1/qts/pll_config.h +++ b/board/keymile/secu1/qts/pll_config.h @@ -6,78 +6,78 @@ #ifndef __SOCFPGA_PLL_CONFIG_H__ #define __SOCFPGA_PLL_CONFIG_H__ -#define CONFIG_HPS_DBCTRL_STAYOSC1 1 +#define CFG_HPS_DBCTRL_STAYOSC1 1 -#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 39 -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 39 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1 -#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 24 -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 7 -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 4 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 1 -#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 24 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 7 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 4 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 1 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1 -#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 14 -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 14 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 -#define CONFIG_HPS_CLK_OSC1_HZ 40000000 -#define CONFIG_HPS_CLK_OSC2_HZ 40000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 600000000 -#define CONFIG_HPS_CLK_EMAC0_HZ 250000000 -#define CONFIG_HPS_CLK_EMAC1_HZ 1953125 -#define CONFIG_HPS_CLK_USBCLK_HZ 12500000 -#define CONFIG_HPS_CLK_NAND_HZ 31250000 -#define CONFIG_HPS_CLK_SDMMC_HZ 3125000 -#define CONFIG_HPS_CLK_QSPI_HZ 3125000 -#define CONFIG_HPS_CLK_SPIM_HZ 200000000 -#define CONFIG_HPS_CLK_CAN0_HZ 12500000 -#define CONFIG_HPS_CLK_CAN1_HZ 12500000 -#define CONFIG_HPS_CLK_GPIODB_HZ 32000 -#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 -#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 +#define CFG_HPS_CLK_OSC1_HZ 40000000 +#define CFG_HPS_CLK_OSC2_HZ 40000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 600000000 +#define CFG_HPS_CLK_EMAC0_HZ 250000000 +#define CFG_HPS_CLK_EMAC1_HZ 1953125 +#define CFG_HPS_CLK_USBCLK_HZ 12500000 +#define CFG_HPS_CLK_NAND_HZ 31250000 +#define CFG_HPS_CLK_SDMMC_HZ 3125000 +#define CFG_HPS_CLK_QSPI_HZ 3125000 +#define CFG_HPS_CLK_SPIM_HZ 200000000 +#define CFG_HPS_CLK_CAN0_HZ 12500000 +#define CFG_HPS_CLK_CAN1_HZ 12500000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000 -#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 3 +#define CFG_HPS_ALTERAGRP_DBGATCLK 3 #endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/keymile/secu1/qts/sdram_config.h b/board/keymile/secu1/qts/sdram_config.h index b0ff86ef381..a0ce0b26ca9 100644 --- a/board/keymile/secu1/qts/sdram_config.h +++ b/board/keymile/secu1/qts/sdram_config.h @@ -8,76 +8,76 @@ #define __SOCFPGA_SDRAM_CONFIG_H__ /* SDRAM configuration */ -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 60 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 2341 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 13 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 3 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 3 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 3 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 14 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 5 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 60 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 2341 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 13 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 3 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 3 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 3 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 /* Sequencer auto configuration */ #define RW_MGR_ACTIVATE_0_AND_1 0x11 diff --git a/board/softing/vining_fpga/qts/iocsr_config.h b/board/softing/vining_fpga/qts/iocsr_config.h index 8c78aecdd3d..4059ed5ad12 100644 --- a/board/softing/vining_fpga/qts/iocsr_config.h +++ b/board/softing/vining_fpga/qts/iocsr_config.h @@ -6,10 +6,10 @@ #ifndef __SOCFPGA_IOCSR_CONFIG_H__ #define __SOCFPGA_IOCSR_CONFIG_H__ -#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 const unsigned long iocsr_scan_chain0_table[] = { 0x00000000, diff --git a/board/softing/vining_fpga/qts/pll_config.h b/board/softing/vining_fpga/qts/pll_config.h index fa046183369..40bc8f7f7c1 100644 --- a/board/softing/vining_fpga/qts/pll_config.h +++ b/board/softing/vining_fpga/qts/pll_config.h @@ -6,79 +6,79 @@ #ifndef __SOCFPGA_PLL_CONFIG_H__ #define __SOCFPGA_PLL_CONFIG_H__ -#define CONFIG_HPS_DBCTRL_STAYOSC1 1 +#define CFG_HPS_DBCTRL_STAYOSC1 1 -#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4 -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1 -#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 -#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1 -#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 -#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 -#define CONFIG_HPS_CLK_EMAC0_HZ 250000000 -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 -#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 -#define CONFIG_HPS_CLK_NAND_HZ 488281 -#define CONFIG_HPS_CLK_SDMMC_HZ 1953125 -#define CONFIG_HPS_CLK_QSPI_HZ 320000000 -#define CONFIG_HPS_CLK_SPIM_HZ 200000000 -#define CONFIG_HPS_CLK_CAN0_HZ 12500000 -#define CONFIG_HPS_CLK_CAN1_HZ 12500000 -#define CONFIG_HPS_CLK_GPIODB_HZ 32000 -#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 -#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 800000000 +#define CFG_HPS_CLK_EMAC0_HZ 250000000 +#define CFG_HPS_CLK_EMAC1_HZ 250000000 +#define CFG_HPS_CLK_USBCLK_HZ 200000000 +#define CFG_HPS_CLK_NAND_HZ 488281 +#define CFG_HPS_CLK_SDMMC_HZ 1953125 +#define CFG_HPS_CLK_QSPI_HZ 320000000 +#define CFG_HPS_CLK_SPIM_HZ 200000000 +#define CFG_HPS_CLK_CAN0_HZ 12500000 +#define CFG_HPS_CLK_CAN1_HZ 12500000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000 -#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 3 +#define CFG_HPS_ALTERAGRP_DBGATCLK 3 #endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/softing/vining_fpga/qts/sdram_config.h b/board/softing/vining_fpga/qts/sdram_config.h index ec067eb473d..27e3f3b2a57 100644 --- a/board/softing/vining_fpga/qts/sdram_config.h +++ b/board/softing/vining_fpga/qts/sdram_config.h @@ -7,76 +7,76 @@ #define __SOCFPGA_SDRAM_CONFIG_H__ /* SDRAM configuration */ -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 /* Sequencer auto configuration */ #define RW_MGR_ACTIVATE_0_AND_1 0x0D diff --git a/board/sr1500/qts/iocsr_config.h b/board/sr1500/qts/iocsr_config.h index b3b167fa7fc..2622b960314 100644 --- a/board/sr1500/qts/iocsr_config.h +++ b/board/sr1500/qts/iocsr_config.h @@ -6,10 +6,10 @@ #ifndef __SOCFPGA_IOCSR_CONFIG_H__ #define __SOCFPGA_IOCSR_CONFIG_H__ -#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 const unsigned long iocsr_scan_chain0_table[] = { 0x00100000, diff --git a/board/sr1500/qts/pll_config.h b/board/sr1500/qts/pll_config.h index 02f068f7424..885fe91eeba 100644 --- a/board/sr1500/qts/pll_config.h +++ b/board/sr1500/qts/pll_config.h @@ -6,79 +6,79 @@ #ifndef __SOCFPGA_PLL_CONFIG_H__ #define __SOCFPGA_PLL_CONFIG_H__ -#define CONFIG_HPS_DBCTRL_STAYOSC1 1 +#define CFG_HPS_DBCTRL_STAYOSC1 1 -#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1 -#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 -#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1 -#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 -#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 -#define CONFIG_HPS_CLK_EMAC0_HZ 1953125 -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 -#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 -#define CONFIG_HPS_CLK_NAND_HZ 50000000 -#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 -#define CONFIG_HPS_CLK_QSPI_HZ 400000000 -#define CONFIG_HPS_CLK_SPIM_HZ 12500000 -#define CONFIG_HPS_CLK_CAN0_HZ 12500000 -#define CONFIG_HPS_CLK_CAN1_HZ 12500000 -#define CONFIG_HPS_CLK_GPIODB_HZ 32000 -#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 -#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 800000000 +#define CFG_HPS_CLK_EMAC0_HZ 1953125 +#define CFG_HPS_CLK_EMAC1_HZ 250000000 +#define CFG_HPS_CLK_USBCLK_HZ 200000000 +#define CFG_HPS_CLK_NAND_HZ 50000000 +#define CFG_HPS_CLK_SDMMC_HZ 200000000 +#define CFG_HPS_CLK_QSPI_HZ 400000000 +#define CFG_HPS_CLK_SPIM_HZ 12500000 +#define CFG_HPS_CLK_CAN0_HZ 12500000 +#define CFG_HPS_CLK_CAN1_HZ 12500000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000 -#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 3 +#define CFG_HPS_ALTERAGRP_DBGATCLK 3 #endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/sr1500/qts/sdram_config.h b/board/sr1500/qts/sdram_config.h index d25354bb49c..3438221d686 100644 --- a/board/sr1500/qts/sdram_config.h +++ b/board/sr1500/qts/sdram_config.h @@ -7,76 +7,76 @@ #define __SOCFPGA_SDRAM_CONFIG_H__ /* SDRAM configuration */ -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x330 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x330 +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 /* Sequencer auto configuration */ #define RW_MGR_ACTIVATE_0_AND_1 0x0D diff --git a/board/terasic/de0-nano-soc/qts/iocsr_config.h b/board/terasic/de0-nano-soc/qts/iocsr_config.h index 6ff5bd57112..b856474b770 100644 --- a/board/terasic/de0-nano-soc/qts/iocsr_config.h +++ b/board/terasic/de0-nano-soc/qts/iocsr_config.h @@ -6,10 +6,10 @@ #ifndef __SOCFPGA_IOCSR_CONFIG_H__ #define __SOCFPGA_IOCSR_CONFIG_H__ -#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 const unsigned long iocsr_scan_chain0_table[] = { 0x00000000, diff --git a/board/terasic/de0-nano-soc/qts/pll_config.h b/board/terasic/de0-nano-soc/qts/pll_config.h index e439336d45a..36d8fd1df2c 100644 --- a/board/terasic/de0-nano-soc/qts/pll_config.h +++ b/board/terasic/de0-nano-soc/qts/pll_config.h @@ -6,78 +6,78 @@ #ifndef _PRELOADER_PLL_CONFIG_H_ #define _PRELOADER_PLL_CONFIG_H_ -#define CONFIG_HPS_DBCTRL_STAYOSC1 1 +#define CFG_HPS_DBCTRL_STAYOSC1 1 -#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73 -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 18 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 73 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 18 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1 -#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 19 -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 -#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 19 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1 -#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 -#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 -#define CONFIG_HPS_CLK_EMAC0_HZ 1953125 -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 -#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 -#define CONFIG_HPS_CLK_NAND_HZ 50000000 -#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 -#define CONFIG_HPS_CLK_QSPI_HZ 3613281 -#define CONFIG_HPS_CLK_SPIM_HZ 200000000 -#define CONFIG_HPS_CLK_CAN0_HZ 12500000 -#define CONFIG_HPS_CLK_CAN1_HZ 12500000 -#define CONFIG_HPS_CLK_GPIODB_HZ 32000 -#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 -#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1850000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 800000000 +#define CFG_HPS_CLK_EMAC0_HZ 1953125 +#define CFG_HPS_CLK_EMAC1_HZ 250000000 +#define CFG_HPS_CLK_USBCLK_HZ 200000000 +#define CFG_HPS_CLK_NAND_HZ 50000000 +#define CFG_HPS_CLK_SDMMC_HZ 200000000 +#define CFG_HPS_CLK_QSPI_HZ 3613281 +#define CFG_HPS_CLK_SPIM_HZ 200000000 +#define CFG_HPS_CLK_CAN0_HZ 12500000 +#define CFG_HPS_CLK_CAN1_HZ 12500000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000 -#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 4 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4 +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 4 +#define CFG_HPS_ALTERAGRP_DBGATCLK 4 #endif /* _PRELOADER_PLL_CONFIG_H_ */ diff --git a/board/terasic/de0-nano-soc/qts/sdram_config.h b/board/terasic/de0-nano-soc/qts/sdram_config.h index 0504dd688f9..3fb2f2a58b4 100644 --- a/board/terasic/de0-nano-soc/qts/sdram_config.h +++ b/board/terasic/de0-nano-soc/qts/sdram_config.h @@ -5,80 +5,80 @@ #ifndef __SDRAM_CONFIG_H #define __SDRAM_CONFIG_H -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED 0x1 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED 0x1 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED 0x3 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x311 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED 0x1 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED 0x1 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED 0x3 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x311 /* Sequencer auto configuration */ #define RW_MGR_ACTIVATE_0_AND_1 0x0D diff --git a/board/terasic/de1-soc/qts/iocsr_config.h b/board/terasic/de1-soc/qts/iocsr_config.h index c65183ed8c0..359fd0e4173 100644 --- a/board/terasic/de1-soc/qts/iocsr_config.h +++ b/board/terasic/de1-soc/qts/iocsr_config.h @@ -6,10 +6,10 @@ #ifndef __SOCFPGA_IOCSR_CONFIG_H__ #define __SOCFPGA_IOCSR_CONFIG_H__ -#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 const unsigned long iocsr_scan_chain0_table[] = { 0x00000000, diff --git a/board/terasic/de1-soc/qts/pll_config.h b/board/terasic/de1-soc/qts/pll_config.h index 4544f926935..2811e04c480 100644 --- a/board/terasic/de1-soc/qts/pll_config.h +++ b/board/terasic/de1-soc/qts/pll_config.h @@ -6,85 +6,85 @@ #ifndef __SOCFPGA_PLL_CONFIG_H__ #define __SOCFPGA_PLL_CONFIG_H__ -#define CONFIG_HPS_DBCTRL_STAYOSC1 1 +#define CFG_HPS_DBCTRL_STAYOSC1 1 -#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1 -#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 -#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1 -#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 -#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 -#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_EMAC0_HZ 1953125 -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 -#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 -#define CONFIG_HPS_CLK_NAND_HZ 50000000 -#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 -#define CONFIG_HPS_CLK_QSPI_HZ 400000000 -#define CONFIG_HPS_CLK_SPIM_HZ 200000000 -#define CONFIG_HPS_CLK_CAN0_HZ 12500000 -#define CONFIG_HPS_CLK_CAN1_HZ 12500000 -#define CONFIG_HPS_CLK_GPIODB_HZ 32000 -#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 -#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 800000000 +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_EMAC0_HZ 1953125 +#define CFG_HPS_CLK_EMAC1_HZ 250000000 +#define CFG_HPS_CLK_USBCLK_HZ 200000000 +#define CFG_HPS_CLK_NAND_HZ 50000000 +#define CFG_HPS_CLK_SDMMC_HZ 200000000 +#define CFG_HPS_CLK_QSPI_HZ 400000000 +#define CFG_HPS_CLK_SPIM_HZ 200000000 +#define CFG_HPS_CLK_CAN0_HZ 12500000 +#define CFG_HPS_CLK_CAN1_HZ 12500000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000 -#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 3 +#define CFG_HPS_ALTERAGRP_DBGATCLK 3 #endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/terasic/de1-soc/qts/sdram_config.h b/board/terasic/de1-soc/qts/sdram_config.h index c60426f2ff6..7b0ff2ce01b 100644 --- a/board/terasic/de1-soc/qts/sdram_config.h +++ b/board/terasic/de1-soc/qts/sdram_config.h @@ -7,76 +7,76 @@ #define __SOCFPGA_SDRAM_CONFIG_H__ /* SDRAM configuration */ -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 18 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 18 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 /* Sequencer auto configuration */ #define RW_MGR_ACTIVATE_0_AND_1 0x0D diff --git a/board/terasic/de10-nano/qts/iocsr_config.h b/board/terasic/de10-nano/qts/iocsr_config.h index bc5b7a07c7d..a889d3da348 100644 --- a/board/terasic/de10-nano/qts/iocsr_config.h +++ b/board/terasic/de10-nano/qts/iocsr_config.h @@ -6,10 +6,10 @@ #ifndef __SOCFPGA_IOCSR_CONFIG_H__ #define __SOCFPGA_IOCSR_CONFIG_H__ -#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 const unsigned long iocsr_scan_chain0_table[] = { 0x00000000, diff --git a/board/terasic/de10-nano/qts/pll_config.h b/board/terasic/de10-nano/qts/pll_config.h index 854936b2a33..192ffb4e27b 100644 --- a/board/terasic/de10-nano/qts/pll_config.h +++ b/board/terasic/de10-nano/qts/pll_config.h @@ -6,79 +6,79 @@ #ifndef __SOCFPGA_PLL_CONFIG_H__ #define __SOCFPGA_PLL_CONFIG_H__ -#define CONFIG_HPS_DBCTRL_STAYOSC1 1 +#define CFG_HPS_DBCTRL_STAYOSC1 1 -#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1 -#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 19 -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 -#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 19 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1 -#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 -#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 -#define CONFIG_HPS_CLK_EMAC0_HZ 1953125 -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 -#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 -#define CONFIG_HPS_CLK_NAND_HZ 50000000 -#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 -#define CONFIG_HPS_CLK_QSPI_HZ 3125000 -#define CONFIG_HPS_CLK_SPIM_HZ 200000000 -#define CONFIG_HPS_CLK_CAN0_HZ 12500000 -#define CONFIG_HPS_CLK_CAN1_HZ 12500000 -#define CONFIG_HPS_CLK_GPIODB_HZ 32000 -#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 -#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 800000000 +#define CFG_HPS_CLK_EMAC0_HZ 1953125 +#define CFG_HPS_CLK_EMAC1_HZ 250000000 +#define CFG_HPS_CLK_USBCLK_HZ 200000000 +#define CFG_HPS_CLK_NAND_HZ 50000000 +#define CFG_HPS_CLK_SDMMC_HZ 200000000 +#define CFG_HPS_CLK_QSPI_HZ 3125000 +#define CFG_HPS_CLK_SPIM_HZ 200000000 +#define CFG_HPS_CLK_CAN0_HZ 12500000 +#define CFG_HPS_CLK_CAN1_HZ 12500000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000 -#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 3 +#define CFG_HPS_ALTERAGRP_DBGATCLK 3 #endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/terasic/de10-nano/qts/sdram_config.h b/board/terasic/de10-nano/qts/sdram_config.h index 26910ef348b..abf29f25c1a 100644 --- a/board/terasic/de10-nano/qts/sdram_config.h +++ b/board/terasic/de10-nano/qts/sdram_config.h @@ -7,76 +7,76 @@ #define __SOCFPGA_SDRAM_CONFIG_H__ /* SDRAM configuration */ -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 /* Sequencer auto configuration */ #define RW_MGR_ACTIVATE_0_AND_1 0x0D diff --git a/board/terasic/de10-standard/qts/iocsr_config.h b/board/terasic/de10-standard/qts/iocsr_config.h index c062b5521fd..4aed74e8b29 100644 --- a/board/terasic/de10-standard/qts/iocsr_config.h +++ b/board/terasic/de10-standard/qts/iocsr_config.h @@ -6,10 +6,10 @@ #ifndef __SOCFPGA_IOCSR_CONFIG_H__ #define __SOCFPGA_IOCSR_CONFIG_H__ -#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 const unsigned long iocsr_scan_chain0_table[] = { 0x00000000, diff --git a/board/terasic/de10-standard/qts/pll_config.h b/board/terasic/de10-standard/qts/pll_config.h index b08a9779179..c1ecd4b8208 100644 --- a/board/terasic/de10-standard/qts/pll_config.h +++ b/board/terasic/de10-standard/qts/pll_config.h @@ -6,79 +6,79 @@ #ifndef __SOCFPGA_PLL_CONFIG_H__ #define __SOCFPGA_PLL_CONFIG_H__ -#define CONFIG_HPS_DBCTRL_STAYOSC1 1 +#define CFG_HPS_DBCTRL_STAYOSC1 1 -#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73 -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4 -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 18 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 73 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 18 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1 -#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 -#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1 -#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 -#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 -#define CONFIG_HPS_CLK_EMAC0_HZ 1953125 -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 -#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 -#define CONFIG_HPS_CLK_NAND_HZ 50000000 -#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 -#define CONFIG_HPS_CLK_QSPI_HZ 370000000 -#define CONFIG_HPS_CLK_SPIM_HZ 200000000 -#define CONFIG_HPS_CLK_CAN0_HZ 12500000 -#define CONFIG_HPS_CLK_CAN1_HZ 12500000 -#define CONFIG_HPS_CLK_GPIODB_HZ 32000 -#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 -#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1850000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 800000000 +#define CFG_HPS_CLK_EMAC0_HZ 1953125 +#define CFG_HPS_CLK_EMAC1_HZ 250000000 +#define CFG_HPS_CLK_USBCLK_HZ 200000000 +#define CFG_HPS_CLK_NAND_HZ 50000000 +#define CFG_HPS_CLK_SDMMC_HZ 200000000 +#define CFG_HPS_CLK_QSPI_HZ 370000000 +#define CFG_HPS_CLK_SPIM_HZ 200000000 +#define CFG_HPS_CLK_CAN0_HZ 12500000 +#define CFG_HPS_CLK_CAN1_HZ 12500000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000 -#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 4 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4 +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 4 +#define CFG_HPS_ALTERAGRP_DBGATCLK 4 #endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/terasic/de10-standard/qts/sdram_config.h b/board/terasic/de10-standard/qts/sdram_config.h index 630b5511a61..1bfa4277282 100644 --- a/board/terasic/de10-standard/qts/sdram_config.h +++ b/board/terasic/de10-standard/qts/sdram_config.h @@ -7,76 +7,76 @@ #define __SOCFPGA_SDRAM_CONFIG_H__ /* SDRAM configuration */ -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 11 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 18 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 11 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 18 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 /* Sequencer auto configuration */ #define RW_MGR_ACTIVATE_0_AND_1 0x0D diff --git a/board/terasic/sockit/qts/iocsr_config.h b/board/terasic/sockit/qts/iocsr_config.h index b8cb5f08ab6..7b72ae9c3c2 100644 --- a/board/terasic/sockit/qts/iocsr_config.h +++ b/board/terasic/sockit/qts/iocsr_config.h @@ -6,10 +6,10 @@ #ifndef __SOCFPGA_IOCSR_CONFIG_H__ #define __SOCFPGA_IOCSR_CONFIG_H__ -#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 const unsigned long iocsr_scan_chain0_table[] = { 0x00000000, diff --git a/board/terasic/sockit/qts/pll_config.h b/board/terasic/sockit/qts/pll_config.h index f6ffa08654a..104e324d8a4 100644 --- a/board/terasic/sockit/qts/pll_config.h +++ b/board/terasic/sockit/qts/pll_config.h @@ -6,79 +6,79 @@ #ifndef __SOCFPGA_PLL_CONFIG_H__ #define __SOCFPGA_PLL_CONFIG_H__ -#define CONFIG_HPS_DBCTRL_STAYOSC1 1 +#define CFG_HPS_DBCTRL_STAYOSC1 1 -#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1 -#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 -#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1 -#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 -#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 -#define CONFIG_HPS_CLK_EMAC0_HZ 1953125 -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 -#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 -#define CONFIG_HPS_CLK_NAND_HZ 50000000 -#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 -#define CONFIG_HPS_CLK_QSPI_HZ 400000000 -#define CONFIG_HPS_CLK_SPIM_HZ 200000000 -#define CONFIG_HPS_CLK_CAN0_HZ 12500000 -#define CONFIG_HPS_CLK_CAN1_HZ 12500000 -#define CONFIG_HPS_CLK_GPIODB_HZ 32000 -#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 -#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 800000000 +#define CFG_HPS_CLK_EMAC0_HZ 1953125 +#define CFG_HPS_CLK_EMAC1_HZ 250000000 +#define CFG_HPS_CLK_USBCLK_HZ 200000000 +#define CFG_HPS_CLK_NAND_HZ 50000000 +#define CFG_HPS_CLK_SDMMC_HZ 200000000 +#define CFG_HPS_CLK_QSPI_HZ 400000000 +#define CFG_HPS_CLK_SPIM_HZ 200000000 +#define CFG_HPS_CLK_CAN0_HZ 12500000 +#define CFG_HPS_CLK_CAN1_HZ 12500000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000 -#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 3 +#define CFG_HPS_ALTERAGRP_DBGATCLK 3 #endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/terasic/sockit/qts/sdram_config.h b/board/terasic/sockit/qts/sdram_config.h index 96cc3570341..efdbc855740 100644 --- a/board/terasic/sockit/qts/sdram_config.h +++ b/board/terasic/sockit/qts/sdram_config.h @@ -7,76 +7,76 @@ #define __SOCFPGA_SDRAM_CONFIG_H__ /* SDRAM configuration */ -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 11 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 12 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 11 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 12 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 /* Sequencer auto configuration */ #define RW_MGR_ACTIVATE_0_AND_1 0x0D |