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-rw-r--r--board/cadence/xtfpga/xtfpga.c12
-rw-r--r--board/freescale/common/cadmus.c2
-rw-r--r--board/freescale/common/cadmus.h2
-rw-r--r--board/freescale/ls1021aqds/ls1021aqds.c2
-rw-r--r--board/freescale/ls1088a/ls1088a.c2
-rw-r--r--board/freescale/p2041rdb/p2041rdb.c2
-rw-r--r--board/freescale/t102xrdb/spl.c7
-rw-r--r--board/freescale/t102xrdb/t102xrdb.c5
-rw-r--r--board/freescale/t104xrdb/spl.c7
-rw-r--r--board/freescale/t208xrdb/spl.c7
-rw-r--r--board/freescale/t208xrdb/t208xrdb.c5
-rw-r--r--board/freescale/t4rdb/spl.c7
-rw-r--r--board/keymile/kmcent2/kmcent2.c5
-rw-r--r--board/xes/common/fsl_8xxx_clk.c6
14 files changed, 23 insertions, 48 deletions
diff --git a/board/cadence/xtfpga/xtfpga.c b/board/cadence/xtfpga/xtfpga.c
index c26793d76cc..d30940d7c3e 100644
--- a/board/cadence/xtfpga/xtfpga.c
+++ b/board/cadence/xtfpga/xtfpga.c
@@ -49,7 +49,7 @@ int checkboard(void)
return 0;
}
-int board_postclk_init(void)
+unsigned long get_board_sys_clk(void)
{
/*
* Obtain CPU clock frequency from board and cache in global
@@ -58,11 +58,17 @@ int board_postclk_init(void)
*/
#ifdef CONFIG_SYS_FPGAREG_FREQ
- gd->cpu_clk = (*(volatile unsigned long *)CONFIG_SYS_FPGAREG_FREQ);
+ return (*(volatile unsigned long *)CONFIG_SYS_FPGAREG_FREQ);
#else
/* early Tensilica bitstreams lack this reg, but most run at 50 MHz */
- gd->cpu_clk = 50000000UL;
+ return 50000000;
#endif
+}
+
+int board_postclk_init(void)
+{
+ gd->cpu_clk = get_board_sys_clk();
+
return 0;
}
diff --git a/board/freescale/common/cadmus.c b/board/freescale/common/cadmus.c
index 7e7394f333e..b14abac9a1c 100644
--- a/board/freescale/common/cadmus.c
+++ b/board/freescale/common/cadmus.c
@@ -37,7 +37,7 @@ get_board_version(void)
unsigned long
-get_clock_freq(void)
+get_board_sys_clk(void)
{
volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
diff --git a/board/freescale/common/cadmus.h b/board/freescale/common/cadmus.h
index ddc2bb6c1f6..fb74e8f6db5 100644
--- a/board/freescale/common/cadmus.h
+++ b/board/freescale/common/cadmus.h
@@ -19,7 +19,7 @@ extern unsigned int get_board_version(void);
/*
* Returns either 33000000 or 66000000 as the SYS_CLK_FREQ.
*/
-extern unsigned long get_clock_freq(void);
+extern unsigned long get_board_sys_clk(void);
/*
diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c
index fbbd27d9d71..0647622cde5 100644
--- a/board/freescale/ls1021aqds/ls1021aqds.c
+++ b/board/freescale/ls1021aqds/ls1021aqds.c
@@ -102,6 +102,7 @@ int checkboard(void)
return 0;
}
+#ifdef CONFIG_DYNAMIC_SYS_CLK_FREQ
unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
@@ -126,6 +127,7 @@ unsigned long get_board_sys_clk(void)
}
return 66666666;
}
+#endif
#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ
unsigned long get_board_ddr_clk(void)
diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c
index 73c2077ecdb..8a112a699a6 100644
--- a/board/freescale/ls1088a/ls1088a.c
+++ b/board/freescale/ls1088a/ls1088a.c
@@ -374,6 +374,7 @@ bool if_board_diff_clk(void)
#endif
}
+#ifdef CONFIG_DYNAMIC_SYS_CLK_FREQ
unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
@@ -397,6 +398,7 @@ unsigned long get_board_sys_clk(void)
return 66666666;
}
+#endif
#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ
unsigned long get_board_ddr_clk(void)
diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c
index 4ece1e6ea0a..894fe8ee279 100644
--- a/board/freescale/p2041rdb/p2041rdb.c
+++ b/board/freescale/p2041rdb/p2041rdb.c
@@ -148,7 +148,7 @@ int board_early_init_r(void)
return 0;
}
-unsigned long get_board_sys_clk(unsigned long dummy)
+unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = CPLD_READ(sysclk_sw1);
diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c
index ac373d77247..7f59172076b 100644
--- a/board/freescale/t102xrdb/spl.c
+++ b/board/freescale/t102xrdb/spl.c
@@ -25,11 +25,6 @@ phys_size_t get_effective_memsize(void)
return CONFIG_SYS_L3_SIZE;
}
-unsigned long get_board_sys_clk(void)
-{
- return CONFIG_SYS_CLK_FREQ;
-}
-
#if defined(CONFIG_SPL_MMC_BOOT)
#define GPIO1_SD_SEL 0x00020000
int board_mmc_getcd(struct mmc *mmc)
@@ -74,7 +69,7 @@ void board_init_f(ulong bootflag)
#endif
/* initialize selected port with appropriate baud rate */
- sys_clk = get_board_sys_clk();
+ sys_clk = CONFIG_SYS_CLK_FREQ;
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
ccb_clk = sys_clk * plat_ratio / 2;
diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c
index ab7675e2090..539a5c73444 100644
--- a/board/freescale/t102xrdb/t102xrdb.c
+++ b/board/freescale/t102xrdb/t102xrdb.c
@@ -162,11 +162,6 @@ int board_early_init_r(void)
return 0;
}
-unsigned long get_board_sys_clk(void)
-{
- return CONFIG_SYS_CLK_FREQ;
-}
-
#ifdef CONFIG_TARGET_T1024RDB
void board_reset(void)
{
diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c
index c7df11100e0..6acc5161b6d 100644
--- a/board/freescale/t104xrdb/spl.c
+++ b/board/freescale/t104xrdb/spl.c
@@ -25,11 +25,6 @@ phys_size_t get_effective_memsize(void)
return CONFIG_SYS_L3_SIZE;
}
-unsigned long get_board_sys_clk(void)
-{
- return CONFIG_SYS_CLK_FREQ;
-}
-
#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
void board_init_f(ulong bootflag)
{
@@ -73,7 +68,7 @@ void board_init_f(ulong bootflag)
console_init_f();
/* initialize selected port with appropriate baud rate */
- sys_clk = get_board_sys_clk();
+ sys_clk = CONFIG_SYS_CLK_FREQ;
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
uart_clk = sys_clk * plat_ratio / 2;
diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c
index 2204a98ac8a..40aa0c5df39 100644
--- a/board/freescale/t208xrdb/spl.c
+++ b/board/freescale/t208xrdb/spl.c
@@ -24,11 +24,6 @@ phys_size_t get_effective_memsize(void)
return CONFIG_SYS_L3_SIZE;
}
-unsigned long get_board_sys_clk(void)
-{
- return CONFIG_SYS_CLK_FREQ;
-}
-
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, ccb_clk;
@@ -43,7 +38,7 @@ void board_init_f(ulong bootflag)
console_init_f();
/* initialize selected port with appropriate baud rate */
- sys_clk = get_board_sys_clk();
+ sys_clk = CONFIG_SYS_CLK_FREQ;
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
ccb_clk = sys_clk * plat_ratio / 2;
diff --git a/board/freescale/t208xrdb/t208xrdb.c b/board/freescale/t208xrdb/t208xrdb.c
index 3611dbbf327..1c8017b593a 100644
--- a/board/freescale/t208xrdb/t208xrdb.c
+++ b/board/freescale/t208xrdb/t208xrdb.c
@@ -109,11 +109,6 @@ int board_early_init_r(void)
return 0;
}
-unsigned long get_board_sys_clk(void)
-{
- return CONFIG_SYS_CLK_FREQ;
-}
-
int misc_init_r(void)
{
u8 reg;
diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c
index 69d1449b070..8c7421da81c 100644
--- a/board/freescale/t4rdb/spl.c
+++ b/board/freescale/t4rdb/spl.c
@@ -30,11 +30,6 @@ phys_size_t get_effective_memsize(void)
return CONFIG_SYS_L3_SIZE;
}
-unsigned long get_board_sys_clk(void)
-{
- return CONFIG_SYS_CLK_FREQ;
-}
-
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, ccb_clk;
@@ -52,7 +47,7 @@ void board_init_f(ulong bootflag)
console_init_f();
/* initialize selected port with appropriate baud rate */
- sys_clk = get_board_sys_clk();
+ sys_clk = CONFIG_SYS_CLK_FREQ;
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
ccb_clk = sys_clk * plat_ratio / 2;
diff --git a/board/keymile/kmcent2/kmcent2.c b/board/keymile/kmcent2/kmcent2.c
index 4f5164e63ca..ca24b960c76 100644
--- a/board/keymile/kmcent2/kmcent2.c
+++ b/board/keymile/kmcent2/kmcent2.c
@@ -181,11 +181,6 @@ unsigned long get_serial_clock(unsigned long dummy)
return (gd->bus_clk / 2);
}
-unsigned long get_board_sys_clk(unsigned long dummy)
-{
- return 66666666;
-}
-
int misc_init_f(void)
{
/* configure QRIO pis for i2c deblocking */
diff --git a/board/xes/common/fsl_8xxx_clk.c b/board/xes/common/fsl_8xxx_clk.c
index 8ca65ca8593..8c72c154456 100644
--- a/board/xes/common/fsl_8xxx_clk.c
+++ b/board/xes/common/fsl_8xxx_clk.c
@@ -9,7 +9,7 @@
/*
* Return SYSCLK input frequency - 50 MHz or 66 MHz depending on POR config
*/
-unsigned long get_board_sys_clk(ulong dummy)
+unsigned long get_board_sys_clk(void)
{
#if defined(CONFIG_MPC85xx)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
@@ -33,13 +33,13 @@ unsigned long get_board_sys_clk(ulong dummy)
* Return DDR input clock - synchronous with SYSCLK or 66 MHz
* Note: 86xx doesn't support asynchronous DDR clk
*/
-unsigned long get_board_ddr_clk(ulong dummy)
+unsigned long get_board_ddr_clk(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 ddr_ratio = (in_be32(&gur->porpllsr) & 0x00003e00) >> 9;
if (ddr_ratio == 0x7)
- return get_board_sys_clk(dummy);
+ return get_board_sys_clk();
#ifdef CONFIG_ARCH_P2020
if (in_be32(&gur->gpporcr) & 0x20000)
generated by cgit v1.2.3 (git 2.39.1) at 2024-11-10 13:17:22 +0000