diff options
Diffstat (limited to 'cpu/mcf52x2/speed.c')
| -rw-r--r-- | cpu/mcf52x2/speed.c | 35 |
1 files changed, 34 insertions, 1 deletions
diff --git a/cpu/mcf52x2/speed.c b/cpu/mcf52x2/speed.c index ac860b2c673..bc1e20023b1 100644 --- a/cpu/mcf52x2/speed.c +++ b/cpu/mcf52x2/speed.c @@ -2,6 +2,9 @@ * (C) Copyright 2003 * Josef Baumgartner <josef.baumgartner@telex.de> * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * Hayden Fraser (Hayden.Fraser@freescale.com) + * * See file CREDITS for list of people who contributed to this * project. * @@ -23,6 +26,7 @@ #include <common.h> #include <asm/processor.h> +#include <asm/immap.h> DECLARE_GLOBAL_DATA_PTR; @@ -31,8 +35,37 @@ DECLARE_GLOBAL_DATA_PTR; */ int get_clocks (void) { - gd->cpu_clk = CFG_CLK; +#if defined(CONFIG_M5249) || defined(CONFIG_M5253) + volatile unsigned long cpll = mbar2_readLong(MCFSIM_PLLCR); + unsigned long pllcr; + +#ifndef CFG_PLL_BYPASS + #ifdef CONFIG_M5249 + /* Setup the PLL to run at the specified speed */ +#ifdef CFG_FAST_CLK + pllcr = 0x925a3100; /* ~140MHz clock (PLL bypass = 0) */ +#else + pllcr = 0x135a4140; /* ~72MHz clock (PLL bypass = 0) */ +#endif +#endif /* CONFIG_M5249 */ + +#ifdef CONFIG_M5253 + pllcr = CFG_PLLCR; +#endif /* CONFIG_M5253 */ + + cpll = cpll & 0xfffffffe; /* Set PLL bypass mode = 0 (PSTCLK = crystal) */ + mbar2_writeLong(MCFSIM_PLLCR, cpll); /* Set the PLL to bypass mode (PSTCLK = crystal) */ + mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* set the clock speed */ + pllcr ^= 0x00000001; /* Set pll bypass to 1 */ + mbar2_writeLong(MCFSIM_PLLCR, pllcr); /* Start locking (pll bypass = 1) */ + udelay(0x20); /* Wait for a lock ... */ +#endif /* #ifndef CFG_PLL_BYPASS */ + +#endif /* CONFIG_M5249 || CONFIG_M5253 */ + + gd->cpu_clk = CFG_CLK; +#if defined(CONFIG_M5249) || defined(CONFIG_M5253) gd->bus_clk = gd->cpu_clk / 2; #else gd->bus_clk = gd->cpu_clk; |