diff options
Diffstat (limited to 'cpu/mcf5445x/start.S')
| -rw-r--r-- | cpu/mcf5445x/start.S | 256 |
1 files changed, 253 insertions, 3 deletions
diff --git a/cpu/mcf5445x/start.S b/cpu/mcf5445x/start.S index 89ec7bcc914..2a6019bbfc7 100644 --- a/cpu/mcf5445x/start.S +++ b/cpu/mcf5445x/start.S @@ -46,15 +46,30 @@ addl #60,%sp; /* space for 15 regs */ \ rte; +#if defined(CONFIG_CF_SBF) +#define ASM_DRAMINIT (asm_dram_init - TEXT_BASE + CFG_INIT_RAM_ADDR) +#define ASM_SBF_IMG_HDR (asm_sbf_img_hdr - TEXT_BASE + CFG_INIT_RAM_ADDR) +#endif + .text + /* * Vector table. This is used for initial platform startup. * These vectors are to catch any un-intended traps. */ _vectors: +#if defined(CONFIG_CF_SBF) + +INITSP: .long 0 /* Initial SP */ +INITPC: .long ASM_DRAMINIT /* Initial PC */ + +#else + +INITSP: .long 0 /* Initial SP */ +INITPC: .long _START /* Initial PC */ + +#endif -INITSP: .long 0x00000000 /* Initial SP */ -INITPC: .long _START /* Initial PC */ vector02: .long _FAULT /* Access Error */ vector03: .long _FAULT /* Address Error */ vector04: .long _FAULT /* Illegal Instruction */ @@ -83,6 +98,8 @@ vector1D: .long _FAULT /* Autovector Level 5 */ vector1E: .long _FAULT /* Autovector Level 6 */ vector1F: .long _FAULT /* Autovector Level 7 */ +#if !defined(CONFIG_CF_SBF) + /* TRAP #0 - #15 */ vector20_2F: .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT @@ -122,9 +139,237 @@ vector192_255: .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT .long _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT, _FAULT +#endif - .text +#if defined(CONFIG_CF_SBF) + /* Image header: chksum 4 bytes, len 4 bytes, img dest 4 bytes */ +asm_sbf_img_hdr: + .long 0x00000000 /* checksum, not yet implemented */ + .long 0x00030000 /* image length */ + .long TEXT_BASE /* image to be relocated at */ + +asm_dram_init: + move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0 + movec %d0, %RAMBAR1 /* init Rambar */ + move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_SP_OFFSET), %sp + clr.l %sp@- + + /* Must disable global address */ + move.l #0xFC008000, %a1 + move.l #(CFG_CS0_BASE), (%a1) + move.l #0xFC008008, %a1 + move.l #(CFG_CS0_CTRL), (%a1) + move.l #0xFC008004, %a1 + move.l #(CFG_CS0_MASK), (%a1) + + /* + * Dram Initialization + * a1, a2, and d0 + */ + /* mscr sdram */ + move.l #0xFC0A4074, %a1 + move.b #(CFG_SDRAM_DRV_STRENGTH), (%a1) + nop + + /* SDRAM Chip 0 and 1 */ + move.l #0xFC0B8110, %a1 + move.l #0xFC0B8114, %a2 + + /* calculate the size */ + move.l #0x13, %d1 + move.l #(CFG_SDRAM_SIZE), %d2 +#ifdef CFG_SDRAM_BASE1 + lsr.l #1, %d2 +#endif + +dramsz_loop: + lsr.l #1, %d2 + add.l #1, %d1 + cmp.l #1, %d2 + bne dramsz_loop + + /* SDRAM Chip 0 and 1 */ + move.l #(CFG_SDRAM_BASE), (%a1) + or.l %d1, (%a1) +#ifdef CFG_SDRAM_BASE1 + move.l #(CFG_SDRAM_BASE1), (%a2) + or.l %d1, (%a2) +#endif + nop + + /* dram cfg1 and cfg2 */ + move.l #0xFC0B8008, %a1 + move.l #(CFG_SDRAM_CFG1), (%a1) + nop + move.l #0xFC0B800C, %a2 + move.l #(CFG_SDRAM_CFG2), (%a2) + nop + + move.l #0xFC0B8000, %a1 /* Mode */ + move.l #0xFC0B8004, %a2 /* Ctrl */ + +#ifdef CONFIG_M54455EVB + /* Issue PALL */ + move.l #(CFG_SDRAM_CTRL + 2), (%a2) + nop + + /* Issue LEMR */ + move.l #(CFG_SDRAM_EMOD + 0x408), (%a1) + nop + move.l #(CFG_SDRAM_MODE + 0x300), (%a1) + nop + + move.l #1000, %d0 +wait1000: + nop + subq.l #1, %d0 + bne wait1000 +#endif + + /* Issue PALL */ + move.l #(CFG_SDRAM_CTRL + 2), (%a2) + nop + + /* Perform two refresh cycles */ + move.l #(CFG_SDRAM_CTRL + 4), %d0 + nop + move.l %d0, (%a2) + move.l %d0, (%a2) + nop +#ifdef CONFIG_M54455EVB + move.l #(CFG_SDRAM_MODE + 0x200), (%a1) + nop +#elif defined(CONFIG_M54451EVB) + /* Issue LEMR */ + move.l #(CFG_SDRAM_MODE), (%a2) + nop + move.l #(CFG_SDRAM_EMOD), (%a2) + nop +#endif + + move.l #500, %d0 +wait500: + nop + subq.l #1, %d0 + bne wait500 + + move.l #(CFG_SDRAM_CTRL), %d0 + and.l #0x7FFFFFFF, %d0 +#ifdef CONFIG_M54455EVB + or.l #0x10000c00, %d0 +#elif defined(CONFIG_M54451EVB) + or.l #0x10000000, %d0 +#endif + move.l %d0, (%a2) + nop + + /* + * DSPI Initialization + * a0 - general, sram - 0x80008000 - 32, see M54455EVB.h + * a1 - dspi status + * a2 - dtfr + * a3 - drfr + * a4 - Dst addr + */ + /* Enable pins for DSPI mode - chip-selects are enabled later */ + move.l #0xFC0A4063, %a0 + move.b #0x7F, (%a0) + + /* Configure DSPI module */ + move.l #0xFC05C000, %a0 + move.l #0x80FF0C00, (%a0) /* Master, clear TX/RX FIFO */ + + move.l #0xFC05C00C, %a0 + move.l #0x3E000011, (%a0) + + move.l #0xFC05C034, %a2 /* dtfr */ + move.l #0xFC05C03B, %a3 /* drfr */ + + move.l #(ASM_SBF_IMG_HDR + 4), %a1 + move.l (%a1)+, %d5 + move.l (%a1), %a4 + + move.l #(CFG_INIT_RAM_ADDR + CFG_SBFHDR_DATA_OFFSET), %a0 + move.l #(CFG_SBFHDR_SIZE), %d4 + + move.l #0xFC05C02C, %a1 /* dspi status */ + + /* Issue commands and address */ + move.l #0x8002000B, %d2 /* Fast Read Cmd */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.l #0x80020000, %d2 /* Address byte 2 */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.l #0x80020000, %d2 /* Address byte 1 */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.l #0x80020000, %d2 /* Address byte 0 */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.l #0x80020000, %d2 /* Dummy Wr and Rd */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + /* Transfer serial boot header to sram */ +asm_dspi_rd_loop1: + move.l #0x80020000, %d2 + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.b %d1, (%a0) /* read, copy to dst */ + + add.l #1, %a0 /* inc dst by 1 */ + sub.l #1, %d4 /* dec cnt by 1 */ + bne asm_dspi_rd_loop1 + + /* Transfer u-boot from serial flash to memory */ +asm_dspi_rd_loop2: + move.l #0x80020000, %d2 + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + move.b %d1, (%a4) /* read, copy to dst */ + + add.l #1, %a4 /* inc dst by 1 */ + sub.l #1, %d5 /* dec cnt by 1 */ + bne asm_dspi_rd_loop2 + + move.l #0x00020000, %d2 /* Terminate */ + jsr asm_dspi_wr_status + jsr asm_dspi_rd_status + + /* jump to memory and execute */ + move.l #(TEXT_BASE + 0x400), %a0 + jmp (%a0) + +asm_dspi_wr_status: + move.l (%a1), %d0 /* status */ + and.l #0x0000F000, %d0 + cmp.l #0x00003000, %d0 + bgt asm_dspi_wr_status + + move.l %d2, (%a2) + rts + +asm_dspi_rd_status: + move.l (%a1), %d0 /* status */ + and.l #0x000000F0, %d0 + lsr.l #4, %d0 + cmp.l #0, %d0 + beq asm_dspi_rd_status + + move.b (%a3), %d1 + rts +#endif /* CONFIG_CF_SBF */ + + .text + . = 0x400 .globl _start _start: nop @@ -132,11 +377,16 @@ _start: move.w #0x2700,%sr /* Mask off Interrupt */ /* Set vector base register at the beginning of the Flash */ +#if defined(CONFIG_CF_SBF) + move.l #TEXT_BASE, %d0 + movec %d0, %VBR +#else move.l #CFG_FLASH_BASE, %d0 movec %d0, %VBR move.l #(CFG_INIT_RAM_ADDR + CFG_INIT_RAM_CTRL), %d0 movec %d0, %RAMBAR1 +#endif /* initialize general use internal ram */ move.l #0, %d0 |