6 files changed, 49 insertions, 52 deletions
diff --git a/cpu/mpc86xx/Makefile b/cpu/mpc86xx/Makefile
index 34a97555621..daca79ad4f2 100644
--- a/cpu/mpc86xx/Makefile
+++ b/cpu/mpc86xx/Makefile
@@ -29,26 +29,23 @@ include $(TOPDIR)/config.mk
 LIB	= $(obj)lib$(CPU).a
 
 START	= start.o
-SOBJS	= cache.o
 
-ifneq ($(CONFIG_NUM_CPUS),1)
-COBJS-y += mp.o
-SOBJS += release.o
-endif
-COBJS-y	+= traps.o
+SOBJS-y += cache.o
+SOBJS-$(CONFIG_MP) += release.o
+
 COBJS-y	+= cpu.o
 COBJS-y	+= cpu_init.o
-COBJS-y	+= speed.o
-COBJS-y	+= interrupts.o
-
-COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
-
-COBJS-$(CONFIG_MPC8641) += ddr-8641.o
 # 8610 & 8641 are identical w/regards to DDR
 COBJS-$(CONFIG_MPC8610) += ddr-8641.o
+COBJS-$(CONFIG_MPC8641) += ddr-8641.o
+COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
+COBJS-y	+= interrupts.o
+COBJS-$(CONFIG_MP) += mp.o
+COBJS-y	+= speed.o
+COBJS-y	+= traps.o
 
-SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
-OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS-y))
+SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
 START	:= $(addprefix $(obj),$(START))
 
 all:	$(obj).depend $(START) $(LIB)
diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c
index 4f29122f409..49528aae713 100644
--- a/cpu/mpc86xx/cpu_init.c
+++ b/cpu/mpc86xx/cpu_init.c
@@ -31,7 +31,7 @@
 #include <mpc86xx.h>
 #include <asm/mmu.h>
 #include <asm/fsl_law.h>
-#include "mp.h"
+#include <asm/mp.h>
 
 void setup_bats(void);
 
diff --git a/cpu/mpc86xx/fdt.c b/cpu/mpc86xx/fdt.c
index 383b06b5ae6..a36ee30c3f0 100644
--- a/cpu/mpc86xx/fdt.c
+++ b/cpu/mpc86xx/fdt.c
@@ -9,15 +9,15 @@
 #include <common.h>
 #include <libfdt.h>
 #include <fdt_support.h>
-#include "mp.h"
+#include <asm/mp.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
-#if (CONFIG_NUM_CPUS > 1)
+#ifdef CONFIG_MP
 	int off;
-	u32 bootpg;
+	u32 bootpg = determine_mp_bootpg();
 #endif
 
 	do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
@@ -48,13 +48,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 			       "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
 #endif
 
-#if (CONFIG_NUM_CPUS > 1)
-	/* if we have 4G or more of memory, put the boot page at 4Gb-1M */
-	if (gd->ram_size > 0xfffff000)
-		bootpg = 0xfff00000;
-	else
-		bootpg = gd->ram_size - (1024 * 1024);
-
+#ifdef CONFIG_MP
 	/* Reserve the boot page so OSes dont use it */
 	off = fdt_add_mem_rsv(blob, bootpg, (u64)4096);
 	if (off < 0)
diff --git a/cpu/mpc86xx/mp.c b/cpu/mpc86xx/mp.c
index 5014401ddc2..2940673c7c7 100644
--- a/cpu/mpc86xx/mp.c
+++ b/cpu/mpc86xx/mp.c
@@ -4,20 +4,45 @@
 #include <ioports.h>
 #include <lmb.h>
 #include <asm/io.h>
-#include "mp.h"
+#include <asm/mp.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if (CONFIG_NUM_CPUS > 1)
-void cpu_mp_lmb_reserve(struct lmb *lmb)
+int cpu_reset(int nr)
+{
+	/* dummy function so common/cmd_mp.c will build
+	 * should be implemented in the future, when cpu_release()
+	 * is supported.  Be aware there may be a similiar bug
+	 * as exists on MPC85xx w/its PIC having a timing window
+	 * associated to resetting the core */
+	return 1;
+}
+
+int cpu_status(int nr)
 {
-	u32 bootpg;
+	/* dummy function so common/cmd_mp.c will build */
+	return 0;
+}
+
+int cpu_release(int nr, int argc, char *argv[])
+{
+	/* dummy function so common/cmd_mp.c will build
+	 * should be implemented in the future */
+	return 1;
+}
 
+u32 determine_mp_bootpg(void)
+{
 	/* if we have 4G or more of memory, put the boot page at 4Gb-1M */
 	if ((u64)gd->ram_size > 0xfffff000)
-		bootpg = 0xfff00000;
-	else
-		bootpg = gd->ram_size - (1024 * 1024);
+		return (0xfff00000);
+
+	return (gd->ram_size - (1024 * 1024));
+}
+
+void cpu_mp_lmb_reserve(struct lmb *lmb)
+{
+	u32 bootpg = determine_mp_bootpg();
 
 	/* tell u-boot we stole a page */
 	lmb_reserve(lmb, bootpg, 4096);
@@ -31,18 +56,9 @@ void setup_mp(void)
 {
 	extern ulong __secondary_start_page;
 	ulong fixup = (ulong)&__secondary_start_page;
-	u32 bootpg;
+	u32 bootpg = determine_mp_bootpg();
 	u32 bootpg_va;
 
-	/*
-	 * If we have 4G or more of memory, put the boot page at 4Gb-1M.
-	 * Otherwise, put it at the very end of RAM.
-	 */
-	if (gd->ram_size > 0xfffff000)
-		bootpg = 0xfff00000;
-	else
-		bootpg = gd->ram_size - (1024 * 1024);
-
 	if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) {
 		/* We're not covered by the DDR mapping, set up BAT  */
 		write_bat(DBAT7, CONFIG_SYS_SCRATCH_VA | BATU_BL_128K |
@@ -65,4 +81,3 @@ void setup_mp(void)
 		out_be32((uint *)(CONFIG_SYS_CCSRBAR + 0x20), 0x80000000 |
 			 (bootpg >> 12));
 }
-#endif
diff --git a/cpu/mpc86xx/mp.h b/cpu/mpc86xx/mp.h
deleted file mode 100644
index 886e0c839d8..00000000000
--- a/cpu/mpc86xx/mp.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __MPC86XX_MP_H_
-#define __MPC86XX_MP_H_
-
-void setup_mp(void);
-void cpu_mp_lmb_reserve(struct lmb *lmb);
-
-#endif
diff --git a/cpu/mpc86xx/release.S b/cpu/mpc86xx/release.S
index 95efbb4f803..67a6f2bdb57 100644
--- a/cpu/mpc86xx/release.S
+++ b/cpu/mpc86xx/release.S
@@ -41,7 +41,6 @@
  * Core 0 must copy this to a 1M aligned region and set BPTR
  * to point to it.
  */
-#if (CONFIG_NUM_CPUS > 1)
 	.align 12
 .globl __secondary_start_page
 __secondary_start_page:
@@ -166,4 +165,3 @@ invl2:
 	blr
 
 	/* Never Returns, Running in Linux Now */
-#endif