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path: root/drivers/clk/stm32/clk-stm32f.c
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Diffstat (limited to 'drivers/clk/stm32/clk-stm32f.c')
-rw-r--r--drivers/clk/stm32/clk-stm32f.c26
1 files changed, 14 insertions, 12 deletions
diff --git a/drivers/clk/stm32/clk-stm32f.c b/drivers/clk/stm32/clk-stm32f.c
index 4c186419335..d68c75ed201 100644
--- a/drivers/clk/stm32/clk-stm32f.c
+++ b/drivers/clk/stm32/clk-stm32f.c
@@ -522,18 +522,20 @@ static ulong stm32_set_rate(struct clk *clk, ulong rate)
/* get the current PLLSAIR output freq */
pllsair_rate = stm32_clk_get_pllsai_rate(priv, PLLSAIR);
- best_div = pllsair_rate / rate;
-
- /* look into pllsaidivr_table if this divider is available*/
- for (i = 0 ; i < sizeof(pllsaidivr_table); i++)
- if (best_div == pllsaidivr_table[i]) {
- /* set pll_saidivr with found value */
- clrsetbits_le32(&regs->dckcfgr,
- RCC_DCKCFGR_PLLSAIDIVR_MASK,
- pllsaidivr_table[i] <<
- RCC_DCKCFGR_PLLSAIDIVR_SHIFT);
- return rate;
- }
+ if ((pllsair_rate % rate) == 0) {
+ best_div = pllsair_rate / rate;
+
+ /* look into pllsaidivr_table if this divider is available */
+ for (i = 0 ; i < sizeof(pllsaidivr_table); i++)
+ if (best_div == pllsaidivr_table[i]) {
+ /* set pll_saidivr with found value */
+ clrsetbits_le32(&regs->dckcfgr,
+ RCC_DCKCFGR_PLLSAIDIVR_MASK,
+ pllsaidivr_table[i] <<
+ RCC_DCKCFGR_PLLSAIDIVR_SHIFT);
+ return rate;
+ }
+ }
/*
* As no pllsaidivr value is suitable to obtain requested freq,