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-rw-r--r--drivers/spi/renesas_rpc_spi.c10
-rw-r--r--drivers/spi/sh_qspi.c2
-rw-r--r--drivers/spi/spi-sunxi.c34
3 files changed, 39 insertions, 7 deletions
diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c
index 3eb14061c81..8aff2238645 100644
--- a/drivers/spi/renesas_rpc_spi.c
+++ b/drivers/spi/renesas_rpc_spi.c
@@ -203,7 +203,7 @@ static void rpc_spi_flush_read_cache(struct udevice *dev)
static u32 rpc_spi_get_strobe_delay(void)
{
#ifndef CONFIG_RZA1
- u32 cpu_type = rmobile_get_cpu_type();
+ u32 cpu_type = renesas_get_cpu_type();
/*
* NOTE: RPC_PHYCNT_STRTIM value:
@@ -212,11 +212,11 @@ static u32 rpc_spi_get_strobe_delay(void)
* 7: On other R-Car Gen3
* 15: On R-Car Gen4
*/
- if (cpu_type == RMOBILE_CPU_TYPE_R8A7796 && rmobile_get_cpu_rev_integer() == 1)
+ if (cpu_type == RENESAS_CPU_TYPE_R8A7796 && renesas_get_cpu_rev_integer() == 1)
return RPC_PHYCNT_STRTIM(6);
- else if (cpu_type == RMOBILE_CPU_TYPE_R8A779F0 ||
- cpu_type == RMOBILE_CPU_TYPE_R8A779G0 ||
- cpu_type == RMOBILE_CPU_TYPE_R8A779H0)
+ else if (cpu_type == RENESAS_CPU_TYPE_R8A779F0 ||
+ cpu_type == RENESAS_CPU_TYPE_R8A779G0 ||
+ cpu_type == RENESAS_CPU_TYPE_R8A779H0)
return RPC_PHYCNT_STRTIM2(15);
else
#endif
diff --git a/drivers/spi/sh_qspi.c b/drivers/spi/sh_qspi.c
index 7dd1fe75e04..72594993853 100644
--- a/drivers/spi/sh_qspi.c
+++ b/drivers/spi/sh_qspi.c
@@ -13,7 +13,7 @@
#include <malloc.h>
#include <spi.h>
#include <wait_bit.h>
-#include <asm/arch/rmobile.h>
+#include <asm/arch/renesas.h>
#include <asm/io.h>
#include <linux/bitops.h>
diff --git a/drivers/spi/spi-sunxi.c b/drivers/spi/spi-sunxi.c
index c56d82d998a..9ec6b359e22 100644
--- a/drivers/spi/spi-sunxi.c
+++ b/drivers/spi/spi-sunxi.c
@@ -117,6 +117,8 @@ enum sun4i_spi_bits {
SPI_TCR_XCH,
SPI_TCR_CS_MANUAL,
SPI_TCR_CS_LEVEL,
+ SPI_TCR_SDC,
+ SPI_TCR_SDM,
SPI_FCR_TF_RST,
SPI_FCR_RF_RST,
SPI_FSR_RF_CNT_MASK,
@@ -128,6 +130,7 @@ struct sun4i_spi_variant {
u32 fifo_depth;
bool has_soft_reset;
bool has_burst_ctl;
+ bool has_clk_ctl;
};
struct sun4i_spi_plat {
@@ -302,7 +305,19 @@ static int sun4i_spi_claim_bus(struct udevice *dev)
setbits_le32(SPI_REG(priv, SPI_TCR), SPI_BIT(priv, SPI_TCR_CS_MANUAL) |
SPI_BIT(priv, SPI_TCR_CS_ACTIVE_LOW));
- sun4i_spi_set_speed_mode(dev->parent);
+ if (priv->variant->has_clk_ctl) {
+ sun4i_spi_set_speed_mode(dev->parent);
+ } else {
+ /*
+ * At this moment there is no ability to change input clock.
+ * Therefore, we can only use default HOSC@24MHz clock and
+ * set SPI sampling mode to normal
+ */
+ clrsetbits_le32(SPI_REG(priv, SPI_TCR),
+ SPI_BIT(priv, SPI_TCR_SDC) |
+ SPI_BIT(priv, SPI_TCR_SDM),
+ SPI_BIT(priv, SPI_TCR_SDM));
+ }
return 0;
}
@@ -516,6 +531,8 @@ static const u32 sun6i_spi_bits[] = {
[SPI_TCR_CS_MASK] = 0x30,
[SPI_TCR_CS_MANUAL] = BIT(6),
[SPI_TCR_CS_LEVEL] = BIT(7),
+ [SPI_TCR_SDC] = BIT(11),
+ [SPI_TCR_SDM] = BIT(13),
[SPI_TCR_XCH] = BIT(31),
[SPI_FCR_RF_RST] = BIT(15),
[SPI_FCR_TF_RST] = BIT(31),
@@ -526,6 +543,7 @@ static const struct sun4i_spi_variant sun4i_a10_spi_variant = {
.regs = sun4i_spi_regs,
.bits = sun4i_spi_bits,
.fifo_depth = 64,
+ .has_clk_ctl = true,
};
static const struct sun4i_spi_variant sun6i_a31_spi_variant = {
@@ -534,6 +552,7 @@ static const struct sun4i_spi_variant sun6i_a31_spi_variant = {
.fifo_depth = 128,
.has_soft_reset = true,
.has_burst_ctl = true,
+ .has_clk_ctl = true,
};
static const struct sun4i_spi_variant sun8i_h3_spi_variant = {
@@ -542,6 +561,15 @@ static const struct sun4i_spi_variant sun8i_h3_spi_variant = {
.fifo_depth = 64,
.has_soft_reset = true,
.has_burst_ctl = true,
+ .has_clk_ctl = true,
+};
+
+static const struct sun4i_spi_variant sun50i_r329_spi_variant = {
+ .regs = sun6i_spi_regs,
+ .bits = sun6i_spi_bits,
+ .fifo_depth = 64,
+ .has_soft_reset = true,
+ .has_burst_ctl = true,
};
static const struct udevice_id sun4i_spi_ids[] = {
@@ -557,6 +585,10 @@ static const struct udevice_id sun4i_spi_ids[] = {
.compatible = "allwinner,sun8i-h3-spi",
.data = (ulong)&sun8i_h3_spi_variant,
},
+ {
+ .compatible = "allwinner,sun50i-r329-spi",
+ .data = (ulong)&sun50i_r329_spi_variant,
+ },
{ /* sentinel */ }
};