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-rw-r--r--drivers/serial/serial_zynq.c4
1 files changed, 0 insertions, 4 deletions
diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c
index 050b9c06259..ff28f3c8019 100644
--- a/drivers/serial/serial_zynq.c
+++ b/drivers/serial/serial_zynq.c
@@ -21,10 +21,6 @@
#define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */
-/* Some clock/baud constants */
-#define ZYNQ_UART_BDIV 15 /* Default/reset BDIV value */
-#define ZYNQ_UART_BASECLK 3125000L /* master / (bdiv + 1) */
-
struct uart_zynq {
u32 control; /* Control Register [8:0] */
u32 mode; /* Mode Register [10:0] */