diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/mtd/nand/raw/stm32_fmc2_nand.c | 3 | ||||
-rw-r--r-- | drivers/pinctrl/pinctrl_stm32.c | 19 | ||||
-rw-r--r-- | drivers/ram/stm32mp1/stm32mp1_interactive.c | 2 | ||||
-rw-r--r-- | drivers/spi/stm32_qspi.c | 27 |
4 files changed, 22 insertions, 29 deletions
diff --git a/drivers/mtd/nand/raw/stm32_fmc2_nand.c b/drivers/mtd/nand/raw/stm32_fmc2_nand.c index fb3279b405e..69dbb629e93 100644 --- a/drivers/mtd/nand/raw/stm32_fmc2_nand.c +++ b/drivers/mtd/nand/raw/stm32_fmc2_nand.c @@ -735,6 +735,9 @@ static int stm32_fmc2_nfc_setup_interface(struct mtd_info *mtd, int chipnr, if (IS_ERR(sdrt)) return PTR_ERR(sdrt); + if (sdrt->tRC_min < 30000) + return -EOPNOTSUPP; + if (chipnr == NAND_DATA_IFACE_CHECK_ONLY) return 0; diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index b755fa42b4f..b06da50b2cd 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -61,6 +61,13 @@ static const char * const pinmux_otype[] = { [STM32_GPIO_OTYPE_OD] = "open-drain", }; +static const char * const pinmux_speed[] = { + [STM32_GPIO_SPEED_2M] = "Low speed", + [STM32_GPIO_SPEED_25M] = "Medium speed", + [STM32_GPIO_SPEED_50M] = "High speed", + [STM32_GPIO_SPEED_100M] = "Very-high speed", +}; + static int stm32_pinctrl_get_af(struct udevice *dev, unsigned int offset) { struct stm32_gpio_priv *priv = dev_get_priv(dev); @@ -201,6 +208,7 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev, int af_num; unsigned int gpio_idx; u32 pupd, otype; + u8 speed; /* look up for the bank which owns the requested pin */ gpio_dev = stm32_pinctrl_get_gpio_dev(dev, selector, &gpio_idx); @@ -214,6 +222,7 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev, priv = dev_get_priv(gpio_dev); pupd = (readl(&priv->regs->pupdr) >> (gpio_idx * 2)) & PUPD_MASK; otype = (readl(&priv->regs->otyper) >> gpio_idx) & OTYPE_MSK; + speed = (readl(&priv->regs->ospeedr) >> gpio_idx * 2) & OSPEED_MASK; switch (mode) { case GPIOF_UNKNOWN: @@ -222,13 +231,15 @@ static int stm32_pinctrl_get_pin_muxing(struct udevice *dev, break; case GPIOF_FUNC: af_num = stm32_pinctrl_get_af(gpio_dev, gpio_idx); - snprintf(buf, size, "%s %d %s %s", pinmux_mode[mode], af_num, - pinmux_otype[otype], pinmux_bias[pupd]); + snprintf(buf, size, "%s %d %s %s %s", pinmux_mode[mode], af_num, + pinmux_otype[otype], pinmux_bias[pupd], + pinmux_speed[speed]); break; case GPIOF_OUTPUT: - snprintf(buf, size, "%s %s %s %s", + snprintf(buf, size, "%s %s %s %s %s", pinmux_mode[mode], pinmux_otype[otype], - pinmux_bias[pupd], label ? label : ""); + pinmux_bias[pupd], label ? label : "", + pinmux_speed[speed]); break; case GPIOF_INPUT: snprintf(buf, size, "%s %s %s", pinmux_mode[mode], diff --git a/drivers/ram/stm32mp1/stm32mp1_interactive.c b/drivers/ram/stm32mp1/stm32mp1_interactive.c index f0fe7e61e33..2c19847c663 100644 --- a/drivers/ram/stm32mp1/stm32mp1_interactive.c +++ b/drivers/ram/stm32mp1/stm32mp1_interactive.c @@ -391,7 +391,7 @@ bool stm32mp1_ddr_interactive(void *priv, if (next_step < 0) return false; - if (step < 0 || step > ARRAY_SIZE(step_str)) { + if (step < 0 || step >= ARRAY_SIZE(step_str)) { printf("** step %d ** INVALID\n", step); return false; } diff --git a/drivers/spi/stm32_qspi.c b/drivers/spi/stm32_qspi.c index 90c207d5184..eb52ff73b23 100644 --- a/drivers/spi/stm32_qspi.c +++ b/drivers/spi/stm32_qspi.c @@ -115,15 +115,8 @@ struct stm32_qspi_regs { #define STM32_BUSY_TIMEOUT_US 100000 #define STM32_ABT_TIMEOUT_US 100000 -struct stm32_qspi_flash { - u32 cr; - u32 dcr; - bool initialized; -}; - struct stm32_qspi_priv { struct stm32_qspi_regs *regs; - struct stm32_qspi_flash flash[STM32_QSPI_MAX_CHIP]; void __iomem *mm_base; resource_size_t mm_size; ulong clock_rate; @@ -407,25 +400,11 @@ static int stm32_qspi_claim_bus(struct udevice *dev) return -ENODEV; if (priv->cs_used != slave_cs) { - struct stm32_qspi_flash *flash = &priv->flash[slave_cs]; - priv->cs_used = slave_cs; - if (flash->initialized) { - /* Set the configuration: speed + cs */ - writel(flash->cr, &priv->regs->cr); - writel(flash->dcr, &priv->regs->dcr); - } else { - /* Set chip select */ - clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL, - priv->cs_used ? STM32_QSPI_CR_FSEL : 0); - - /* Save the configuration: speed + cs */ - flash->cr = readl(&priv->regs->cr); - flash->dcr = readl(&priv->regs->dcr); - - flash->initialized = true; - } + /* Set chip select */ + clrsetbits_le32(&priv->regs->cr, STM32_QSPI_CR_FSEL, + priv->cs_used ? STM32_QSPI_CR_FSEL : 0); } setbits_le32(&priv->regs->cr, STM32_QSPI_CR_EN); |